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71. 发明授权

US4916088A Method of making a low dislocation density semiconductor device 失效
标题翻译：制造低位错密度半导体器件的方法
公开(公告)号：US4916088A
公开(公告)日：1990-04-10
申请号：US187939
申请日：1988-04-29
申请人： John B. Mooney , Arden Sher
发明人： John B. Mooney , Arden Sher
IPC分类号： H01L21/20
CPC分类号： H01L21/0262 , H01L21/02381 , H01L21/02395 , H01L21/0245 , H01L21/02463 , H01L21/02502 , H01L21/02546 , H01L21/02658 , Y10S148/015 , Y10S148/04 , Y10S148/072 , Y10S148/097 , Y10S438/938
摘要： A low dislocation density semiconductor device includes a first semiconductor layer of a III-V or II-VI semiconductor compound and alloying atoms on a non-metal substrate. The semiconductor compound usually has a large dislocation density. A predetermined position of the alloying atoms in the compound lattice structure can substantially reduce the compound dislocation density. Energy is applied to the alloying atoms so they are at the predetermined positions. The number of alloying atoms causes the semiconductor compound solubility limit to be exceeded. The layer is formed on a substrate of the III-V or II-VI semiconductor, such as gallium arsenide or another semiconductor, such as silicon or on an insulator such as sapphire. In the latter cases, the layer is formed on an intermediate layer having a lattice constant between that of the substrate and semiconductor compound. A second layer is epitaxially deposited on the first layer so both layers have virtually the same lattice constant and dislocation density. The alloying atoms are deposited by different energy assist methods, e.g. by an ion beam that irradiates the substrate, or by an energy assisted organometallic chemical vapor deposition process. The energy assist can be by ionization or optical irradiation causing topical heating of surface atoms deposited by the OMCVD process, without heating of the substrate or the underlying atoms. If the ion beam process is employed, the substrate is annealed such that the alloying atoms move from initial random locations thereof in the compound lattice to the predetermined locations.
摘要翻译：低位错密度半导体器件包括III-V或II-VI半导体化合物的第一半导体层和非金属衬底上的合金原子。半导体化合物通常具有大的位错密度。复合晶格结构中的合金原子的预定位置可以显着降低复合位错密度。能量被施加到合金原子上，使得它们处于预定位置。合金原子的数量导致超过半导体化合物溶解度极限。该层形成在III-V或II-VI半导体的衬底上，例如砷化镓或诸如硅之类的另一半导体，或者在诸如蓝宝石的绝缘体上。在后一种情况下，该层形成在晶格常数在基板和半导体化合物之间的中间层上。第二层被外延沉积在第一层上，因此两层具有几乎相同的晶格常数和位错密度。合金原子通过不同的能量辅助方法沉积，例如通过照射衬底的离子束，或通过能量辅助的有机金属化学气相沉积工艺。能量辅助可以通过电离或光照射引起局部加热由OMCVD工艺沉积的表面原子，而不加热底物或下面的原子。如果使用离子束工艺，则将衬底退火，使得合金原子从复合晶格中的初始随机位置移动到预定位置。

72. 发明授权

US4897367A Process for growing gallium arsenide on silicon substrate 失效
标题翻译：在硅衬底上生长砷化镓的工艺
公开(公告)号：US4897367A
公开(公告)日：1990-01-30
申请号：US324880
申请日：1989-03-17
申请人： Kazuto Ogasawara
发明人： Kazuto Ogasawara
IPC分类号： C30B1/02 , C30B29/42 , H01L21/20 , H01L21/203 , H01L21/324
CPC分类号： H01L21/02513 , H01L21/02381 , H01L21/02433 , H01L21/0245 , H01L21/02463 , H01L21/02505 , H01L21/02546 , H01L21/02631 , Y10S148/025 , Y10S148/072 , Y10S148/097 , Y10S148/149 , Y10S438/933 , Y10S438/938
摘要： A GaAs layer having a high crystallinity can be grown over an Si substrate without warping, by process for growing a GaAs layer on an Si substrate, said process comprising: forming a first GaAs layer in the amorphous state on the Si substrate at a first temperature, the first GaAs layer being formed with a thickness allowing formation of a single crystalline layer having a thickness of one to three monomolecular layers; heating the first GaAs layer to change the amorphous state of the first GaAs layer to a single crystalline state; forming an Si layer on the first GaAs layer at a second temperature higher than the first temperature, the Si layer being formed with a thickness having one to six monoatomic layers; forming a second GaAs layer in the amorphous state on the Si layer at the first temperature, the second GaAs layer being formed with a thickness substantially the same as the thickness of the first GaAs layer; heating the second GaAs layer the change the amorphous state of the second GaAs layer to a single crystalline state; and epitaxially growing a third GaAs layer on the second GaAs layer.
摘要翻译：通过在Si衬底上生长GaAs层的工艺，可以在Si衬底上生长具有高结晶度的GaAs层，而不会翘曲，所述方法包括：在第一温度下在Si衬底上形成处于非晶态的第一GaAs层形成第一GaAs层，其厚度允许形成厚度为一至三个单分子层的单晶层; 加热第一GaAs层以将第一GaAs层的非晶态改变为单晶态; 在高于第一温度的第二温度下在第一GaAs层上形成Si层，所述Si层形成为具有一至六个单原子层的厚度; 在所述第一温度下在所述Si层上形成非晶状态的第二GaAs层，所述第二GaAs层形成为与所述第一GaAs层的厚度基本相同的厚度; 加热第二GaAs层将第二GaAs层的非晶态改变为单晶态; 并在第二GaAs层上外延生长第三GaAs层。

73. 发明授权

US4830984A Method for heteroepitaxial growth using tensioning layer on rear substrate surface 失效
标题翻译：使用后衬底表面上的张紧层进行异质外延生长的方法
公开(公告)号：US4830984A
公开(公告)日：1989-05-16
申请号：US220917
申请日：1988-07-18
申请人： Andrew J. Purdes
发明人： Andrew J. Purdes
IPC分类号： H01L21/20
CPC分类号： H01L21/02381 , H01L21/02546 , H01L21/02658 , H01L29/7842 , Y10S148/056 , Y10S148/072 , Y10S148/097 , Y10S148/149 , Y10S438/933 , Y10S438/938
摘要： A method, and products formed by such method, of providing a substantially planar surface to a layer of semiconducting material (24) formed on a first surface of a substrate (20), the substrate having a second surface opposite the first surface. The method comprising forming a layer (22) of a first material on the second surface of the substrate; forming a layer of the semiconducting material (24) on the first surface of the substrate; whereby said layer of said first material exerts a tensioning force on said second surface of the substrate (20) which countereffects a tensioning force exerted on said first surface of said substrate by said layer of semiconductor material (24) so that said first surface of said substrate has a substantially planar form. In some embodiments tensioning forces arise due to differential thermal expansion of said first material and said substrate and said semiconductor material and said substrate.
摘要翻译：一种方法以及通过这种方法形成的产品，在基板（20）的第一表面上形成的半导体材料层（24）提供基本平坦的表面，该基板具有与第一表面相对的第二表面。所述方法包括在所述基板的第二表面上形成第一材料层（22）; 在衬底的第一表面上形成半导体材料层（24）; 其中所述第一材料的所述层在所述衬底（20）的所述第二表面上施加张力，所述第二表面对由所述半导体材料层（24）施加在所述衬底的所述第一表面上的张力作用，使得所述第一表面的所述第一表面衬底具有基本上平面的形式。在一些实施例中，由于所述第一材料和所述衬底以及所述半导体材料和所述衬底的不同的热膨胀，产生张紧力。

74. 发明授权

US4820650A Introducing lattice defect with ice particles in semiconductor wafer 失效
标题翻译：在半导体晶片中引入具有冰颗粒的晶格缺陷
公开(公告)号：US4820650A
公开(公告)日：1989-04-11
申请号：US121357
申请日：1987-11-16
申请人： Akemi Nagae , Shinichi Satou , Takaaki Fukumoto , Toshiaki Ohmori
发明人： Akemi Nagae , Shinichi Satou , Takaaki Fukumoto , Toshiaki Ohmori
IPC分类号： H01L21/322 , H01L21/463
CPC分类号： H01L21/3221 , Y10S438/938
摘要： The invention employs ice for introducing lattice defect into a semiconductor wafer, and is constructed to introduce particles of ice into the semiconductor wafer by ionizing (24) and accelerating (25) the particles of ice, whereby backside damage can be provided on the semiconductor wafer without leaving a pollutant source of the semiconductor wafer.
摘要翻译：本发明采用冰将晶格缺陷引入到半导体晶片中，并通过离子化（24）并加速（25）冰颗粒，将冰颗粒引入半导体晶片，由此可以在半导体晶片上提供背面损伤而不会留下半导体晶片的污染源。

75. 发明授权

US4806996A Dislocation-free epitaxial layer on a lattice-mismatched porous or otherwise submicron patterned single crystal substrate 失效
标题翻译：在晶格失配的多孔或其他亚微米图案化单晶衬底上的无位错外延层
公开(公告)号：US4806996A
公开(公告)日：1989-02-21
申请号：US186739
申请日：1988-04-25
申请人： Sergey Luryi
发明人： Sergey Luryi
IPC分类号： H01L21/20 , H01L29/161 , H01L29/06 , H01L29/34
CPC分类号： H01L21/02381 , H01L21/02428 , H01L21/0243 , H01L21/02521 , H01L21/02532 , H01L21/02543 , H01L21/02546 , Y10S117/913 , Y10S438/933 , Y10S438/938 , Y10S438/96
摘要： Dislocation-free epitaxial layers on the surfaces of lattice mismatched single crystal substrates, such as germanium or gallium arsenide on silicon, can be grown provided the surfaces are suitably patterned, such as castellated or porous.
摘要翻译：可以生长晶格失配的单晶衬底（如硅上的锗或砷化镓）的表面上的无位错的外延层，只要这些表面适当地构图，例如铸造或多孔的。

76. 发明授权

US4793872A III-V Compound heteroepitaxial 3-D semiconductor structures utilizing superlattices 失效
标题翻译： III-V利用超晶格的复合异质外延三维半导体结构
公开(公告)号：US4793872A
公开(公告)日：1988-12-27
申请号：US21684
申请日：1987-03-04
申请人： Paul L. Meunier , Manijeh Razeghi
发明人： Paul L. Meunier , Manijeh Razeghi
IPC分类号： G02B6/12 , G02F1/05 , H01L21/20 , H01L21/822 , H01L31/10 , H01L33/00 , H01S5/00 , H01L27/14 , H01L29/161
CPC分类号： H01L21/8221 , H01L21/0237 , H01L21/02461 , H01L21/02546 , Y10S148/065 , Y10S148/072 , Y10S148/097 , Y10S148/11 , Y10S148/16 , Y10S148/164 , Y10S438/938 , Y10S438/967
摘要： A component of semiconductor material deposited by epitaxial growth on a substrate having a predetermined and different lattice parameter consists of an alternate succession of layers of a first type and layers of a second type deposited on the substrate. The lattice parameter of the first type of layers is substantially matched with the lattice parameter of the substrate. In the case of the second type of layers, the lattice parameter is matched and even equal to that of the first type of layers. A component having a lattice parameter equal to that of the second type of layers is formed on the last layer of the second type. Moreover, the energy gaps of the two types of layers are different.
摘要翻译：通过外延生长沉积在具有预定和不同晶格参数的衬底上的半导体材料的部件由沉积在衬底上的第一类型的层和第二类层组成。第一类型的层的晶格参数基本上与衬底的晶格参数匹配。在第二类型层的情况下，晶格参数匹配并且甚至等于第一类型的层。具有等于第二类型层的晶格参数的分量形成在第二类型的最后层上。此外，两种类型的层的能隙是不同的。

77. 发明授权

US4137103A Silicon integrated circuit region containing implanted arsenic and germanium 失效
标题翻译：硅集成电路区域包含植入砷和锗
公开(公告)号：US4137103A
公开(公告)日：1979-01-30
申请号：US908322
申请日：1978-05-22
申请人： Siegfried R. Mader , Burton J. Masters , H. Bernhard Pogge
发明人： Siegfried R. Mader , Burton J. Masters , H. Bernhard Pogge
IPC分类号： H01L21/265 , H01L29/167 , H01L21/203
CPC分类号： H01L21/26513 , H01L21/26506 , H01L29/167 , Y10S148/024 , Y10S148/061 , Y10S438/938
摘要： A method for forming N conductivity-type regions in a silicon substrate comprising ion implanting arsenic to form a region in said substrate having an arsenic atom concentration of at least 1 .times. 10.sup.-2 As atoms/total atoms in substrate, and ion implanting germanium into said substrate region. Even though the atomic radius of arsenic is very close to that of silicon -- the arsenic radius is only 0.5% smaller -- when high arsenic atom concentrations of at least 1 .times. 10.sup.-2 atoms/total atoms in the substrate are introduced in the substrate, and such high concentrations are only possible when arsenic is ion implanted, then atomic misfit dislocations will occur. The implanted germanium atoms compensate for the lattice strain in the silicon to minimize dislocations.

78. 发明授权

US4111719A Minimization of misfit dislocations in silicon by double implantation of arsenic and germanium 失效
标题翻译：通过阿根廷和德国的双重植入来最小化硅中的杂质错位
公开(公告)号：US4111719A
公开(公告)日：1978-09-05
申请号：US748035
申请日：1976-12-06
申请人： Siegfried R. Mader , Burton J. Masters , H. Bernhard Pogge
发明人： Siegfried R. Mader , Burton J. Masters , H. Bernhard Pogge
IPC分类号： H01L21/265 , H01L29/167 , H01L9/10
CPC分类号： H01L21/26513 , H01L21/26506 , H01L29/167 , Y10S148/024 , Y10S148/061 , Y10S438/938
摘要： A method for forming N conductivity-type regions in a silicon substrate comprising ion implanting arsenic to form a region in said substrate having an arsenic atom concentration of at least 1 .times. 10.sup.-2 As atoms/total atoms in substrate, and ion implanting germanium into said substrate region. Even though the atomic radius of arsenic is very close to that of silicon -- the arsenic radius is only 0.5% smaller -- when high arsenic atom concentrations of at least 1 .times. 10.sup.-2 atoms/total atoms in the substrate are introduced in the substrate, and such high concentrations are only possible when arsenic is ion implanted, then atomic misfit dislocations will occur. The implanted germanium atoms compensate for the lattice strain in the silicon to minimize dislocations.
摘要翻译：一种用于在硅衬底中形成N导电型区域的方法，其包括离子注入砷以形成所述衬底中的砷原子浓度至少为1×10 -2 As原子/底物中的总原子，并将离子注入锗所述衬底区域。尽管砷的原子半径非常接近于硅的原子半径 - 砷的半径只有0.5％ - 当基片中至少有1×10-2个原子/总原子的高砷原子浓度被引入到底物，并且这样高的浓度仅在砷被离子注入时才可能，则将发生原子失配位错。植入的锗原子补偿硅中的晶格应变以最小化位错。

79. 发明授权

US3963539A Two stage heteroepitaxial deposition process for GaAsP/Si LED's 失效
标题翻译： GaAsP / Si LED的两级异质外延沉积工艺（3 s
公开(公告)号：US3963539A
公开(公告)日：1976-06-15
申请号：US533590
申请日：1974-12-17
申请人： Bernard M. Kemlage , Jerry M. Woodall , William C. Wuestenhoefer
发明人： Bernard M. Kemlage , Jerry M. Woodall , William C. Wuestenhoefer
IPC分类号： H01L21/205 , H01L33/00
CPC分类号： H01L21/0262 , H01L21/02381 , H01L21/02461 , H01L21/02463 , H01L21/02502 , H01L21/0251 , H01L21/02543 , H01L21/02546 , H01L33/00 , Y10S148/025 , Y10S148/059 , Y10S148/067 , Y10S148/072 , Y10S148/119 , Y10S438/933 , Y10S438/938
摘要： A process for producing light emitting diodes is disclosed. In the process a primer layer of GaP is pyrolytically deposited on a Si substrate with the resulting epitaxial film thickness being sufficient to form complete coalescence of the epitaxial nuclei, but thin enough to avoid cracks in the epitaxial layer due to stress induced by thermal expansion. The thickness is generally between 1-2.mu. . A second layer of GaP is then deposited using the standard halide transport process with thicknesses of 10-20.mu. with the graded addition of AsH.sub.3, until the particularly desired design composition of GaAsP is obtained. A constant layer of GaAsP is grown on the graded layer.
摘要翻译：公开了一种制造发光二极管的方法。在该过程中，GaP的底漆层热解沉积在Si衬底上，所得到的外延膜厚度足以形成外延核的完全聚结，但足够薄以避免由于热膨胀引起的应力引起的外延层中的裂纹。厚度一般在1-2亩之间。然后使用标准的卤化物传输工艺沉积第二层GaP，厚度为10-20微米，分级加入AsH 3，直到获得特别期望的GaAsP设计组成。在等级层上生长GaAsP的恒定层。

80. 发明授权

US3963538A Two stage heteroepitaxial deposition process for GaP/Si 失效
标题翻译： GaP / Si两相异质外延沉积工艺
公开(公告)号：US3963538A
公开(公告)日：1976-06-15
申请号：US533604
申请日：1974-12-17
申请人： Robert W. Broadie , Bernard M. Kemlage , H. Bernard Pogge
发明人： Robert W. Broadie , Bernard M. Kemlage , H. Bernard Pogge
IPC分类号： H01L21/205 , H01L33/00
CPC分类号： H01L21/02381 , H01L21/02461 , H01L21/02463 , H01L21/02505 , H01L21/0251 , H01L21/02543 , H01L21/02546 , H01L21/0262 , H01L33/00 , Y10S148/025 , Y10S148/059 , Y10S148/067 , Y10S148/072 , Y10S148/119 , Y10S438/933 , Y10S438/938
摘要： A process for producing light emitting diodes is disclosed. In the process a primer layer of GaP is pyrolytically deposited on a Si substrate with the resulting epitaxial film thickness being sufficient to form complete coalescence of the epitaxial nuclei, but thin enough to avoid cracks in the epitaxial layer due to stress induced by thermal expansion. The thickness is generally between 0.1-10.mu.. A second layer of GaP is then deposited using the standard halide transport process with thicknesses of 2-5 .mu. or higher. In the case of GaP LED's the thickness is about 10-40 .mu., whereas for the case of GaAsP LED's the GaP thickness is 2-5 .mu. and this is then followed, through the addition of AsH.sub.3, with GaAsP graded from the GaP composition to the particularly desired design composition. The final composition is then maintained for 10-20 .mu..
摘要翻译：公开了一种制造发光二极管的方法。在该过程中，GaP的底漆层热解沉积在Si衬底上，所得到的外延膜厚度足以形成外延核的完全聚结，但足够薄以避免由于热膨胀引起的应力引起的外延层中的裂纹。厚度通常在0.1-10亩之间。然后使用厚度为2-5μm或更高的标准卤化物传输工艺沉积第二层GaP。在GaP LED的厚度约为10-40微米的情况下，而GaAsP LED的GaP厚度为2-5微米，然后通过加入AsH3，GaP组分分级为GaAsP 特别期望的设计组合。然后将最终组合物保持10-20亩。

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