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71. 发明授权

US09772845B2 Method and apparatus to process KECCAK secure hashing algorithm 有权
公开(公告)号：US09772845B2
公开(公告)日：2017-09-26
申请号：US13976184
申请日：2011-12-13
申请人： Kirk S. Yap , Gilbert M. Wolrich , James D. Guilford , Vinodh Gopal , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
发明人： Kirk S. Yap , Gilbert M. Wolrich , James D. Guilford , Vinodh Gopal , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
IPC分类号： G06F9/30 , H04L9/06
CPC分类号： G06F9/30145 , H04L9/0643 , H04L2209/122
摘要： A processor includes a plurality of registers, an instruction decoder to receive an instruction to process a KECCAK state cube of data representing a KECCAK state of a KECCAK hash algorithm, to partition the KECCAK state cube into a plurality of subcubes, and to store the subcubes in the plurality of registers, respectively, and an execution unit coupled to the instruction decoder to perform the KECCAK hash algorithm on the plurality of subcubes respectively stored in the plurality of registers in a vector manner.

72. 发明授权

US09734065B2 Method of managing consistency of caches 有权
公开(公告)号：US09734065B2
公开(公告)日：2017-08-15
申请号：US14916915
申请日：2014-09-05
申请人： SAGEM DEFENSE SECURITE
发明人： Christian Valpard
IPC分类号： H03M13/00 , G06F12/0817 , H04L9/06 , G06F11/10 , G06F12/0811 , G06F12/14 , G06F13/16 , H04L9/30 , H04L9/32
CPC分类号： G06F12/0824 , G06F11/1004 , G06F12/0811 , G06F12/1408 , G06F13/1663 , G06F2212/1052 , G06F2212/283 , G06F2212/621 , H04L9/0656 , H04L9/0662 , H04L9/304 , H04L2209/122 , H04L2209/127 , H04L2209/34
摘要： The present invention relates to a method of transmitting a message comprising an integrity check and a header, between two processing units via a shared memory, comprising steps of: —generation (501), by a first processing unit, of a first pseudorandom binary string; —encryption (502) of the message to be transmitted by applying an involutive transformation dependent on the first pseudorandom binary string generated; —transmission and storage (503) of the encrypted message in the shared memory; —generation (504), by the second processing unit, of a second pseudorandom binary string; —decryption of the message stored by applying an involutive transformation dependent on the second pseudorandom binary string, and by decrypting the header (505) of said message, by verifying the decrypted header (505), and as a function of the result of the verification, by decrypting the complete message (506); —verification (507) of the integrity of the decrypted message on the basis of its integrity check.

73. 发明授权

US09722805B2 Integrated security device and signal processing method used for an integrated security device 有权
公开(公告)号：US09722805B2
公开(公告)日：2017-08-01
申请号：US14651130
申请日：2012-12-11
申请人： Daisuke Suzuki
发明人： Daisuke Suzuki
IPC分类号： H04L12/00 , H04L9/32 , G09C1/00 , H04L9/08
CPC分类号： H04L9/3278 , G09C1/00 , H04L9/0866 , H04L2209/122
摘要： An integrated security device, including: an encryption/decoding processing unit for executing processing necessary for authentication by using a logic circuit that forms an encryption/decoding function; a selector for selecting signals whose number corresponds to a specific number of lines from among signals from a plurality of intermediate nodes of the logic circuit in accordance with a selection signal; and a signal processing unit having a function of detecting a glitch caused by the signals corresponding to the specific number of lines, for implementing both a function of generating a physical random number and a function of generating a device identifier by a physical characteristic based on the glitch detected by switch-selecting the signals corresponding to the specific number of lines.

74. 发明授权

US09667410B2 Semiconductor device 有权
公开(公告)号：US09667410B2
公开(公告)日：2017-05-30
申请号：US14844175
申请日：2015-09-03
申请人： Renesas Electronics Corporation
发明人： Daisuke Oshida
IPC分类号： H04L29/06 , H04L9/00 , G06F21/72 , G06F21/55 , G06F21/71 , G09C1/00 , H04L9/06
CPC分类号： H04L9/002 , G06F21/554 , G06F21/71 , G09C1/00 , H04L9/003 , H04L9/0631 , H04L2209/122 , H04L2209/125 , H04L2209/46
摘要： In data processing including high-speed cipher calculation for which it is not appropriate to employ a leveling technique, tamper resistance is improved against an attack to a specific position performed by knowing a layout of functional blocks in a semiconductor chip. Examples of the attack include micro-probing, fault injection, and electromagnetic wave analysis.A semiconductor device, in which a plurality of IC chips that perform the same cipher calculation in parallel are laminated or stacked, performs data processing including the cipher calculation. A chip that compares and verifies results of the cipher calculations performed by the plurality of chips is laminated in an intermediate layer whose element surface is covered by another chip. For example, when three chips are laminated, a chip in the intermediate layer sandwiched by the upper layer and the lower layer has a comparative verification function.

75. 发明申请

US20170091148A1 METHOD FOR CALCULATING ELLIPTIC CURVE SCALAR MULTIPLICATION 审中-公开
公开(公告)号：US20170091148A1
公开(公告)日：2017-03-30
申请号：US15126699
申请日：2014-09-26
申请人： Hitachi, Ltd.
发明人： Masashi TAKAHASHI
IPC分类号： G06F17/16 , G06F7/72
CPC分类号： G06F17/16 , G06F7/722 , G06F7/725 , G09C1/00 , H04L9/3066 , H04L9/3252 , H04L2209/122
摘要： An elliptic curve scalar multiplication apparatus stores a prime number p and information of a first point, the prime number p defining a field of definition Fp, which defines a first curve, which is a Weierstrass form elliptic curve, and expressed as p=p0+p1c+ . . . +p1cn−1, (where c equals 2f and f is an integer equal to or larger than 1 that is units of breaking data into pieces in multiple-precision integer arithmetic executed by the elliptic curve scalar multiplication apparatus), calculates a Montgomery constant k0, work, and h1, executes doubling of a second point, which is calculated from the first point, by Montgomery multiplication that uses k0, work, and h1, adds a third point and fourth point, which are calculated from the first point, by Montgomery multiplication that uses k0, work, and h1; and calculates a scalar multiple of the first point, based on a result of the doubling and the addition.

76. 发明申请

US20160277181A1 Method and System for High-Efficiency Self-Adaptive Modular Data Encryption 审中-公开
标题翻译：高效自适应模块化数据加密方法与系统
公开(公告)号：US20160277181A1
公开(公告)日：2016-09-22
申请号：US15069975
申请日：2014-05-04
申请人： Wai Chuen WONG , Kin Man YUNG , Shaohua XIANG
发明人： WAI CHUEN WONG , KIN MAN YUNG , SHAOHUA XIANG
IPC分类号： H04L9/06 , G09C1/00
CPC分类号： H04L9/0637 , G09C1/00 , H04L2209/122
摘要： A method for high-efficiency self-adaptive modular data encryption is provided. The method includes: acquiring sizes of file blocks of an operating system, an application program and a document system; adjusting a size of a self-adaptive encrypted data block according to the sizes of the file blocks; partitioning data into a plurality of data blocks; and encrypting the data blocks according to the size of the self-adaptive encrypted data block. A system for high-efficiency self-adaptive modular data encryption is also provided. In encryption and decryption processes, partitioning of data blocks is directly related to data processing speed and efficiency. The self-adaptive system of the present invention is configured to partition data blocks and to automatically adjust and match sizes of encrypted blocks according to the operation system, the application program and the document system environment, thereby greatly improving the speed and efficiency of data encryption and decryption processes.
摘要翻译：提供了一种高效率自适应模块化数据加密方法。该方法包括：获取操作系统，应用程序和文档系统的文件块的大小; 根据文件块的大小调整自适应加密数据块的大小; 将数据分割成多个数据块; 并根据自适应加密数据块的大小加密数据块。还提供了一种用于高效自适应模块化数据加密的系统。在加密和解密过程中，数据块的划分与数据处理速度和效率直接相关。本发明的自适应系统被配置为根据操作系统，应用程序和文档系统环境来划分数据块并自动调整和匹配加密块的大小，从而大大提高数据加密的速度和效率和解密过程。

77. 发明授权

US09389855B2 Arithmetic device 有权
公开(公告)号：US09389855B2
公开(公告)日：2016-07-12
申请号：US14589740
申请日：2015-01-05
申请人： Kabushiki Kaisha Toshiba
发明人： Hideo Shimizu
IPC分类号： G06F21/00 , G06F9/30 , H04L9/28 , H04L9/06 , G06F12/02 , G06F21/60
CPC分类号： G06F9/3001 , G06F12/0215 , G06F21/602 , G06F2212/1008 , H04L9/0631 , H04L2209/122
摘要： According to an embodiment, an arithmetic device includes an arithmetic processing unit, an address generating unit, and a control unit. The arithmetic processing unit performs a plurality of arithmetic processing used in an encryption method. Based on an upper bit of the address of the first piece of data and based on an offset which is a value corresponding to a counter value and which is based on the address of the first piece of data, the address generating unit generates addresses of the memory device. The control unit controls the arithmetic processing unit in such a way that the arithmetic processing is done in a sequence determined in the encryption method, and that specifies an update of the counter value at a timing of modifying the type of data and at a timing of modifying data.

78. 发明申请

US20160191234A1 INFORMATION PROCESSING APPARATUS, PROGRAM, AND RECORDING MEDIUM 审中-公开
标题翻译：信息处理设备，程序和记录介质
公开(公告)号：US20160191234A1
公开(公告)日：2016-06-30
申请号：US15063719
申请日：2016-03-08
申请人： FUJI ELECTRIC CO., LTD.
发明人： Kenji TAKATSUKASA
IPC分类号： H04L9/06 , G09C1/00
CPC分类号： H04L9/0631 , G09C1/00 , H04L2209/122
摘要： An information processing apparatus is provided that performs information processing for encrypting data using AES, which includes performing a process of generating round key data on a one-byte-by-one-byte basis, performing a row shift transformation that is a process of performing row shifting for the data by use of a row shift table, performing a byte substitution transformation that is a process of performing byte substitution for the data having undergone the row shift transformation by use of a byte substitution table that is a one-dimensional array, performing a column mix transformation that is a process of performing column mixing for the data having undergone the byte substitution transformation based on equivalent expressions, performing a key add transformation that is a process of performing an exclusive-OR operation based on the round key data and the data having undergone the column mix transformation, wherein the row shift transformation, the byte substitution transformation, the column mix transformation, and the key add transformation are performed on a four-byte-by-four-byte basis.
摘要翻译：提供了一种信息处理装置，其执行用于使用AES对数据进行加密的信息处理，其包括以逐个字节为单位执行生成循环密钥数据的处理，执行作为执行的处理的行移位变换通过使用行移位表对数据进行行移位，执行字节替换变换，该字符替换变换是通过使用作为一维数组的字节替换表对经历行移位变换的数据进行字节替换的处理，执行列混合变换，该列混合变换是对已经经过基于等效表达式的字节替换变换的数据执行列混合的处理，执行基于循环密钥数据执行异或运算的处理的密钥附加变换，以及已经进行了列混合变换的数据，其中行移位变换，字节替换变换在四字节四字节的基础上执行列混合变换和密钥添加变换。

79. 发明授权

US09317286B2 Apparatus and method for implementing instruction support for the camellia cipher algorithm 有权
标题翻译：用于实现山茶密码算法的指令支持的装置和方法
公开(公告)号：US09317286B2
公开(公告)日：2016-04-19
申请号：US12414831
申请日：2009-03-31
申请人： Christopher H. Olson , Gregory F. Grohoski , Lawrence A. Spracklen
发明人： Christopher H. Olson , Gregory F. Grohoski , Lawrence A. Spracklen
IPC分类号： G06F9/30 , G06F9/38 , H04L9/06 , G06F15/00
CPC分类号： G06F9/30145 , G06F9/30003 , G06F9/30007 , G06F9/30018 , G06F9/30167 , G06F9/382 , G06F9/3851 , G06F9/3877 , H04L9/0625 , H04L2209/122 , H04L2209/125 , H04L2209/24
摘要： A processor including instruction support for implementing the Camellia block cipher algorithm may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include a cryptographic unit that may receive instructions for execution. The instructions include one or more Camellia instructions defined within the ISA. In addition, the Camellia instructions may be executable by the cryptographic unit to implement portions of a Camellia cipher that is compliant with Internet Engineering Task Force (IETF) Request For Comments (RFC) 3713. In response to receiving a Camellia F( )-operation instruction defined within the ISA, the cryptographic unit may perform an F( ) operation, as defined by the Camellia cipher, upon a data input operand and a subkey operand, in which the data input operand and subkey operand may be specified by the Camellia F( )-operation instruction.
摘要翻译：包括用于实现Camellia块密码算法的指令支持的处理器可以从定义的指令集体系结构（ISA）发出用于执行编程器可选择指令的执行。处理器可以包括可以接收执行指令的密码单元。说明书包括在ISA内定义的一个或多个Camellia指令。另外，山茶花指令可以由加密单元执行，以实现符合因特网工程任务组（IETF）请求注释（RFC）3713的Camellia密码的部分。响应于接收到Camellia F（）操作在ISA内定义的指令中，加密单元可以在数据输入操作数和子键操作数上执行由Camellia密码定义的F（）操作，其中数据输入操作数和子键操作数可以由Camellia F （）操作指令。

80. 发明申请

US20160072621A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20160072621A1
公开(公告)日：2016-03-10
申请号：US14844175
申请日：2015-09-03
申请人： Renesas Electronics Corporation
发明人： Daisuke OSHIDA
IPC分类号： H04L9/00 , G06F21/72
CPC分类号： H04L9/002 , G06F21/554 , G06F21/71 , G09C1/00 , H04L9/003 , H04L9/0631 , H04L2209/122 , H04L2209/125 , H04L2209/46
摘要： In data processing including high-speed cipher calculation for which it is not appropriate to employ a leveling technique, tamper resistance is improved against an attack to a specific position performed by knowing a layout of functional blocks in a semiconductor chip. Examples of the attack include micro-probing, fault injection, and electromagnetic wave analysis.A semiconductor device, in which a plurality of IC chips that perform the same cipher calculation in parallel are laminated or stacked, performs data processing including the cipher calculation. A chip that compares and verifies results of the cipher calculations performed by the plurality of chips is laminated in an intermediate layer whose element surface is covered by another chip. For example, when three chips are laminated, a chip in the intermediate layer sandwiched by the upper layer and the lower layer has a comparative verification function.
摘要翻译：在包括不适合使用调平技术的高速密码计算的数据处理中，通过了解半导体芯片中的功能块的布局，可以防止对特定位置的攻击的防篡改。攻击的例子包括微观探测，故障注入和电磁波分析。将并行进行相同的密码计算的多个IC芯片层叠或层叠的半导体装置，进行包括密码计算的数据处理。比较和验证由多个芯片执行的密码计算的结果的芯片被层压在其元件表面被另一个芯片覆盖的中间层中。例如，当层叠三个芯片时，由上层和下层夹持的中间层中的芯片具有比较验证功能。

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