专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明申请

US20050041727A1 PHY control module for a multi-pair gigabit transceiver 有权
标题翻译：用于多对千兆位收发器的PHY控制模块
公开(公告)号：US20050041727A1
公开(公告)日：2005-02-24
申请号：US10744527
申请日：2003-12-23
申请人： Oscar Agazi
发明人： Oscar Agazi
IPC分类号： G01R31/30 , G01R31/317 , G01R31/3185 , H03H7/30 , H03H21/00 , H04B1/38 , H04B3/23 , H04B3/32 , H04B3/46 , H04L1/00 , H04L1/08 , H04L1/24 , H04L7/00 , H04L7/02 , H04L7/033 , H04L25/03 , H04L25/06 , H04L25/14 , H04L25/49 , H04L25/497 , H04L29/08
CPC分类号： H04L7/0062 , G01R31/3004 , G01R31/3008 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318552 , G01R31/318594 , H03H21/0067 , H03H2021/007 , H03H2021/0074 , H04B3/23 , H04B3/32 , H04B3/487 , H04L1/0009 , H04L1/0054 , H04L1/08 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03267 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L69/323 , H04L2025/03363 , H04L2025/03369 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03681 , H04L2025/03745
摘要： A method for controlling operation of a multi-pair gigabit transceiver. The multi-pair gigabit transceiver comprises a Physical Layer Control module (PHY Control), a Physical Coding Sublayer module (PCS) and a Digital Signal Processing module (DSP). The PHY Control receives user-defined inputs from the Serial Management module and status signals and diagnostics signals from the DSP and the PCS and generates control signals, responsive to the user-defined inputs, the status signals and diagnostics signals, to the DSP and the PCS.
摘要翻译：一种用于控制多对千兆位收发器的操作的方法。多对千兆位收发器包括物理层控制模块（PHY Control），物理编码子层模块（PCS）和数字信号处理模块（DSP）。 PHY控制接收来自串行管理模块的用户定义的输入以及来自DSP和PCS的状态信号和诊断信号，并根据用户定义的输入，状态信号和诊断信号产生控制信号到DSP和 PCS。

72. 发明申请

US20040264615A1 Margin test methods and circuits 有权
标题翻译：保证金测试方法和电路
公开(公告)号：US20040264615A1
公开(公告)日：2004-12-30
申请号：US10815604
申请日：2004-03-31
发明人： Andrew Ho , Vladimir Stojanovic , Bruno W. Garlepp , Fred F. Chen
IPC分类号： H04K001/00
CPC分类号： H04B17/29 , G01R31/31711 , G06F11/08 , H04B17/21 , H04L1/20 , H04L1/241 , H04L1/242 , H04L7/033 , H04L7/043 , H04L7/10 , H04L25/03006 , H04L25/03057 , H04L25/03146 , H04L25/03949 , H04L27/01
摘要： Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.
摘要翻译：描述了数字接收机边缘测试的方法和电路。这些方法和电路可以防止误差响应于错误接收的数据而崩溃，并且因此可以用在采用历史数据的接收机中以减少符号间干扰（ISI）。一些实施例检测未知模式的输入数据流的接收错误，因此可以用于系统内边缘测试。这样的系统可以适于在设备操作期间动态地改变系统参数，以保持足够的余量，尽管由于例如系统噪声环境的波动。温度和电源电压变化。还描述了绘制和解释由所公开的方法和电路产生的滤波和未滤波的误差数据的方法。一些实施例可以过滤错误数据以促进模式特定的边缘测试。

73. 发明申请

US20040193982A1 Built-in self-test for digital transmitters 审中-公开
标题翻译：数字发射机内置自检
公开(公告)号：US20040193982A1
公开(公告)日：2004-09-30
申请号：US10404794
申请日：2003-03-31
申请人： ArrayComm, Inc.
发明人： Veerendra Bhora , Tibor Boros , Pulakesh Roy
IPC分类号： G01R031/28
CPC分类号： G01R31/31703 , H04L1/242
摘要： The present invention allows a complex digital processing engine to be tested automatically and autonomously using a minimum of memory and processing resources. In one embodiment, the invention includes an input buffer to store a digital test sequence, a digital data modulator coupled to the input buffer to generate a modulated digital sample sequence using the test sequence, a test buffer coupled to the modulator to receive and store a representation of the sample sequence, and a test buffer output to enable the test buffer contents to be compared to a reference sequence.
摘要翻译：本发明允许使用最少的存储器和处理资源来自动和自主地测试复杂的数字处理引擎。在一个实施例中，本发明包括用于存储数字测试序列的输入缓冲器，耦合到输入缓冲器的数字数据调制器，以使用测试序列生成调制数字采样序列，耦合到调制器的测试缓冲器，用于接收和存储样本序列的表示以及使测试缓冲区内容与参考序列进行比较的测试缓冲区输出。

74. 发明申请

US20040088624A1 Method for quantifying I/O chip/package resonance 有权
标题翻译：量化I / O芯片/封装谐振的方法
公开(公告)号：US20040088624A1
公开(公告)日：2004-05-06
申请号：US10277302
申请日：2002-10-22
发明人： Claude R. Gauthier , Aninda K. Roy , Brian W. Amick
IPC分类号： H04L001/22 , H04B001/74 , H02H003/05 , H05K010/00 , H03K019/003 , G06F011/00 , G01R031/28
CPC分类号： G01R31/31924 , G01R31/31932 , H04L1/242
摘要： A method for quantifying effects of resonance in an integrated circuit's power distribution network is provided. The power distribution network includes a first power supply line and a second power supply line to provide power to the integrated circuit. Test ranges are selected for two test parameters, reference voltage potential of a receiver and data transmission frequency of the integrated circuit. At each combination of the two test parameters, bit patterns are transmitted by the integrated circuit to the receiver. A comparison is made between the transmitted bits and the received bits to determine whether the transmitted bits were correctly received. The comparison may be used to determine and report a range of values for the reference voltage potential and data transmission frequency that allow the transmitted bits to be correctly received.
摘要翻译：提供了一种用于量化集成电路配电网络中谐振效应的方法。配电网络包括向集成电路提供电力的第一电源线和第二电源线。选择两个测试参数的测试范围，接收机的参考电压电位和集成电路的数据传输频率。在两个测试参数的每个组合中，位模式由集成电路传输到接收器。在发送的比特和接收的比特之间进行比较，以确定发送的比特是否被正确地接收。比较可以用于确定和报告允许正确接收发送位的参考电压电位和数据传输频率的值的范围。

75. 发明授权

US06731691B2 Multi-pair gigabit ethernet transceiver having adaptive disabling of circuit elements 有权
标题翻译：具有自适应禁用电路元件的多对千兆以太网收发器
公开(公告)号：US06731691B2
公开(公告)日：2004-05-04
申请号：US10205735
申请日：2002-07-26
申请人： Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , Henry Samueli , David E. Kruse , Arthur Abnous
发明人： Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , Henry Samueli , David E. Kruse , Arthur Abnous
IPC分类号： H09B1500
CPC分类号： H04L7/0062 , G01R31/3004 , G01R31/3008 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318552 , G01R31/318594 , H04B3/23 , H04B3/235 , H04B3/32 , H04L1/0021 , H04L1/0047 , H04L1/0053 , H04L1/0054 , H04L1/0059 , H04L1/006 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03197 , H04L25/03203 , H04L25/03235 , H04L25/03267 , H04L25/03987 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2001/0096 , H04L2025/03363 , H04L2025/03369 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03745
摘要： Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.
摘要翻译：公开了为多对千兆位以太网收发器提供高速解码，增强的功率降低和时钟域划分的各种系统和方法。 ISI补偿分为两个阶段; 第一级补偿由解调器中的发射机的部分响应脉冲整形滤波器的特性引起的ISI分量，第二级补偿由维特比解码器中的多对传输信道的特性引起的ISI分量。基于从单位深度判决反馈均衡器接收的尾值和系数值的子集，通过从多个判决反馈均衡器向维特比提供输入信号来减小DFE深度来实现高速解码。通过自适应地截断NEXT，FEXT和回声消除滤波器中的有源抽头，或通过禁用解码器电路部分，如通道响应特性允许，实现功率降低。生成接收时钟信号，使得其与模拟采样时钟信号在频率上同步，并且相对于采样时钟信号之一具有特定的相位偏移。调整该相位偏移，使得由于来自数字部分到模拟部分的开关噪声的耦合而导致的系统性能降低被大大减小。

76. 发明申请

US20040049359A1 System and method for detecting a device requiring power 有权
标题翻译：用于检测需要电源的设备的系统和方法
公开(公告)号：US20040049359A1
公开(公告)日：2004-03-11
申请号：US10446530
申请日：2003-05-27
发明人： Vafa Rakshani , Nariman Yousefi
IPC分类号： G06F019/00 , G01R021/00 , G01R021/06
CPC分类号： H04L12/2697 , G06F1/266 , H02J13/0048 , H04L1/242 , H04L12/10 , H04L25/02 , H04L43/0817 , H04L43/50 , Y02B90/226 , Y04S20/16 , Y04S40/168 , Y10T307/832
摘要： A system and technique for detecting a device that requires power is implemented with a power detection station. The power detection system includes a detector having an output and a return which are coupled together by the device when the device requires power. The detector includes a word generator for generating test pulses for transmission to the device via the detector output, and a comparator for comparing the detector output with the detector return. The power detection station has a wide variety of applications, including by way of example, a switch or hub.
摘要翻译：用电力检测站实现用于检测需要电力的装置的系统和技术。功率检测系统包括具有输出和返回的检测器，当设备需要电力时，该检测器由设备耦合在一起。该检测器包括用于产生经由检测器输出传输到设备的测试脉冲的字产生器，以及用于将检测器输出与检测器返回值进行比较的比较器。电力检测站具有各种各样的应用，例如通过开关或集线器。

77. 发明授权

US06693881B1 Method for bit error rate measurements in a cell-based telecommunication system 有权
标题翻译：基于小区的电信系统中的误码率测量方法
公开(公告)号：US06693881B1
公开(公告)日：2004-02-17
申请号：US09315014
申请日：1999-05-20
申请人： Marc Huysmans , Frank Cyriel Michel Defoort
发明人： Marc Huysmans , Frank Cyriel Michel Defoort
IPC分类号： H04J314
CPC分类号： H04L1/242 , H04L1/20
摘要： A method for bit error rate measurements in a cell-based telecommunication system is presented, comprising the following steps of generating a first bit pattern at a first location of said telecommunication system, transmitting said first bit pattern from said first location to a second location of said telecommunication system, thereby obtaining a transmitted bit pattern, generating a second bit pattern at said second location, said second bit pattern being identical with the first bit pattern and comparing said transmitted bit pattern with said second bit pattern. The first bit pattern is transmitted in at least one unused cell (U, I), said unused cell (U, I) being generated during normal operation of said telecommunication system in the case of a lack of used cells to be transmitted.
摘要翻译：在基于小区的电信系统中提出了一种用于误码率测量的方法，包括以下步骤：在所述电信系统的第一位置处产生第一位模式，将所述第一位模式从所述第一位置发送到第二位置，所述电信系统，从而获得发送位模式，在所述第二位置产生第二位模式，所述第二位模式与第一位模式相同，并将所发送的位模式与所述第二位模式进行比较。在至少一个未使用的小区（U，I）中发送第一比特模式，在缺少要发送的小区的情况下，在所述电信系统的正常操作期间生成所述未使用小区（U，I）。

78. 发明申请

US20040008050A1 Dynamic register with IDDQ testing capability 失效
标题翻译：具有IDDQ测试功能的动态寄存器
公开(公告)号：US20040008050A1
公开(公告)日：2004-01-15
申请号：US10436687
申请日：2003-05-13
发明人： Mehdi Hatamian
IPC分类号： G01R001/00 , G01R031/26
CPC分类号： H04L7/0062 , G01R31/3004 , G01R31/3008 , G01R31/3012 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318552 , G01R31/318594 , H04B3/23 , H04B3/32 , H04L1/0054 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03267 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2025/03363 , H04L2025/03369 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03745
摘要： The present invention is a method and a system for controlling a voltage at a node in a circuit such that the node is prevented from having an unknown floating voltage during a steady state of a clock signal. The circuit includes a transmission gate which has input and output terminals, and operates in response to a clock signal. The node is located proximal to the output terminal of the transmission gate. The method includes the operations of driving the node with an input signal when the transmission gate is open during a first steady state of the clock signal and pulling the node to a fixed voltage when the transmission gate is closed during a second steady state of the clock signal.
摘要翻译：本发明是一种用于控制电路节点处的电压的方法和系统，使得节点在时钟信号的稳定状态期间被防止具有未知的浮动电压。该电路包括具有输入和输出端的传输门，并响应时钟信号而工作。节点位于传输门的输出端附近。该方法包括在时钟信号的第一稳定状态期间传输门打开时驱动节点的操作，并且在时钟的第二稳定状态期间传输门关闭时将节点拉至固定电压信号。

79. 发明授权

US06629290B1 Method and apparatus for automatic transmit verification 有权
标题翻译：自动发送验证的方法和装置
公开(公告)号：US06629290B1
公开(公告)日：2003-09-30
申请号：US09531519
申请日：2000-03-21
申请人： Joon Kit Goh , Boon Piaw Tan , L. S. Chua
发明人： Joon Kit Goh , Boon Piaw Tan , L. S. Chua
IPC分类号： G06F702
CPC分类号： H04L1/242
摘要： A method and apparatus for automatically verifying whether a network interface is transmitting frame data properly. Frame data stored in host memory is transmitted to the network interface and to a transmit data checker. The network interface receives, processes and transmits the frame data. The processed frame data is transmitted to a network media and to the transmit data checker. The transmit data checker compares the frame data from the host memory with the processed frame data from the network interface and generates an indicator signal. The indicator signal indicates whether the network interface is transmitting processed frame data properly. The indicator signal is sent to a display which displays the result. The transmit data checker includes a timer for determining the processing time of the network interface. The timer measures the time between reception of the frame data from the host memory and the reception of the transmitted data.
摘要翻译：一种用于自动验证网络接口是否正确传输帧数据的方法和装置。存储在主机存储器中的帧数据被发送到网络接口和发送数据检查器。网络接口接收，处理和发送帧数据。经处理的帧数据被发送到网络媒体和发送数据检查器。发送数据检查器将来自主机存储器的帧数据与来自网络接口的经处理的帧数据进行比较，并生成指示符信号。指示信号表示网络接口是否正确发送处理后的帧数据。指示灯信号被发送到显示结果的显示器。发送数据检查器包括用于确定网络接口的处理时间的定时器。定时器测量从主机存储器接收帧数据和接收发送数据之间的时间。

80. 发明授权

US06628737B1 Signal synchronization using synchronization pattern extracted from signal 有权
标题翻译：使用从信号提取的同步模式的信号同步
公开(公告)号：US06628737B1
公开(公告)日：2003-09-30
申请号：US09327735
申请日：1999-06-08
申请人： Bogdan Timus
发明人： Bogdan Timus
IPC分类号： H04L700
CPC分类号： H04L1/20 , H04L1/242 , H04L7/0008 , H04L7/042 , H04L2027/0034
摘要： A signal quality measurement system includes a transmitter for transmitting a test signal to a receiver and a device for storing a copy of the test signal at the receiver. The similarity between the stored copy of the test signal and the signal received at the receiver is measured to determine reception quality. The receiver also includes a device for selecting a sequence of different synchronization patterns directly from the stored copy of the test signal, for determining, from said received signal, a sequence of signal segments that best matches the synchronization pattern sequence and for synchronizing the received signal with the signal segment sequence, thereby synchronizing the received signal with the stored copy of the test signal.
摘要翻译：信号质量测量系统包括用于将测试信号发送到接收机的发射机和用于在接收机处存储测试信号的副本的设备。测量存储的测试信号的副本与在接收器处接收的信号之间的相似度，以确定接收质量。接收机还包括用于从所存储的测试信号的副本中直接选择不同同步模式的序列的装置，用于从所述接收的信号中确定与该同步模式序列最佳匹配并使接收的信号同步的信号段的序列利用信号段序列，从而使接收的信号与存储的测试信号的副本同步。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式