专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明申请

US20040205438A1 Low complexity error concealment for wireless transmission 有权
标题翻译：无线传输的低复杂度错误隐藏
公开(公告)号：US20040205438A1
公开(公告)日：2004-10-14
申请号：US10435176
申请日：2003-05-10
申请人： G-PLUS, INC
发明人： Charles Chien , David Hsueh-Chia Chien
IPC分类号： H04L001/00 , G06F011/00 , G06F011/30 , H03M013/00 , G08C025/00
CPC分类号： H04L1/0071 , G11B20/10009 , H03M13/00 , H04L1/0019 , H04L1/0045 , H04L1/0072
摘要： An apparatus and method for concealing errors in digital data. An interpolator estimates a value of a sample of digital data from other samples of the digital data. The interpolator has an input for inputting the digital data and an output for outputting the estimated value of the sample of the digital data. A holding unit has an input for selectively receiving the sample of the digital data only when the sample is error free, and an output for outputting the error free sample. The input of the holding unit may be in parallel with the input of the interpolator. A selector selects between outputting the estimated value of the sample of the received digital data from an output of the interpolator and outputting the error free sample of the received digital data from an output of a holding unit based on at least one error indicator.
摘要翻译：一种用于隐藏数字数据中的错误的装置和方法。内插器估计来自数字数据的其他样本的数字数据样本的值。内插器具有用于输入数字数据的输入和用于输出数字数据的样本的估计值的输出。保持单元具有用于仅当样本无错误时有选择地接收数字数据的样本的输入和用于输出无错误样本的输出。保持单元的输入可以与内插器的输入并联。选择器选择从内插器的输出输出接收的数字数据的样本的估计值，并基于至少一个误差指示符从保持单元的输出输出接收到的数字数据的无错误采样。

72. 发明申请

US20040178936A1 Frequency error detection apparatus and method based on histogram information on input signals 有权
标题翻译：基于输入信号直方图信息的频率误差检测装置和方法
公开(公告)号：US20040178936A1
公开(公告)日：2004-09-16
申请号：US10799890
申请日：2004-03-15
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Jae-Wook Lee , Jung-Hyun Lee
IPC分类号： H03M001/10
CPC分类号： H03L7/091 , H03M13/00
摘要： Disclosed is frequency error detection apparatus and method based on histogram information of an input signal. The apparatus includes an analog-to-digital (A/D) converter for sampling and converting an analog signal inputted to an electronic device into digital values; a zero crossing point detector for detecting sign changes of the digital values, and detecting zero crossing points; a period information detector for detecting period information which is the number of the digital values corresponding to a periodic signal; a histogram information calculator for counting the number of detections for the respective period information based on the period information, and calculating error-detection-target histogram information; and a frequency error calculator for detecting a difference between the error-detection-target histogram information and a reference histogram information, and calculating a frequency error value based on the difference. The present invention can shorten time necessary for frequency error detections and improve accuracy of the detected frequency error value.
摘要翻译：公开了基于输入信号的直方图信息的频率误差检测装置和方法。该装置包括用于对输入到电子设备的模拟信号进行采样和转换为数字值的模数（A / D）转换器; 用于检测数字值的符号变化的零交叉点检测器，以及检测过零点; 周期信息检测器，用于检测作为周期信号对应的数字值的周期信息; 直方图信息计算器，用于根据周期信息对各周期信息的检测次数进行计数，并计算误差检测目标直方图信息; 以及频率误差计算器，用于检测误差检测目标直方图信息和参考直方图信息之间的差异，并且基于该差计算频率误差值。本发明可以缩短频率误差检测所需的时间并提高检测到的频率误差值的精度。

73. 发明授权

US06788222B2 Low weight data encoding for minimal power delivery impact 有权
标题翻译：低重量数据编码，最小的功率传递影响
公开(公告)号：US06788222B2
公开(公告)日：2004-09-07
申请号：US09759245
申请日：2001-01-16
申请人： Stephen H. Hall , Michael W. Leddige
发明人： Stephen H. Hall , Michael W. Leddige
IPC分类号： H03M700
CPC分类号： H03M13/00
摘要： A low weight encoding circuit of a power delivery system for encoding data sent out on an I/O bus with minimal current drawn so as to minimize signal and timing distortions. Such a low weight encoding circuit comprises a current balance tester arranged to test whether a predetermined number of data bits is current balanced; a current balance encoder and decode bit generator arranged to encode data bits and generate encoded data and corresponding decode bits if the predetermined number of data bits is not current balanced; and a latch arranged to latch either the data bits, via an I/O bus, if said predetermined number of data bits is current balanced or the encoded data and corresponding decode bits, via the I/O bus, if the predetermined number of data bits is not current balanced.
摘要翻译：一种功率传递系统的低权重编码电路，用于以最小的电流来对在I / O总线上发送的数据进行编码，以最小化信号和定时失真。这样一个低权重编码电路包括一个当前平衡测试器，其被布置成测试预定数量的数据位是否是电流平衡的; 电流平衡编码器和解码位发生器，其布置成如果预定数量的数据位不是电流平衡则编码数据位并产生编码数据和对应的解码位; 以及锁存器，其经由I / O总线经由I / O总线来锁存数据位，如果所述预定数量的数据位是电流平衡或经过I / O总线的编码数据和对应的解码位，则如果预定数量的数据位不是电流平衡。

74. 发明授权

US06771570B1 Method and format for reading and writing in a multilevel optical data system 有权
标题翻译：在多级光学数据系统中读写的方法和格式
公开(公告)号：US06771570B1
公开(公告)日：2004-08-03
申请号：US09476395
申请日：1999-12-30
申请人： Terrence L. Wong , Gregory S. Lewis , David C. Lee , Yi Ling , Stephen P. Pope , Steven R. Spielman , Jonathan A. Zingman
发明人： Terrence L. Wong , Gregory S. Lewis , David C. Lee , Yi Ling , Stephen P. Pope , Steven R. Spielman , Jonathan A. Zingman
IPC分类号： G11B1722
CPC分类号： G11B20/1252 , G11B7/0045 , G11B7/005 , G11B7/00745 , G11B7/013 , G11B20/10009 , G11B20/1403 , G11B20/1833 , G11B27/19 , G11B27/24 , G11B27/3027 , G11B2020/1222 , G11B2020/1268 , G11B2020/1275 , G11B2020/1287 , G11B2220/20 , G11B2220/2537 , H03M13/00 , H03M13/23
摘要： A system and method for reading and writing in a multilevel optical data system is disclosed. The system provides control signals for timing acquisition, level calibration, DC control, AGC, equalizer training and data synchronization. The user data is ECC protected and optionally convolutionally encoded before being combined with the control signals in an information block. The multilevel information block can be written to an optical disc as a series of multilevel marks. The optical disc may also contain an Address in Pregroove signal (AIP) to facilitate synchronization during writing of an information block. The AIP signal has an integer number of address frames per information block.
摘要翻译：公开了一种用于在多级光学数据系统中读取和写入的系统和方法。系统提供定时采集，电平校准，直流控制，AGC，均衡器训练和数据同步的控制信号。在与信息块中的控制信号组合之前，用户数据被ECC保护并可选地进行卷积编码。多级信息块可以作为一系列多级标记写入光盘。光盘还可以包含预编码信号（AIP）中的地址，以便于在写入信息块期间进行同步。 AIP信号具有每个信息块的整数个地址帧。

75. 发明申请

US20040146029A1 Rate matching and channel interleaving for a communications system 审中-公开
标题翻译：通信系统的速率匹配和信道交织
公开(公告)号：US20040146029A1
公开(公告)日：2004-07-29
申请号：US10753546
申请日：2004-01-08
发明人： Wen Tong , Catherine Leretaille , Stephane Gosne
IPC分类号： H04B007/216
CPC分类号： H03M13/2739 , H03M13/00 , H03M13/271 , H03M13/275 , H03M13/276 , H03M13/2764 , H03M13/2792 , H03M13/2957 , H03M13/635 , H04L1/0041 , H04L1/0052 , H04L1/0068 , H04L1/0071
摘要： A method of and apparatus for matching a rate of data bits, in a matrix of data bits interleaved by a predetermined interleaving process, to a desired rate by deletion of redundant data bits or repetition of data bits derived from the matrix, includes steps of determining in a non-interleaved matrix of the data bits a pattern of bits to be deleted or repeated to provide the desired data rate, decoding an address of each bit in said pattern in a manner inverse to the interleaving process to produce a respective address of the bit in the matrix of interleaved data bits, and deleting or repeating the respective bit in the interleaved data bits in dependence upon the respective address. The address decoding is performed in the same manner as a coding of addresses for producing the interleaved data bits from the non-interleaved matrix of the data bits. The specification also discloses an advantageous interleaving process for channel interleaving in a 3rd generation CDMA wireless communications system, a shuffling method for a second stage of interleaving in such a system, and how the rate matching can be conveniently applied to turbo-coded data.
摘要翻译：一种方法和装置，用于通过删除冗余数据位或从该矩阵导出的数据比特的重复，将由预定交织处理交织的数据比特矩阵中的数据比特速率匹配到期望速率，包括以下步骤：确定在数据比特的非交织矩阵中，要删除或重复的比特模式以提供期望的数据速率，以与交织处理相反的方式对所述模式中的每个比特的地址进行解码，以产生相应的地址并且根据相应的地址删除或重复交织的数据比特中的各个比特。以与用于从数据比特的非交织矩阵产生交错数据比特的地址的编码相同的方式执行地址解码。本说明书还公开了一种用于第三代CDMA无线通信系统中的信道交织的有利的交织过程，在这种系统中用于第二级交织的混洗方法，以及如何将速率匹配方便地应用于turbo编码数据。

76. 发明授权

US06766490B1 Reduced table size forward error correcting encoder 失效
标题翻译：减小表尺寸前向纠错编码器
公开(公告)号：US06766490B1
公开(公告)日：2004-07-20
申请号：US09518581
申请日：2000-03-03
申请人： Gary Garrabrant , Katherine Elliott
发明人： Gary Garrabrant , Katherine Elliott
IPC分类号： H03M1315
CPC分类号： H03M13/6312 , H03M7/30 , H03M13/00
摘要： A method and system for encoding and decoding a sequence of K binary digits using reduced-size lookup tables. The sequence of K binary digits is separated into multiple segments (e.g., a first segment and a second segment). The first segment is used as an index into a first lookup table that contains an encoded version of all combinations of binary digits possible in the first segment. In a similar manner, the second segment is used as an index into a second lookup table that contains an encoded version of all combinations of binary digits possible in the second segment. Using the first lookup table, an encoded sequence is obtained for the first segment, and an encoded sequence is obtained for the second segment using the second lookup table. An encoded sequence for the entire sequence of K binary digits is obtained by combining the encoded sequences for the first and second segments. Two lookup tables are thus used to encode the sequence of K binary digits instead of a single lookup table having 2K entries. The sizes of the two lookup tables are such that, if combined, they would contain fewer than 2K entries, thereby saving memory space in devices with limited memory capacity.
摘要翻译：一种使用缩小尺寸查找表对K个二进制数字序列进行编码和解码的方法和系统。 K个二进制数字的序列被分成多个段（例如，第一段和第二段）。第一段用作第一查找表中的索引，其包含第一段中可能的二进制数字的所有组合的编码版本。以类似的方式，第二段用作第二查找表的索引，其包含第二段中可能的二进制数字的所有组合的编码版本。使用第一查找表，获得针对第一段的编码序列，并且使用第二查找表为第二段获得编码序列。通过组合第一和第二段的编码序列来获得K个二进制数字的整个序列的编码序列。因此，使用两个查找表来编码K个二进制数字的序列，而不是具有2K个条目的单个查找表。两个查找表的大小使得如果组合，它们将包含少于2K个条目，从而在具有有限内存容量的设备中节省存储空间。

77. 发明申请

US20040117713A1 Generalized convolutional interleaver/de-interleaver 有权
标题翻译：广义卷积交织器/解交织器
公开(公告)号：US20040117713A1
公开(公告)日：2004-06-17
申请号：US10718894
申请日：2003-11-21
发明人： Kelley Brian Cameron
IPC分类号： H03M013/00
CPC分类号： H03M13/2782 , H03M13/00 , H03M13/2732 , H03M13/276 , H03M13/2789
摘要： A memory-efficient convolutional interleaver/de-interleaver with a memory array, a write commutator, and a read commutator wherein the commutators perform their respective write and read operations relative to a preselected memory cell after a predetermined delay. The delay is chosen using a modulo-based technique, such that an efficient implementation of a Ramsey Type-II interleaver is realized.
摘要翻译：具有存储器阵列的存储器高效卷积交织器/解交织器，写入换向器和读取换向器，其中，在预定延迟之后，换向器相对于预先选择的存储器单元执行它们各自的写入和读取操作。使用基于模的技术来选择延迟，使得实现了Ramsey II型交织器的有效实现。

78. 发明申请

US20040098651A1 System and method for generating self-checking data having information content in an error detection field 审中-公开
标题翻译：用于在错误检测领域中生成具有信息内容的自检数据的系统和方法
公开(公告)号：US20040098651A1
公开(公告)日：2004-05-20
申请号：US10298628
申请日：2002-11-18
发明人： Colm Marin Rice
IPC分类号： H03M013/00
CPC分类号： H04L1/0057 , G06F11/1044 , H03M13/00 , H03M13/03 , H04L1/0072
摘要： An error correction method which includes information-containing data in error correction fields thereby conserving memory space. Calculation of the error correction field can be performed using a formula that includes identifying data such as a company identification number. Memory space that would otherwise be used to provide space for a company identifier number in the source field, for example, can be saved by encoding the company identifier number into the error correction digits. The encoding step can be performed as part of the error correction formula processing so that additional encoding steps are not required
摘要翻译：一种误差校正方法，其包括纠错区域中的包含信息的数据，从而节省存储空间。可以使用包括识别诸如公司标识号的数据的公式来执行误差校正字段的计算。否则将用于为源字段中的公司标识符号提供空间的存储空间可以通过将公司标识符编码到纠错数字中来保存。编码步骤可以作为纠错公式处理的一部分来执行，使得不需要额外的编码步骤

79. 发明申请

US20040085231A1 Robust system for transmitting and receiving map data 有权
公开(公告)号：US20040085231A1
公开(公告)日：2004-05-06
申请号：US10663953
申请日：2003-09-16
发明人： Wayne E. Bretl , Mark Fimoff
IPC分类号： H03M007/00
CPC分类号： H04L1/0071 , H03M7/3082 , H03M13/00 , H04L1/0041 , H04L27/02 , H04N21/2383 , H04N21/4382 , Y02D70/10
摘要： Frames comprise odd fields and even fields. The frame sync segments of the odd fields contains a current map specifying the location of data in frames, a next map specifying the location of data in a future frame, and a frame count designating the future frame. The frame sync segments of the even field may contain the same information. Alternatively, the frame sync segments of the odd fields contain the current map and part of the frame count, and the frame sync segments of the corresponding even fields contain the next map and the rest of the frame count. A receiver uses the map and frame count information to find data in the fields of received frames.

80. 发明授权

US06711105B1 Method and apparatus for writing and reading optical recording medium 有权
公开(公告)号：US06711105B1
公开(公告)日：2004-03-23
申请号：US09373176
申请日：1999-08-12
申请人： Kenji Narumi , Kenichi Nishiuchi
发明人： Kenji Narumi , Kenichi Nishiuchi
IPC分类号： G11B700
CPC分类号： H03M13/2789 , G11B7/0045 , G11B7/00454 , G11B7/006 , G11B7/007 , G11B7/00718 , G11B7/00745 , G11B7/013 , G11B20/10212 , G11B20/10527 , G11B20/1217 , G11B20/1251 , G11B20/1403 , G11B20/18 , G11B20/1866 , G11B27/19 , G11B27/24 , G11B27/3027 , G11B27/329 , G11B2020/10898 , G11B2020/1232 , G11B2020/1267 , G11B2020/1277 , G11B2020/1287 , G11B2020/1288 , G11B2220/20 , G11B2220/216 , H03M13/00
摘要： An apparatus for writing on and reading an overwritable optical disk comprises an identifier detector that identifies a recording condition in the sector to be overwritten, and a delay time controller circuit that sets a variation range of the start point for writing according to the recording condition. The record timing of the modulated data signal is changed at random within the set variation range when overwriting the sector of the optical disk.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式