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71. 发明授权

US06853323B1 Differential voltage output digital-to-analog converter 有权
标题翻译：差分电压输出数模转换器
公开(公告)号：US06853323B1
公开(公告)日：2005-02-08
申请号：US10838754
申请日：2004-05-04
申请人： Yi-Huei Chen , Po-Chiun Huang , Chieh-Hung Chen
发明人： Yi-Huei Chen , Po-Chiun Huang , Chieh-Hung Chen
IPC分类号： H03M1/06 , H03M1/66 , H03M1/68 , H03M1/74
CPC分类号： H03M1/0678 , H03M1/685 , H03M1/747
摘要： A digital-to-analog converter (DAC) for use in high-speed wireless communications. The DAC of the invention comprises a plurality of current steering cells to bi-directionally provide a differential current output. When the DAC sets the differential current output to zero for example, each of the current steering cells establishes dummy branches between a pair of current sources and thereby prevents the current sources from floating. This in turn enables the DAC to operate with a higher update rate.
摘要翻译：用于高速无线通信的数模转换器（DAC）。本发明的DAC包括多个电流导向单元，以双向提供差分电流输出。当DAC将差分电流输出设置为零时，每个当前导向单元在一对电流源之间建立虚拟分支，从而防止电流源浮动。这反过来使DAC能够以更高的更新速率运行。

72. 发明申请

US20040223576A1 Fractional-type Phase-Locked Loop circuit with compensation of phase errors 有权
标题翻译：具有补偿相位误差的分数型锁相环电路
公开(公告)号：US20040223576A1
公开(公告)日：2004-11-11
申请号：US10801503
申请日：2004-03-15
申请人： STMicroelectronics S.r.l.
发明人： Guido Gabriele Albasini , Enrico Temporiti Milani
IPC分类号： H04L025/34
CPC分类号： H03L7/0891 , H03L7/1976 , H03M1/747
摘要： A fractional-type phase-locked loop circuit is proposed for synthesising an output signal multiplying a frequency of a reference signal by a fractional conversion factor, the circuit including means for generating a modulation value, means for generating a feedback signal dividing the frequency of the output signal by a dividing ratio, the dividing ratio being modulated according to the modulation value for providing the conversion factor on the average, means for generating a control signal indicative of a phase difference between the reference signal and the feedback signal, means for controlling the frequency of the output signal according to the control signal, and means for compensating a phase error caused by the modulation of the dividing ratio; in the circuit of an embodiment of the invention, the means for compensating includes means for calculating an incremental value, indicative of an incremental phase error, according to the conversion factor and the modulation value, means for calculating a correction value accumulating the incremental value, and means for conditioning the control signal according to the correction value.
摘要翻译：提出了一种分数型锁相环电路，用于合成将参考信号的频率乘以分数转换因子的输出信号，该电路包括用于产生调制值的装置，用于产生分频的频率的反馈信号的装置输出信号的分频比，分频比根据用于提供平均转换因子的调制值进行调制，用于产生指示参考信号和反馈信号之间的相位差的控制信号的装置，用于控制根据控制信号的输出信号的频率，以及用于补偿由分频比的调制引起的相位误差的装置; 在本发明的实施例的电路中，补偿装置包括根据转换因子和调制值计算表示增量相位误差的增量值的装置，用于计算积累增量值的校正值的装置，以及用于根据校正值调节控制信号的装置。

73. 发明申请

US20040201507A1 Digital-to-analog converter using an array of current sources 有权
标题翻译：使用电流源阵列的数模转换器
公开(公告)号：US20040201507A1
公开(公告)日：2004-10-14
申请号：US10835402
申请日：2004-04-30
申请人： Broadcom Corporation
发明人： Jean Boxho
IPC分类号： H03M001/80
CPC分类号： H03M1/066 , H03M1/1004 , H03M1/747
摘要： A current source DAC has calibration of the current sources used for providing the analog output. There are two outputs, one of which provides the output current or else a differential output is provided. The calibration is cyclic and the current source outputs switched to the output terminals are selected as a function of the point within the calibration cycle. The current stage of the cyclic calibration process is thus taken into account in the D/A conversion. For example, the average time since calibration for all current sources having outputs switched to the first output may be approximately equal to the average time since calibration for all current sources having outputs switched to the second output. In this way, the average current of the cells switched to one terminal is identical to the average current of the cells switched to the other terminal, and the average current of the cells switched to each terminal remains constant in time irrespective of the digital signal value being converted. This ensures DAC linearity.
摘要翻译：电流源DAC具有用于提供模拟输出的电流源的校准。有两个输出，其中一个提供输出电流，或者提供差分输出。校准是循环的，并且切换到输出端的电流源输出作为校准周期内的点的函数被选择。因此在D / A转换中考虑了循环校准过程的当前阶段。例如，具有切换到第一输出的输出的所有电流源的校准后的平均时间可以近似等于对于具有切换到第二输出的输出的所有电流源的校准后的平均时间。以这种方式，切换到一个终端的小区的平均电流与切换到另一个终端的小区的平均电流相同，并且切换到每个终端的小区的平均电流在时间上保持恒定，而与数字信号值无关被转换。这确保了DAC的线性度。

74. 发明申请

US20040036642A1 Digtal-to-analog converter and method for reducing harmonic distortion in a digital-to-analog converter 有权
标题翻译：数模转换器和减少数 - 模转换器谐波失真的方法
公开(公告)号：US20040036642A1
公开(公告)日：2004-02-26
申请号：US10276033
申请日：2003-01-08
发明人： Petri Eloranta
IPC分类号： H03M001/66
CPC分类号： H03K17/04106 , H03K17/162 , H03M1/687 , H03M1/745 , H03M1/747
摘要： The invention relates to a digital-to-analog converter. In order to reduce distortion in the output, the converter comprises a first and a second current output (OUT, XOUT), at least two current sources (1) and assigned to each of the current sources (1) a current switch circuit. Each current switch circuit comprises means (4, 5, 6, 7) for creating two overlapping complementary control signals out of a signal indicating whether the current source (1) is selected, while in a first group of the current switch circuits the connection of the current source (1) to the current outputs is controlled by one of the control signals respectively, and while in a second group of the current switch circuits the control by the control signals is exchanged, each of the current switch circuits of the second group comprising in addition means (10) for inverting the signal input to the means for creating two overlapping complementary control signal (4, 5, 6, 7).
摘要翻译：本发明涉及数模转换器。为了减少输出中的失真，转换器包括第一和第二电流输出（OUT，XOUT），至少两个电流源（1），并分配给每个电流源（1）电流开关电路。每个电流开关电路包括用于从指示电流源（1）是否被选择的信号中产生两个重叠互补控制信号的装置（4,5,6,7），而在第一组电流开关电路中，连接电流源（1）分别由控制信号之一控制，而在第二组电流开关电路中，由控制信号进行的控制被交换，第二组的每个电流开关电路包括用于将输入的信号反相到用于产生两个重叠的互补控制信号（4,5,6,7）的装置的装置（10）。

75. 发明申请

US20040017304A1 Thermometer code digital to audio converter 失效
标题翻译：温度计代码数字到音频转换器
公开(公告)号：US20040017304A1
公开(公告)日：2004-01-29
申请号：US10428620
申请日：2003-05-02
发明人： Friedrich Heizmann , Maximilian Erbar
IPC分类号： H03M001/66
CPC分类号： H03M1/0665 , H03M1/747 , H03M3/502 , H03M7/165
摘要： The invention relates to a method for converting a digital signal an analogue signal and to a digital to analogue converter comprising means for converting a digital signal to a thermometer coded signal, means for randomising the thermometer coded signal, means for controlling the means for randomising based on the digital signal and means for converting the randomised signal to analogue.
摘要翻译：本发明涉及一种将模拟信号的数字信号转换成数模转换器的方法，包括将数字信号转换为温度计编码信号的装置，用于随机化温度计编码信号的装置，用于控制用于随机化的装置的装置对数字信号和用于将随机信号转换为模拟的装置。

76. 发明授权

US06633248B2 Converting digital signals to analog signals 有权
标题翻译：将数字信号转换为模拟信号
公开(公告)号：US06633248B2
公开(公告)日：2003-10-14
申请号：US10226945
申请日：2002-08-23
申请人： Hongjiang Song
发明人： Hongjiang Song
IPC分类号： H03M166
CPC分类号： H03M1/687 , H03M1/0673 , H03M1/685 , H03M1/747 , H03M1/785
摘要： A way of converting digital signals to analog signals is provided for wireless communications. An apparatus is provided that comprises a resistive-ladder array to convert a first portion of a digital input signal to a first analog output signal. The apparatus further includes a current-mode array to convert a second portion of the digital input signal to a second analog output signal.
摘要翻译：提供了将数字信号转换为模拟信号的方式用于无线通信。提供了一种装置，其包括电阻梯形阵列，以将数字输入信号的第一部分转换为第一模拟输出信号。该装置还包括电流模式阵列，用于将数字输入信号的第二部分转换成第二模拟输出信号。

77. 发明授权

US06628219B2 Reducing jitter in mixed-signal integrated circuit devices 有权
公开(公告)号：US06628219B2
公开(公告)日：2003-09-30
申请号：US09987279
申请日：2001-11-14
申请人： Ian Juso Dedic
发明人： Ian Juso Dedic
IPC分类号： H03M100
CPC分类号： H03M1/0836 , H03M1/747
摘要： A mixed-signal integrated circuit device (100) such as a digital-to-analog converter comprises signal processing circuitry (120-170) operable to produce an output signal (OUT) in dependence upon a received input signal (D1-Dm). Production of the output signal (OUT) is initiated at a time determined by a timing signal (CLK) and is completed at a time which is delayed by a delay time with respect to said timing signal (CLK). The signal processing circuitry (120-170) comprises at least one delay-contributing portion (120, 130, 150, 160) which makes a contribution to the delay time that is affected by variations in a power supply voltage (VDD) applied to the delay-contributing portion concerned. The integrated circuit device (100) is provided with at least one internal supply voltage regulator (110) for connection when the device is in use to a power source external of the device (100) to receive therefrom an external power source voltage (VDD). The supply voltage regulator (110) derives a regulated internal power supply voltage (VDD(REG)) from the external power source voltage (VDD), and this regulated internal power supply voltage (VDD(REG)) is applied to one of the delay-contributing portions (130, 150, 160). At least one further circuitry portion (140, 170) within the integrated circuit device (100) is powered by a supply voltage (VDD) other than the regulated internal power supply voltage (VDD(REG)).

78. 发明授权

US06507296B1 Current source calibration circuit 有权
标题翻译：电流源校准电路
公开(公告)号：US06507296B1
公开(公告)日：2003-01-14
申请号：US09930032
申请日：2001-08-14
申请人： Yvette P. Lee , Marwan N. Hassoun
发明人： Yvette P. Lee , Marwan N. Hassoun
IPC分类号： H03M110
CPC分类号： H03M1/1004 , H03M1/747
摘要： A current source calibration circuit and methodology reduce noise generated by current switching. In one embodiment, the calibration circuit provides a random or pseudo-random clock signal to control a switching of calibration circuit. A clock signal generator has been described that provide a number of clock signals having different phases. In one embodiment, the clock signals are used to select a current source of a DAC for calibration. By using a random clock to select the current source, noise, which is generated by switching a primary current source with a backup current source, is spread out over a wider frequency range.
摘要翻译：电流源校准电路和方法减少了电流切换产生的噪声。在一个实施例中，校准电路提供随机或伪随机时钟信号以控制校准电路的切换。已经描述了提供具有不同相位的多个时钟信号的时钟信号发生器。在一个实施例中，时钟信号用于选择用于校准的DAC的电流源。通过使用随机时钟来选择电流源，通过用备用电流源切换初级电流源产生的噪声在较宽的频率范围内扩展。

79. 发明申请

US20020167430A1 DIGITAL-TO-ANALOGUE CONVERTER USING AN ARRAY OF CURRENT SOURCES 有权
标题翻译：使用电流源阵列的数字到模拟转换器
公开(公告)号：US20020167430A1
公开(公告)日：2002-11-14
申请号：US09908569
申请日：2001-07-20
申请人： Broadcom Corporation
发明人： Jean Boxho
IPC分类号： H03M001/06 , H03M001/66
CPC分类号： H03M1/066 , H03M1/1004 , H03M1/747
摘要： A current source DAC has calibration of the current sources used for providing the analog output. There are two outputs, one of which provides the output current or else a differential output is provided. The calibration is cyclic and the current source outputs switched to the output terminals are selected as a function of the point within the calibration cycle. The current stage of the cyclic calibration process is thus taken into account in the D/A conversion. For example, the average time since calibration for all current sources having outputs switched to the first output may be approximately equal to the average time since calibration for all current sources having outputs switched to the second output. In this way, the average current of the cells switched to one terminal is identical to the average current of the cells switched to the other terminal, and the average current of the cells switched to each terminal remains constant in time irrespective of the digital signal value being converted. This ensures DAC linearity.
摘要翻译：电流源DAC具有用于提供模拟输出的电流源的校准。有两个输出，其中一个提供输出电流，或者提供差分输出。校准是循环的，并且切换到输出端的电流源输出作为校准周期内的点的函数被选择。因此在D / A转换中考虑了循环校准过程的当前阶段。例如，具有切换到第一输出的输出的所有电流源的校准后的平均时间可以近似等于对于具有切换到第二输出的输出的所有电流源的校准后的平均时间。以这种方式，切换到一个终端的小区的平均电流与切换到另一个终端的小区的平均电流相同，并且切换到每个终端的小区的平均电流在时间上保持恒定，而与数字信号值无关被转换。这确保了DAC的线性度。

80. 发明授权

US06476753B1 Analog to digital converter using magnetoresistive memory technology 失效
标题翻译：模数转换器采用磁阻存储技术
公开(公告)号：US06476753B1
公开(公告)日：2002-11-05
申请号：US09675183
申请日：2000-09-29
申请人： John P. Hansen , Eric J. Salter
发明人： John P. Hansen , Eric J. Salter
IPC分类号： H03M112
CPC分类号： H03M1/685 , H03M1/142 , H03M1/361 , H03M1/747
摘要： An analog to digital converter using a memory array of multi-state magnetoresistive memory elements in which a received analog signal is proportionally distributed among the memory elements to program the memory array. The memory array may be organized into column and row memory lines and may include analog splitter circuitry that proportionally distributes the analog signal among the column and row memory lines. The analog splitter circuitry may divide the analog signal into increasingly discrete signal levels along the column and row memory lines. The analog splitter circuitry may include multiple current devices, each configured to carry a proportionally increasing current level between consecutive column and row memory lines. Alternatively, the analog splitter circuitry includes substantially equivalent current devices that are grouped and proportionally distributed among the column and row memory lines to proportionally distribute the received analog signal. Read logic digitally combines programmed logic states of the memory elements of the memory array to achieve an output digital value. The read logic counts memory elements having a predetermined memory state. The read logic may use a binary or sequential search for counting memory elements. Signal processing logic may be provided that determines any change in state or threshold condition of the memory array.
摘要翻译：一种使用多状态磁阻存储器元件的存储器阵列的模数转换器，其中接收的模拟信号按比例地分布在存储器元件中以对存储器阵列进行编程。存储器阵列可以被组织成列和行存储器线，并且可以包括在列和行存储器线之间成比例地分配模拟信号的模拟分离器电路。模拟分离器电路可以将模拟信号沿着列和行存储器线分成越来越离散的信号电平。模拟分配器电路可以包括多个当前设备，每个设备被配置为在连续的列和行存储器线之间承载成比例增加的电流电平。或者，模拟分配器电路包括在列和行存储器线之间被分组并按比例地分布的基本上等效的当前器件，以成比例地分配接收的模拟信号。读逻辑数字地组合存储器阵列的存储元件的编程逻辑状态，以实现输出数字值。读取逻辑对具有预定存储器状态的存储器元件进行计数。读逻辑可以使用二进制或顺序搜索来计数存储器元件。可以提供确定存储器阵列的状态或阈值状态的任何变化的信号处理逻辑。

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