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71. 发明授权

US08981448B2 Variable resistance memory device with shunt gate connected to corresponding gate 有权
标题翻译：具有分流栅的可变电阻存储器件连接到相应的栅极
公开(公告)号：US08981448B2
公开(公告)日：2015-03-17
申请号：US13795872
申请日：2013-03-12
申请人： SK Hynix Inc.
发明人： Nam Kyun Park
IPC分类号： H01L27/108 , H01L29/788 , H01L27/24 , H01L21/8239 , H01L29/78
CPC分类号： H01L27/2454 , H01L27/101 , H01L27/2463 , H01L29/4236 , H01L29/42376 , H01L29/4238 , H01L29/66666 , H01L29/7827 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/16
摘要： A variable resistance memory device includes a semiconductor substrate having a vertical transistor with a shunt gate that increases an area of a gate of the vertical transistor.
摘要翻译：可变电阻存储器件包括具有垂直晶体管的半导体衬底，该垂直晶体管具有增加垂直晶体管的栅极面积的分流栅极。

72. 发明申请

US20150041753A1 NANO-SCALE ELECTRICAL CONTACTS, MEMORY DEVICES INCLUDING NANO-SCALE ELECTRICAL CONTACTS, AND RELATED STRUCTURES AND DEVICES 有权
标题翻译：纳米级电气联系人，包括纳米级电气联系人的存储器件及相关结构和器件
公开(公告)号：US20150041753A1
公开(公告)日：2015-02-12
申请号：US14524322
申请日：2014-10-27
申请人： Micron Technology, Inc.
发明人： Jun Liu , Kunal R. Parekh
IPC分类号： H01L45/00
CPC分类号： H01L45/16 , H01L21/0337 , H01L21/76807 , H01L21/76816 , H01L27/2472 , H01L43/02 , H01L43/08 , H01L43/12 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/126 , H01L45/1273 , H01L45/14 , H01L45/146 , H01L45/147 , H01L2924/0002 , H01L2924/00
摘要： Electrical contacts may be formed by forming dielectric liners along sidewalk of a dielectric structure, forming sacrificial liners over and transverse to the dielectric liners along sidewalls of a sacrificial structure, selectively removing portions of the dielectric liners at intersections of the dielectric liners and sacrificial liners to form pores, and at least partially filling the pores with a conductive material. Nano-scale pores may be formed by similar methods. Bottom electrodes may be formed and electrical contacts may be structurally and electrically coupled to the bottom electrodes to form memory devices. Nano-scale electrical contacts may have a rectangular cross-section of as first width and a second width, each width less than about 20 nm. Memory devices may include bottom electrodes, electrical contacts having a cross-sectional area less than about 150 nm2 over and electrically coupled to the bottom electrodes, and a cell material over the electrical contacts.
摘要翻译：可以通过沿电介质结构的人行道形成电介质衬垫来形成电接触件，沿着牺牲结构的侧壁在电介质衬垫之上和横向于形成牺牲衬垫，在电介质衬垫和牺牲衬套的交叉处选择性地去除部分电介质衬垫到形成孔，并且用导电材料至少部分地填充孔。可以通过类似的方法形成纳米尺度的孔。可以形成底部电极，并且电触点可以在结构上和电耦合到底部电极以形成存储器件。纳米级电触头可以具有作为第一宽度和第二宽度的矩形横截面，每个宽度小于约20nm。存储器件可以包括底部电极，具有小于约150nm 2的横截面积并且电耦合到底部电极的电触点，以及电触点上的电池材料。

73. 发明申请

US20150004805A1 METHODS OF FORMING SILICON-CONTAINING DIELECTRIC MATERIALS AND SEMICONDUCTOR DEVICE STRUCTURES, AND RELATED SEMICONDUCTOR DEVICE STRUCTURES 有权
标题翻译：形成含硅介电材料和半导体器件结构的方法及相关半导体器件结构
公开(公告)号：US20150004805A1
公开(公告)日：2015-01-01
申请号：US13932667
申请日：2013-07-01
申请人： Micron Technology, Inc.
发明人： Thomas R. Omstead , Cole S. Franklin
IPC分类号： H01L21/02 , H01L21/283 , H01L29/45
CPC分类号： H01L45/124 , C23C16/345 , C23C16/36 , C23C16/45534 , C23C16/45542 , H01L21/02126 , H01L21/02164 , H01L21/02167 , H01L21/0217 , H01L21/02274 , H01L21/0228 , H01L21/02315 , H01L21/283 , H01L21/76829 , H01L27/2481 , H01L45/06 , H01L45/065 , H01L45/12 , H01L45/1233 , H01L45/126 , H01L45/141 , H01L45/16
摘要： A method of forming a silicon-containing dielectric material. The method includes forming a plasma comprising nitrogen radicals, absorbing the nitrogen radicals onto a substrate, and exposing the substrate to a silicon-containing precursor in a non-plasma environment to form monolayers of a silicon-containing dielectric material on the substrate. Additional methods are also described, as are semiconductor device structures including the silicon-containing dielectric material and methods of forming the semiconductor device structures.
摘要翻译：一种形成含硅电介质材料的方法。该方法包括形成包含氮自由基的等离子体，将氮自由基吸收到衬底上，以及将衬底暴露于非等离子体环境中的含硅前体，以在衬底上形成含硅介电材料的单层。还描述了另外的方法，半导体器件结构包括含硅介电材料和形成半导体器件结构的方法也是如此。

74. 发明授权

US08917545B2 Semiconductor intergrated circuit device, method of manufacturing the same, and method of driving the same 有权
标题翻译：半导体集成电路器件及其制造方法及其驱动方法
公开(公告)号：US08917545B2
公开(公告)日：2014-12-23
申请号：US14183193
申请日：2014-02-18
申请人： SK Hynix Inc.
发明人： Myoung Sub Kim , Soo Gil Kim , Nam Kyun Park , Sung Cheoul Kim , Gap Sok Do , Joon Seop Sim , Hyun Jeong Lee
IPC分类号： G11C11/00 , H01L45/00 , G11C13/00 , H01L27/24
CPC分类号： H01L45/1675 , G11C13/0004 , G11C2013/008 , G11C2213/71 , H01L27/2409 , H01L27/249 , H01L45/06 , H01L45/1226 , H01L45/1246 , H01L45/126 , H01L45/144
摘要： A semiconductor integrated circuit device, a method of manufacturing the same, and a method of driving the same are provided. The device includes a semiconductor substrate, an upper electrode extending from a surface of the semiconductor substrate; a plurality of switching structures extending from both sidewalls of the upper electrode in a direction parallel to the surface of the semiconductor substrate, and a phase-change material layer disposed between the plurality of switching structures and the upper electrode.
摘要翻译：提供了一种半导体集成电路器件及其制造方法及其驱动方法。该器件包括半导体衬底，从半导体衬底的表面延伸的上电极; 多个开关结构，其从与上述半导体基板的表面平行的方向从上述电极的两侧延伸;以及相变材料层，设置在上述多个开关结构体和上部电极之间。

75. 发明授权

US08916413B2 Phase change memory and manufacturing method therefor 有权
标题翻译：相变记忆及其制造方法
公开(公告)号：US08916413B2
公开(公告)日：2014-12-23
申请号：US13656370
申请日：2012-10-19
申请人： Semiconductor Manufacturing International Corporation , Semiconductor Manufacturing International Corporation
发明人： Minda Hu , James Hong
IPC分类号： H01L21/00 , H01L21/20
CPC分类号： H01L45/1683 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要： The present invention discloses a phase change memory and a manufacturing method thereof. The phase change memory according to the present invention uses top electrodes provided on the top of storage nodes to heat the storage nodes such that a phase change layer in the storage nodes undergoes a phase change. In the phase change memory of embodiments of the present invention, the contact area between the top electrode and the storage node is relatively small, which is good for phase change. Moreover, each column of storage nodes is connected by the same linear top electrode, which can improve photo alignment shift margin.
摘要翻译：本发明公开了一种相变存储器及其制造方法。根据本发明的相变存储器使用设置在存储节点顶部的顶部电极来加热存储节点，使得存储节点中的相变层经历相变。在本发明实施例的相变存储器中，顶电极和存储节点之间的接触面积相对较小，这对于相变是有利的。此外，每列存储节点由相同的线性顶部电极连接，这可以提高照片对准偏移余量。

76. 发明授权

US08912515B2 Manufacturing method for pipe-shaped electrode phase change memory 有权
标题翻译：管状电极相变记忆体的制造方法
公开(公告)号：US08912515B2
公开(公告)日：2014-12-16
申请号：US13045376
申请日：2011-03-10
申请人： Hsiang-Lan Lung
发明人： Hsiang-Lan Lung
IPC分类号： H01L45/00
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1625 , H01L45/1675
摘要： A method for manufacturing a memory cell device includes forming a bottom electrode comprising a pipe-shaped member, a top, a bottom and sidewalls having thickness in a dimension orthogonal to the axis of the pipe-shaped member, and having a ring-shaped top surface. A disc shaped member is formed on the bottom of the pipe-shaped member having a thickness in a dimension coaxial with the pipe-shaped member that is not dependent on the thickness of the sidewalls of the pipe-shaped member. A layer of phase change material is deposited in contact with the top surface of the pipe-shaped member. A top electrode in contact with the layer of programmable resistive material. An integrated circuit including an array of such memory cells is described.
摘要翻译：一种用于制造存储单元器件的方法，包括：形成底部电极，该底部电极包括具有与管状构件的轴线正交的尺寸的管状构件，顶部，底部和侧壁，并且具有环形顶部表面。在管状部件的底部上形成有与管状部件同轴的厚度的盘状部件，该管状部件的厚度与管状部件的侧壁厚度无关。一层相变材料沉积成与管状构件的顶表面接触。与可编程电阻材料层接触的顶部电极。描述了包括这种存储器单元的阵列的集成电路。

77. 发明申请

US20140361233A1 3 DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译： 3尺寸半导体器件及其制造方法
公开(公告)号：US20140361233A1
公开(公告)日：2014-12-11
申请号：US14057813
申请日：2013-10-18
申请人： SK Hynix Inc.
发明人： Suk Ki KIM
IPC分类号： H01L45/00 , H01L29/66 , H01L27/24
CPC分类号： H01L27/2463 , H01L21/467 , H01L27/2436 , H01L27/2481 , H01L29/0847 , H01L29/161 , H01L29/165 , H01L29/41783 , H01L29/4236 , H01L29/66621 , H01L29/66666 , H01L29/66969 , H01L29/7838 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1683 , Y10S438/90
摘要： A 3D semiconductor device and a method of manufacturing the same are provided. The method includes forming a first semiconductor layer including a common source node on a semiconductor substrate, forming a transistor region on the first semiconductor layer, wherein the transistor region includes a horizontal channel region substantially parallel to a surface of the semiconductor substrate, and source and drain regions branched from the horizontal channel region to a direction substantially perpendicular to the surface of the semiconductor substrate, processing the first semiconductor layer to locate the common source node corresponding to the source region, forming a gate in a space between the source region and the drain region, forming heating electrodes on the source region and the drain region, and forming resistance variable material layers on the exposed heating electrodes.
摘要翻译：提供了一种3D半导体器件及其制造方法。该方法包括在半导体衬底上形成包括公共源节点的第一半导体层，在第一半导体层上形成晶体管区域，其中晶体管区域包括基本上平行于半导体衬底的表面的水平沟道区域，漏极区域从水平沟道区域分支到基本上垂直于半导体衬底的表面的方向，处理第一半导体层以定位对应于源极区域的公共源极节点，在源极区域和源极区域之间的空间中形成栅极漏极区域，在源极区域和漏极区域上形成加热电极，以及在暴露的加热电极上形成电阻可变材料层。

78. 发明授权

US08890110B2 Vertical memory device and method of fabricating the same 有权
标题翻译：垂直记忆装置及其制造方法
公开(公告)号：US08890110B2
公开(公告)日：2014-11-18
申请号：US13845959
申请日：2013-03-18
申请人： SK Hynix Inc.
发明人： Nam Kyun Park
IPC分类号： H01L47/00 , H01L21/336 , H01L27/24 , H01L45/00
CPC分类号： H01L27/2454 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1608 , H01L45/1683
摘要： A vertical memory device capable of minimizing a cell size and improving current drivability and a method of fabricating the same are provided. The vertical memory device includes a common source region and source regions formed on the common source region and extending in a first direction. Channel regions are formed on each of the source regions, the channel regions extending in the first direction. Trenches are formed between the channel regions. A drain region is formed on each of the channel regions. A conductive layer is formed on a side of each of the channel regions, the conductive layer extending to the first direction. A data storage material is formed on each of the drain regions.
摘要翻译：提供了能够最小化电池尺寸并提高电流驱动能力的垂直存储器件及其制造方法。垂直存储器件包括公共源极区域和形成在共同源极区域上并沿第一方向延伸的源极区域。沟道区形成在每个源区上，沟道区沿第一方向延伸。沟渠区域之间形成沟槽。漏极区域形成在每个沟道区域上。导电层形成在每个沟道区的一侧，导电层延伸到第一方向。在每个漏极区域上形成数据存储材料。

79. 发明授权

US08872148B2 Phase-change memory devices 有权
标题翻译：相变存储器件
公开(公告)号：US08872148B2
公开(公告)日：2014-10-28
申请号：US13735180
申请日：2013-01-07
申请人： Doo-Hwan Park , Gyu-Hwan Oh , Jeong-Min Park , Kyung-Min Chung
发明人： Doo-Hwan Park , Gyu-Hwan Oh , Jeong-Min Park , Kyung-Min Chung
IPC分类号： H01L27/10 , H01L45/00 , H01L27/24
CPC分类号： H01L45/06 , H01L27/2409 , H01L27/2463 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1683
摘要： A phase-change memory device includes a diode, a plug, a doping layer pattern, a phase-change layer pattern and an upper electrode. The diode is disposed on a substrate. The plug is disposed on the diode and has a bottom surface whose area is equal to the area of a top surface of the diode. The plug is formed of metal or a conductive metallic compound. The doping layer pattern is disposed on the plug and has a bottom surface whose area is equal to the area of a top surface of the plug, and includes the same metal or conductive metallic compound as the plug. The phase-change layer pattern is disposed on the doping layer pattern. The upper electrode is disposed on the phase-change layer pattern.
摘要翻译：相变存储器件包括二极管，插头，掺杂层图案，相变层图案和上电极。二极管设置在基板上。插头设置在二极管上，并具有面积等于二极管顶表面面积的底面。插头由金属或导电金属化合物形成。掺杂层图案设置在插塞上，并且具有面积等于插头顶面的面积的底面，并且包括与插头相同的金属或导电金属化合物。相变层图案设置在掺杂层图案上。上电极配置在相变层图案上。

80. 发明授权

US08872146B2 Phase-change random access memory device and method of manufacturing the same 有权
标题翻译：相变随机存取存储器件及其制造方法
公开(公告)号：US08872146B2
公开(公告)日：2014-10-28
申请号：US12821414
申请日：2010-06-23
申请人： Seung-Yun Lee , Young Sam Park , Sung Min Yoon , Kyu-Jeong Choi , Nam-Yeal Lee , Byoung-Gon Yu
发明人： Seung-Yun Lee , Young Sam Park , Sung Min Yoon , Kyu-Jeong Choi , Nam-Yeal Lee , Byoung-Gon Yu
IPC分类号： H01L45/00
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： Provided are a Phase-change Random Access Memory (PRAM) device and a method of manufacturing the same. In particular, a PRAM device including a heating layer, wherein the heating layer comprises first and second heating layers having different physical properties from each other and a method of manufacturing the same are provided. Since the PRAM device according to the present invention includes a heating layer having optimal heating characteristics, a PRAM device having high reliability and excellent operating characteristics can be manufactured.
摘要翻译：提供了一种相变随机存取存储器（PRAM）装置及其制造方法。特别地，包括加热层的PRAM装置及其制造方法，其中加热层包括彼此具有不同物理性质的第一和第二加热层。由于根据本发明的PRAM器件包括具有最佳加热特性的加热层，所以可以制造具有高可靠性和优异的工作特性的PRAM器件。

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