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71. 发明申请

US20160268127A1 Oxide and Manufacturing Method Thereof 审中-公开
标题翻译：氧化物及其制造方法
公开(公告)号：US20160268127A1
公开(公告)日：2016-09-15
申请号：US15066577
申请日：2016-03-10
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Shunpei Yamazaki
IPC分类号： H01L21/02 , H01L29/04 , C23C14/08 , H01L29/66 , C23C14/35 , H01L29/24 , H01L29/786
CPC分类号： H01L21/02565 , C23C14/086 , C23C14/3485 , C23C14/35 , C23C14/352 , H01L21/02422 , H01L21/02554 , H01L21/02631 , H01L21/67207 , H01L21/8258 , H01L27/0688 , H01L27/088 , H01L27/092 , H01L27/10805 , H01L27/1156 , H01L27/1207 , H01L27/1225 , H01L29/045 , H01L29/24 , H01L29/66969 , H01L29/78603 , H01L29/7869 , H01L29/78693
摘要： An oxide with high crystallinity or an oxide having a crystal structure with few defects is provided. A method for manufacturing an oxide with a sputtering apparatus includes a target, a backing plate, a magnet unit, a power source, and a substrate holder. The target is fixed to the backing plate. The magnet unit is disposed on a back surface side of the target with the backing plate positioned therebetween. The power source is electrically connected to the backing plate. The substrate holder faces the target. In the manufacturing method, plasma including a cation is generated with the power source in a space between the target and a substrate, level of plasma density in a region in contact with the substrate is modulated, sputtered particles are generated when the cation collides with the target, and the sputtered particles are deposited on the substrate.
摘要翻译：提供具有高结晶度的氧化物或具有少量缺陷的晶体结构的氧化物。利用溅射装置制造氧化物的方法包括靶，背板，磁体单元，电源和衬底保持器。目标固定在背板上。磁体单元设置在目标的背面侧，背板位于其间。电源电连接到背板。基板支架面向目标。在制造方法中，使用电源在靶与基板之间的空间中产生包含阳离子的等离子体，与基板接触的区域中的等离子体密度的水平被调制，当阳离子与靶，并且溅射的颗粒沉积在基底上。

72. 发明申请

US20160233217A1 ETCHSTOP LAYERS AND CAPACITORS 审中-公开
公开(公告)号：US20160233217A1
公开(公告)日：2016-08-11
申请号：US15132037
申请日：2016-04-18
申请人： Intel Corporation
发明人： Ruth A. Brain
IPC分类号： H01L27/108 , H01L21/768 , H01L23/532 , H01L49/02 , H01L23/528
CPC分类号： H01L28/60 , G06F1/184 , H01L21/02148 , H01L21/0217 , H01L21/02175 , H01L21/02178 , H01L21/02181 , H01L21/02186 , H01L21/02189 , H01L21/02192 , H01L21/31144 , H01L21/76829 , H01L21/76832 , H01L21/76877 , H01L23/5223 , H01L23/5226 , H01L23/5283 , H01L23/53228 , H01L23/5329 , H01L27/10805 , H01L27/10814 , H01L27/1085 , H01L27/10852 , H01L27/10885 , H01L28/40 , H01L28/90 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： Capacitor structures for integrated circuit devices are provided. Capacitors include proximate dense or highly dense etchstop layers. The dense or highly dense etchstop layer is, for example, a high-k material. Capacitors are, for example, metal-insulator-metal (MIM) capacitors and are useful in DRAM (dynamic random access memory) and eDRAM (embedded dynamic random access memory) structures.

73. 发明授权

US09412867B2 Semiconductor device including gate electrode for applying tensile stress to silicon substrate, and method of manufacturing the same 有权
公开(公告)号：US09412867B2
公开(公告)日：2016-08-09
申请号：US14933079
申请日：2015-11-05
申请人： Renesas Electronics Corporation
发明人： Hirokazu Sayama , Kazunobu Ohta , Hidekazu Oda , Kouhei Sugihara
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392 , H01L29/78 , H01L21/265 , H01L21/3215 , H01L21/8238 , H01L21/8234 , H01L27/108 , H01L27/11 , H01L29/49 , H01L29/66
CPC分类号： H01L29/7845 , H01L21/26506 , H01L21/32155 , H01L21/823412 , H01L21/823418 , H01L21/823443 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L21/823835 , H01L21/823842 , H01L27/10805 , H01L27/10844 , H01L27/10894 , H01L27/10897 , H01L27/1104 , H01L27/1116 , H01L29/4925 , H01L29/4933 , H01L29/66477 , H01L29/665 , H01L29/7842 , H01L29/7848
摘要： A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

74. 发明授权

US09406370B2 Memory device, and semiconductor device and electronic appliance including the same 有权
标题翻译：存储器件，以及包括其的半导体器件和电子设备
公开(公告)号：US09406370B2
公开(公告)日：2016-08-02
申请号：US14723618
申请日：2015-05-28
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Takahiko Ishizu
IPC分类号： G11C11/24 , G11C11/406 , G11C11/405 , H01L29/78 , G11C11/404 , G11C11/4074 , H01L27/12 , H01L27/108 , G11C11/4091
CPC分类号： G11C11/40615 , G11C11/404 , G11C11/405 , G11C11/406 , G11C11/4074 , G11C11/4091 , G11C2211/4068 , H01L27/108 , H01L27/10802 , H01L27/10805 , H01L27/1203 , H01L29/7841
摘要： A memory device capable of optimizing a refresh cycle is provided. The memory device includes a monitor circuit capable of generating a signal serving as a trigger for a refresh operation. The monitor circuit includes a transistor and a capacitor. The monitor circuit has a function of sensing that a potential retained in the capacitor is lower than a reference potential, a function of generating a first signal and a second signal on the basis of the sensing result, and a function of turning on the transistor in response to the second signal and resetting the potential retained in the capacitor to an initialization state. It is possible to start refresh of a memory cell in response to the first signal.
摘要翻译：提供了能够优化刷新周期的存储器件。该存储装置包括能够产生用作刷新操作的触发信号的监视电路。监视电路包括晶体管和电容器。监视电路具有检测电容器中保持的电位低于参考电位的功能，基于感测结果产生第一信号和第二信号的功能以及将晶体管导通的功能响应于第二信号并将保持在电容器中的电位重置为初始化状态。可以响应于第一信号开始刷新存储器单元。

75. 发明申请

US20160118418A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20160118418A1
公开(公告)日：2016-04-28
申请号：US14989927
申请日：2016-01-07
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Shunpei YAMAZAKI , Masashi TSUBUKU , Kosei NODA , Kouhei TOYOTAKA , Kazunori WATANABE , Hikaru HARADA
IPC分类号： H01L27/12 , H01L29/417 , H01L29/423 , H01L29/786
CPC分类号： H01L29/7869 , G06F15/76 , H01L27/10805 , H01L27/10873 , H01L27/11 , H01L27/1108 , H01L27/1112 , H01L27/1225 , H01L27/124 , H01L27/1255 , H01L28/60 , H01L29/24 , H01L29/41733 , H01L29/42384 , H01L29/78696
摘要： An object is to provide a memory device including a memory element that can be operated without problems by a thin film transistor with a low off-state current. Provided is a memory device in which a memory element including at least one thin film transistor that includes an oxide semiconductor layer is arranged as a matrix. The thin film transistor including an oxide semiconductor layer has a high field effect mobility and low off-state current, and thus can be operated favorably without problems. In addition, the power consumption can be reduced. Such a memory device is particularly effective in the case where the thin film transistor including an oxide semiconductor layer is provided in a pixel of a display device because the memory device and the pixel can be formed over one substrate.
摘要翻译：目的是提供一种存储器件，其包括可通过具有低截止电流的薄膜晶体管无故障地操作的存储元件。提供了一种存储器件，其中包括至少一个包括氧化物半导体层的薄膜晶体管的存储元件被布置为矩阵。包括氧化物半导体层的薄膜晶体管具有高场效应迁移率和低截止电流，因此可以有利地操作而没有问题。此外，可以降低功耗。由于存储器件和像素可以形成在一个衬底上，所以这种存储器件在包括氧化物半导体层的薄膜晶体管被设置在显示器件的像素中的情况下是特别有效的。

76. 发明授权

US09318546B1 Doped electrode for DRAM capacitor stack 有权
标题翻译：用于DRAM电容器堆叠的掺杂电极
公开(公告)号：US09318546B1
公开(公告)日：2016-04-19
申请号：US14507418
申请日：2014-10-06
申请人： Intermolecular, Inc.
发明人： Prashant B. Phatak
IPC分类号： H01L21/20 , H01L21/28 , H01L49/02 , H01L27/108 , H01L21/02 , H01L21/285
CPC分类号： H01L28/75 , H01L21/02197 , H01L21/2855 , H01L27/108 , H01L27/10805 , H01L28/65
摘要： In some embodiments, a metal oxide second electrode material is formed as part of a MIM DRAM capacitor stack. The second electrode material is doped with one or more dopants. The dopants may influence the crystallinity, resistivity, and/or work function of the second electrode material. The dopants may be uniformly distributed throughout the second electrode material or may be distributed with a gradient in their concentration profile.
摘要翻译：在一些实施例中，金属氧化物第二电极材料形成为MIM DRAM电容器堆叠的一部分。第二电极材料掺杂有一种或多种掺杂剂。掺杂剂可影响第二电极材料的结晶度，电阻率和/或功函数。掺杂剂可以均匀分布在整个第二电极材料中，或者可以以它们的浓度分布梯度分布。

77. 发明申请

US20160099304A1 MoNx as a Top Electrode for TiOx Based DRAM Applications 审中-公开
标题翻译： MoNx作为基于TiOx的DRAM应用的顶级电极
公开(公告)号：US20160099304A1
公开(公告)日：2016-04-07
申请号：US14507462
申请日：2014-10-06
申请人： Intermolecular, Inc.
发明人： Monica Mathur
IPC分类号： H01L49/02
CPC分类号： H01L28/75 , H01L27/10805 , H01L28/65
摘要： A capacitor stack includes a base bottom electrode layer including a conductive metal nitride material. A second bottom electrode layer is formed above the first bottom electrode layer. The second bottom electrode layer includes a conductive metal oxide material, wherein the crystal structure of the conductive metal oxide material promotes a desired high-k crystal phase of a subsequently deposited dielectric layer. A dielectric layer is formed above the second bottom electrode layer. A molybdenum nitride or a molybdenum oxy-nitride layer is formed above the dielectric layer. A fourth top electrode layer is formed above the third top electrode layer. The base top electrode layer includes a conductive metal nitride material.
摘要翻译：电容器堆叠包括包括导电金属氮化物材料的基底电极层。在第一底部电极层的上方形成第二底部电极层。第二底部电极层包括导电金属氧化物材料，其中导电金属氧化物材料的晶体结构促进随后沉积的介电层的期望的高k结晶相。在第二底部电极层的上方形成电介质层。在电介质层上方形成氮化钼或氮氧化钼层。第四上电极层形成在第三顶电极层的上方。基极电极层包括导电金属氮化物材料。

78. 发明申请

US20160071565A1 Memory Circuits and a Method for Forming a Memory Circuit 审中-公开
标题翻译：存储器电路和形成存储器电路的方法
公开(公告)号：US20160071565A1
公开(公告)日：2016-03-10
申请号：US14843484
申请日：2015-09-02
申请人： Infineon Technologies AG
发明人： Marko Lemke
IPC分类号： G11C8/00 , G11C5/14 , H01L27/108
CPC分类号： G11C8/00 , G11C5/141 , G11C5/147 , H01G11/06 , H01G11/50 , H01L27/10805 , H01L27/1085 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/145 , H01L45/1675 , H01M10/425 , Y02E60/13
摘要： A memory circuit includes a memory element which includes a first electrode layer including lithium. The memory element further includes a second electrode layer and a solid-state electrolyte layer arranged between the first electrode layer and the second electrode layer. The memory circuit also includes a memory access circuit configured to determine a memory state of the memory element.
摘要翻译：存储电路包括存储元件，该存储元件包括包括锂的第一电极层。存储元件还包括布置在第一电极层和第二电极层之间的第二电极层和固态电解质层。存储器电路还包括被配置为确定存储器元件的存储器状态的存储器访问电路。

79. 发明申请

US20160064480A1 Semiconductor Constructions, Memory Arrays and Electronic Systems 审中-公开
标题翻译：半导体构造，存储阵列和电子系统
公开(公告)号：US20160064480A1
公开(公告)日：2016-03-03
申请号：US14935049
申请日：2015-11-06
申请人： Micron Technology, Inc.
发明人： Gurtej S. Sandhu , D. Mark Durcan
IPC分类号： H01L29/06 , H01L27/108 , G11C14/00 , H01L27/115
CPC分类号： H01L29/0649 , G11C14/0018 , H01L21/76232 , H01L27/10805 , H01L27/11521 , H01L29/0653
摘要： The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The bottom portions can have substantially vertical sidewalls, and can join to the upper portions at steps which extend substantially perpendicularly from the sidewalls. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.
摘要翻译：本发明包括具有沟槽隔离区域的半导体结构。沟槽隔离区域的沟槽可以包括底部的窄底部部分和上部宽部分。电绝缘材料可以填充上部宽部分，同时留下狭窄底部内的空隙。底部可以具有基本上垂直的侧壁，并且可以从侧壁大致垂直延伸的台阶连接到上部。沟槽隔离区域可以并入存储器阵列中，和/或可并入到电子系统中。本发明还包括形成半导体结构的方法。

80. 发明申请

US20160064391A1 DYNAMIC RANDOM ACCESS MEMORY CELL INCLUDING A FERROELECTRIC CAPACITOR 审中-公开
标题翻译：动态随机访问存储单元，包括一个电磁电容器
公开(公告)号：US20160064391A1
公开(公告)日：2016-03-03
申请号：US14469341
申请日：2014-08-26
申请人： QUALCOMM Incorporated
发明人： Xia Li , Woo Tag Kang , Changhan Hobie Yun , Wei-Chuan Chen
IPC分类号： H01L27/115 , G11C11/409 , G11C11/22 , H01L27/108
CPC分类号： H01L27/11507 , G11C11/221 , G11C11/2273 , G11C11/2275 , G11C11/401 , G11C11/409 , H01G7/06 , H01L27/10805 , H01L27/10808 , H01L27/10897 , H01L27/11512 , H01L27/11514 , H01L28/91
摘要： A memory cell includes a capacitor that includes a first metal layer and a second metal layer. The capacitor includes a ferroelectric layer disposed between the first metal layer and the second metal layer. The ferroelectric layer is a single layer of a bi-stable asymmetric crystalline material.
摘要翻译：存储单元包括包括第一金属层和第二金属层的电容器。电容器包括设置在第一金属层和第二金属层之间的铁电层。铁电层是单层双稳态不对称结晶材料。

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