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71. 发明公开

US20240194559A1 THERMAL DISSIPATION IN SEMICONDUCTOR DEVICES 审中-公开
公开(公告)号：US20240194559A1
公开(公告)日：2024-06-13
申请号：US18583411
申请日：2024-02-21
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Wen-Sheh Huang , Yu-Hsiang Chen , Chii-Ping Chen
IPC分类号： H01L23/367 , H01L21/8238 , H01L23/31 , H01L23/522 , H01L23/528 , H01L27/092 , H01L29/06 , H01L29/66 , H01L29/775 , H01L29/78
CPC分类号： H01L23/367 , H01L21/823821 , H01L21/823871 , H01L23/3171 , H01L23/5226 , H01L23/5283 , H01L23/5286 , H01L27/0922 , H01L28/10 , H01L29/0673 , H01L29/66545 , H01L29/66795 , H01L29/775 , H01L29/7851 , H01L2224/0401
摘要： A device includes a device layer comprising a first transistor; a first interconnect structure on a front-side of the device layer; and a second interconnect structure on a backside of the device layer. The second interconnect structure includes a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a conductive line electrically connected to the source/drain region of the first transistor through the contact; and a thermal dissipation path thermally connected to the device layer, the thermal dissipation path extending to a surface of the second interconnect structure opposite the device layer. The thermal dissipation path comprises a dummy via.

72. 发明授权

US12009326B2 SRAM bit cells with three-dimensional integration 有权
公开(公告)号：US12009326B2
公开(公告)日：2024-06-11
申请号：US17584507
申请日：2022-01-26
申请人： GlobalFoundries Singapore Pte. Ltd.
发明人： Hari Balan , Juan Boon Tan , Ramasamy Chockalingam , Wanbing Yi
IPC分类号： H01L23/00 , H01L23/528 , H01L25/00 , H01L25/065
CPC分类号： H01L24/08 , H01L23/5286 , H01L24/80 , H01L25/0657 , H01L25/50 , H01L2224/08145 , H01L2224/80895 , H01L2224/80896 , H01L2924/1437
摘要： Structures for a static random access memory bit cell and methods of forming a structure for a static random access memory bit cell. The structure includes a first field-effect transistor on a first substrate and a second field-effect transistor on a second substrate. The first field-effect transistor includes a first gate, and the second field-effect transistor includes a second gate. The structure further includes a first interconnect structure on the first substrate and a second interconnect structure on the second substrate. The first interconnect structure includes a first metal feature connected to the first gate, and the first metal feature has a first surface. The second interconnect structure includes a second metal feature connected to the second gate, and the second metal feature has a second surface that is connected to the first surface of the first metal feature.

73. 发明授权

US12009303B2 Integrated circuit semiconductor device 有权
公开(公告)号：US12009303B2
公开(公告)日：2024-06-11
申请号：US17374713
申请日：2021-07-13
申请人： Samsung Electronics Co., Ltd.
发明人： Jaechoon Kim , Seunggeol Ryu , Kyungsuk Oh , Keungbeum Kim , Eonsoo Jang
IPC分类号： H01L23/528 , H01L23/00 , H01L23/36 , H01L23/48 , H01L23/522
CPC分类号： H01L23/5286 , H01L23/36 , H01L23/481 , H01L23/5226 , H01L24/08 , H01L2224/08145
摘要： An integrated circuit semiconductor device includes a substrate having a first surface and a second surface opposite the first surface; a rail through via passing between the first surface and the second surface of the substrate; a cell-level portion arranged on the first surface and comprising a buried rail connected to the rail through via, a local conductive interconnect, a cell via connected to the local conductive interconnect, and a transistor connected to the local conductive interconnect; a signal wiring-level portion arranged on the cell-level portion and comprising a plurality of upper multi-layer interconnect layers connected to the local conductive interconnect via the cell via and upper vias connecting the upper multi-layer interconnect layers to each other; a dummy substrate arranged on the signal wiring-level portion; a bonding-level portion arranged between the signal wiring-level portion and the dummy substrate and bonding the signal wiring-level portion to the dummy substrate, and comprising a bonding pad connected to the upper via; a power delivery network-level portion arranged under the second surface of the substrate and comprising a plurality of lower multi-layer interconnect layers connected to the rail through via and lower vias connecting the lower multi-layer interconnect layers to each other; and an external connection terminal arranged under the power delivery network-level portion and connected to the lower multi-layer interconnect layers.

74. 发明公开

US20240186387A1 VIA AND SOURCE/DRAIN CONTACT LANDING UNDER POWER RAIL 审中-公开
公开(公告)号：US20240186387A1
公开(公告)日：2024-06-06
申请号：US18061495
申请日：2022-12-05
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Ruilong Xie , Min Gyu Sung , Chanro Park , Kangguo Cheng , Julien Frougier
IPC分类号： H01L29/417 , H01L21/28 , H01L21/8238 , H01L23/528 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/775
CPC分类号： H01L29/41733 , H01L21/28123 , H01L21/823807 , H01L21/823814 , H01L21/823871 , H01L21/823878 , H01L23/5286 , H01L27/092 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/775
摘要： A microelectronic structure including a first nano device that includes a plurality of first transistors and the plurality of first transistors includes at least one first source/drain. A second nano device includes a plurality of second transistors and the second nano device is oriented parallel to the first nano device. The plurality of second transistors includes at least two second source/drains. A gate cut located between the first nano device and the second nano device. A source/drain contact connected to the at least one first source/drain and is connected to at least one of the second source/drains. A portion of the source/drain contact extends parallel to the first nano device and the second nano device.

75. 发明公开

US20240186179A1 Methods of Forming Spacers for Semiconductor Devices Including Backside Power Rails 审中-公开
公开(公告)号：US20240186179A1
公开(公告)日：2024-06-06
申请号：US18420209
申请日：2024-01-23
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Li-Zhen Yu , Huan-Chieh Su , Lin-Yu Huang , Cheng-Chi Chuang , Chih-Hao Wang
IPC分类号： H01L21/768 , H01L21/02 , H01L23/528 , H01L23/532 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/78 , H01L29/786
CPC分类号： H01L21/7682 , H01L21/02603 , H01L21/76805 , H01L21/76895 , H01L23/5286 , H01L23/5329 , H01L29/0673 , H01L29/41733 , H01L29/42392 , H01L29/66545 , H01L29/66553 , H01L29/66636 , H01L29/66742 , H01L29/7848 , H01L29/78618 , H01L29/78696
摘要： Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a first source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line, the first conductive line defining a first side boundary of the air spacer.

76. 发明授权

US12002758B2 Backside metal-insulator-metal (MIM) capacitors extending through backside interlayer dielectric (BILD) layer or semiconductor layer and partly through dielectric layer 有权
公开(公告)号：US12002758B2
公开(公告)日：2024-06-04
申请号：US17453516
申请日：2021-11-04
申请人： International Business Machines Corporation
发明人： Ruilong Xie , Takeshi Nogami , Roy R. Yu , Balasubramanian Pranatharthiharan , Chih-Chao Yang
IPC分类号： H01L23/528 , H01L21/768 , H01L23/50 , H01L23/522 , H01L49/02
CPC分类号： H01L23/5286 , H01L21/76802 , H01L21/76877 , H01L23/50 , H01L23/5223 , H01L23/5226 , H01L28/60
摘要： A method of fabricating a semiconductor device comprises forming backside power rails in a dielectric layer arranged above a backside interlayer dielectric (BILD) layer or a semiconductor layer, forming a trench that extends through the BILD layer or the semiconductor layer and partly through the dielectric layer between the backside power rails, depositing a plurality of layers to form a backside metal-insulator-metal (MIM) capacitor in the trench, and forming a first contact to a first metal layer of the plurality of layers. Forming the first contact comprises forming first recesses in a second metal layer of the plurality of layers, and filling the first recesses with an insulative material. The method further comprises forming a second contact to the second metal layer. Forming the second contact comprises forming second recesses in the first metal layer, and filling the second recesses with the insulative material.

77. 发明授权

US11996402B2 Semiconductor device 有权
公开(公告)号：US11996402B2
公开(公告)日：2024-05-28
申请号：US17329669
申请日：2021-05-25
申请人： Samsung Electronics Co., Ltd.
发明人： In-Wook Oh , Byungyun Kang , Donghyun Kim , Hyungjune Kim , Jaebong Jung
IPC分类号： H01L27/02 , H01L21/8238 , H01L23/48 , H01L23/528 , H01L27/092 , H01L29/06 , H01L29/08 , H01L29/423 , H01L29/78 , H01L29/786
CPC分类号： H01L27/0207 , H01L21/823814 , H01L21/823821 , H01L21/823871 , H01L23/481 , H01L23/5286 , H01L27/092 , H01L29/0665 , H01L29/0847 , H01L29/42392 , H01L29/7851 , H01L29/78618 , H01L29/78696
摘要： Disclosed is a semiconductor device comprising a substrate that includes a cell region and a dummy region, a first metal layer on the substrate and including a dummy line on the dummy region, a power delivery network on a bottom surface of the substrate, and a first through via that penetrates the substrate and extends from the power delivery network toward the dummy line. The first through via is electrically connected to the dummy line. The power delivery network includes a plurality of lower lines and a pad line below the lower lines. The pad line is electrically connected through the lower lines to the first through via.

78. 发明授权

US11990412B2 Buried power rails located in a base layer including first, second, and third etch stop layers 有权
公开(公告)号：US11990412B2
公开(公告)日：2024-05-21
申请号：US17488389
申请日：2021-09-29
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Ruilong Xie , Stuart Sieg , Somnath Ghosh , Kisik Choi , Rishikesh Krishnan , Alexander Reznicek
IPC分类号： H01L23/528 , H01L21/311 , H01L21/768 , H01L21/8238 , H01L23/522 , H01L27/092 , H01L29/06 , H01L29/423
CPC分类号： H01L23/5286 , H01L21/31116 , H01L21/76816 , H01L21/76829 , H01L23/5226 , H01L23/5283 , H01L21/823871 , H01L27/092 , H01L29/0665 , H01L29/42392
摘要： Integrated chips and methods of forming the same include forming a stack of layers, including a device stack above a first sacrificial layer, above a substrate. The first sacrificial layer is replaced with a first etch stop layer. The substrate is removed, exposing a substrate-side of the stack of layers. The substrate-side of the stack of layers is etched to form a trench, stopping on the first etch stop layer. A conductive line is formed in the trench.

79. 发明授权

US11989046B2 Voltage regulator with power rail tracking 有权
公开(公告)号：US11989046B2
公开(公告)日：2024-05-21
申请号：US18165093
申请日：2023-02-06
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Haruki Mori , Hidehiro Fujiwara , Zhi-Hao Chang , Yangsyu Lin , Yu-Hao Hsu , Yen-Huei Chen , Hung-Jen Liao , Chiting Cheng
IPC分类号： G05F1/10 , G05F3/24 , G06F1/28 , H01L23/528 , H01L27/092
CPC分类号： G05F3/24 , G05F1/10 , G06F1/28 , H01L23/5286 , H01L27/092
摘要： Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.

80. 发明公开

US20240162152A1 AIRGAP SPACER FOR POWER VIA 审中-公开
公开(公告)号：US20240162152A1
公开(公告)日：2024-05-16
申请号：US18054991
申请日：2022-11-14
申请人： International Business Machines Corporation
发明人： Ruilong Xie , Lawrence A. Clevenger , Nicholas Anthony Lanzillo , Kisik Choi , Huai Huang
IPC分类号： H01L23/528 , H01L21/768 , H01L21/8234 , H01L23/532 , H01L27/088 , H01L29/06 , H01L29/417 , H01L29/66 , H01L29/775
CPC分类号： H01L23/5286 , H01L21/7682 , H01L21/823475 , H01L23/5329 , H01L27/088 , H01L29/0673 , H01L29/41733 , H01L29/66439 , H01L29/775
摘要： One or more systems, devices and/or methods of use provided herein relate to an airgap spacer for power via. The semiconductor device can comprise a power bar wired to a backside power rail, wherein the power bar is located between a first gate of a first field effect transistor (FET) and a second gate of a second FET at least a first airgap between the power bar and at least a portion of the first gate of the first FET and a second airgap between the power bar and at least a portion of the second gate of the second FET, wherein the at least the first airgap and the second airgap maintain parasitic capacitance in the semiconductor device below a threshold.

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