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71. 发明授权

US09401187B2 Integrated circuit and precharge/active flag generation circuit 有权
标题翻译：集成电路和预充电/有源标志生成电路
公开(公告)号：US09401187B2
公开(公告)日：2016-07-26
申请号：US14555442
申请日：2014-11-26
申请人： SK hynix Inc.
发明人： Hyun-Sung Lee
IPC分类号： G11C8/00 , H03K19/082 , G11C7/12 , G11C8/12 , G11C29/00 , H03M9/00 , H03M7/16 , H03M7/24 , H03K19/20
CPC分类号： G11C7/12 , G11C8/12 , G11C29/787 , G11C29/842 , H03K19/20 , H03M7/165 , H03M7/24 , H03M9/00
摘要： An integrated circuit includes a first stage including first logic gates each of which performs a first logic operation on a corresponding signal among first to Nth signals and a first bit of a binary code, and a second stage including second logic gates each of which performs a second logic operation on corresponding output signals of the first logic gates and is reset based on a second bit of the binary code.
摘要翻译：集成电路包括：第一级，包括第一逻辑门，每个第一逻辑门对第一至第N信号中的对应信号和二进制码的第一位执行第一逻辑运算;第二级包括第二逻辑门，每个逻辑门执行对第一逻辑门的相应输出信号进行第二逻辑运算，并基于二进制码的第二位复位。

72. 发明申请

US20100110807A1 Bitline Leakage Detection in Memories 有权
标题翻译：记忆中的位线泄漏检测
公开(公告)号：US20100110807A1
公开(公告)日：2010-05-06
申请号：US12608101
申请日：2009-10-29
申请人： Beena Pious , Xiaowei Deng , Wah Kit Loh , Jon Lescrenier
发明人： Beena Pious , Xiaowei Deng , Wah Kit Loh , Jon Lescrenier
IPC分类号： G11C7/00 , G11C29/00
CPC分类号： G11C29/842 , G11C11/22 , G11C11/41 , G11C29/02 , G11C29/025 , G11C29/12 , G11C2029/1204 , G11C2029/5006
摘要： An integrated circuit containing a memory and a sense amplifier. The integrated circuit also containing an extended delay circuit which extends the delay between when a precharged bitline is floated and when a wordline is enabled. A method of testing an integrated circuit to identify bitlines with excessive leakage.
摘要翻译：包含存储器和读出放大器的集成电路。该集成电路还包含扩展延迟电路，其扩展了预充电位线在浮动时和当字线被使能时的延迟。一种测试集成电路以识别具有过度泄漏的位线的方法。

73. 发明授权

US07492651B2 Semiconductor memory apparatus 有权
标题翻译：半导体存储装置
公开(公告)号：US07492651B2
公开(公告)日：2009-02-17
申请号：US11714562
申请日：2007-03-06
申请人： Khil-Ohk Kang
发明人： Khil-Ohk Kang
IPC分类号： G11C11/00
CPC分类号： G11C29/842 , G11C29/785
摘要： A first input unit, coupled to a repair checking node through a first fuse, is for inverting a logic level of the repair checking node in response to a first address. A second input unit, coupled to the repair checking node through a two or more second fuses, is for inverting a logic level of the repair checking node in response to a second address. The number of the second fuses corresponds to a delay time between a transfer path of the first address and a transfer path of the second address. A repair detecting signal generating unit is for generating a repair detecting signal in response to the logic level of the repair checking node. Other embodiments are also described.
摘要翻译：通过第一熔丝耦合到修复检查节点的第一输入单元用于响应于第一地址来反转修复检查节点的逻辑电平。通过两个或更多个第二保险丝耦合到修复检查节点的第二输入单元用于响应于第二地址来反转修复检查节点的逻辑电平。第二熔丝的数量对应于第一地址的传送路径和第二地址的传送路径之间的延迟时间。修复检测信号生成单元用于响应于修复检查节点的逻辑电平产生修复检测信号。还描述了其它实施例。

74. 发明授权

US07405973B2 Repair circuit of semiconductor memory device 有权
标题翻译：半导体存储器件修复电路
公开(公告)号：US07405973B2
公开(公告)日：2008-07-29
申请号：US11485281
申请日：2006-07-13
申请人： Young Soo Park
发明人： Young Soo Park
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C29/846 , G11C29/842
摘要： An embodiment of the present invention relates to a repair circuit of a semiconductor memory device. The repair circuit includes an address counter that sequentially generates a first column address signal and a second column address signal in response to a write enable signal or a read enable signal, a repair controller that generates a repair column address signal earlier than the second column address signal in response to the first column address signal, an address latch enable signal, a command enable signal, and a write enable signal, and a repair scramble unit that selects a repair cell in response to a repair I/O control signal and the repair column address signal. If an address on which a repair operation must be performed occurs, the repair controller directly receives the write enable signal or the read enable signal and activates the repair controller earlier than a general cell using a previous address, thereby offsetting an operating time consumed in the repair controller. Therefore, the operating speed of the repair cell can become faster than that of the general cell and the operating speed of the device can be improved accordingly.
摘要翻译：本发明的实施例涉及半导体存储器件的修复电路。修复电路包括地址计数器，其响应于写使能信号或读使能信号顺序地产生第一列地址信号和第二列地址信号，修复控制器产生比第二列地址早的修复列地址信号响应于第一列地址信号的信号，地址锁存使能信号，命令使能信号和写使能信号，以及修复加扰单元，其响应于修复I / O控制信号和修复而选择修复单元列地址信号。如果发生修理操作的地址发生，则修理控制器直接接收写入使能信号或读取使能信号，并使用先前地址比普通小区更早地激活修复控制器，从而抵消了在修理控制器。因此，修理单元的运行速度可以比通用单元的运行速度变快，并且可以相应地改善设备的运行速度。

75. 发明申请

US20080056033A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20080056033A1
公开(公告)日：2008-03-06
申请号：US11895250
申请日：2007-08-23
申请人： In-Chul Jeong
发明人： In-Chul Jeong
IPC分类号： G11C8/00 , G11C17/18 , G11C29/00
CPC分类号： G11C8/18 , G11C7/1045 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4087 , G11C29/842 , G11C2207/2272
摘要： A semiconductor memory device includes a delay time selecting portion for outputting, as a final read/write command, an internal read/write command that corresponds to an external read/write command and is synchronized with an external clock rising edge at a tRCD time without any delay when an address is applied before an address setup time based on the external clock rising edge of a previously set tRCD time, a decoder for decoding an address applied from an external portion with the read/write command to output a decoded address, and a selecting portion for receiving the decoded address to select a memory cell of a memory cell array in response to the final read/write command.
摘要翻译：半导体存储器件包括延迟时间选择部分，用于作为最终读/写命令输出与外部读/写命令相对应的内部读/写命令，并且在tRCD时间与外部时钟上升沿同步而没有基于先前设置的tRCD时间的外部时钟上升沿地址建立时间之前应用地址的任何延迟，用于对从外部施加的地址进行解码以用于输出解码的地址的解码器，以及选择部分，用于接收解码的地址以响应于最终的读/写命令来选择存储单元阵列的存储单元。

76. 发明授权

US06937536B2 Antifuse option for row repair 失效
标题翻译：防排污选项进行修复
公开(公告)号：US06937536B2
公开(公告)日：2005-08-30
申请号：US10664182
申请日：2003-09-17
申请人： Brian M. Shirley
发明人： Brian M. Shirley
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/842
摘要： A fuse option for a dynamic random access memory (DRAM) is provided to selectively slow row address signals when redundant rows of memory cells have been selected for use. The fuse option is blown when a redundant row is used to replace a defective row as identified during manufacture of a DRAM. The fuse is coupled to delay circuitry which has a known delay. When the fuse is blown after detecting a defective row, the delay circuitry is coupled in series with selected portions of a row address strobe (RAS) chain of circuitry used to propagate row address selection signals to the proper rows. This provides extra time needed for row address compare and override circuitry, which is not in series with the delay circuitry.
摘要翻译：提供用于动态随机存取存储器（DRAM）的保险丝选项，用于当存储器单元的冗余行已被选择使用时选择性地减慢行地址信号。当冗余行用于替换DRAM制造过程中识别的有缺陷的行时，熔断器选项被烧毁。熔丝耦合到具有已知延迟的延迟电路。当检测到有缺陷的行之后熔断器熔断时，延迟电路与用于将行地址选择信号传播到适当行的电路的行地址选通（RAS）链的选定部分串联耦合。这提供了与延迟电路不一致的行地址比较和覆盖电路所需的额外时间。

77. 发明申请

US20030142563A1 Semiconductor memory device and electronic information device using the same 失效
标题翻译：半导体存储器件和使用其的电子信息器件
公开(公告)号：US20030142563A1
公开(公告)日：2003-07-31
申请号：US10355344
申请日：2003-01-31
发明人： Kaname Yamano
IPC分类号： G11C007/00
CPC分类号： G11C29/84 , G11C29/842
摘要： In a semiconductor memory device, a redundant memory cell is accessible based on an input address signal by a redundant word line selection signal which is output in accordance with whether data read is to be performed or a memory operation other than data read is to be performed.
摘要翻译：在半导体存储器件中，冗余存储器单元可以通过根据是否要执行数据读取而输出的冗余字线选择信号的输入地址信号进行访问，还是要执行数据读取以外的存储器操作。

78. 发明授权

US06571348B1 Method of and apparatus for providing look ahead column redundancy access within a memory 有权
公开(公告)号：US06571348B1
公开(公告)日：2003-05-27
申请号：US09357698
申请日：1999-07-20
申请人： Terry T. Tsai , Daniel F. McLaughlin
发明人： Terry T. Tsai , Daniel F. McLaughlin
IPC分类号： G06F1100
CPC分类号： G11C29/842
摘要： A look ahead column redundancy circuit provides high speed memory access to both regular memory arrays and redundant memory arrays. In the preferred embodiment of the present invention, the information on both the address bus and the information on the next address bus are decoded by redundant column decoders in parallel. The decoded information from the redundant column decoders is then provided to a redundancy column pathway as the addressing information from the address bus and the next address bus is provided to a main column pathway. The information on the address bus is latched when beginning at a new column address. The information on the next address bus is latched for the next column address when operating in a burst cycle mode. The main column pathway preferably includes a latch, a main column decoder and a main column select circuit. A disable signal is also activated by the redundant column decoders if the addressing information for a current memory access operation corresponds to an address within the redundant memory array. When activated, the disable signal disables the main column select circuit within the main column pathway. If the addressing information for a current memory access operation does not correspond to an address within the redundant memory array, then the memory access operation is performed within the main memory array without any delays. Since the decoding is performed before the information is latched onto the column address bus, the proper pathway is selected without the need for any additional delay.

79. 发明授权

US06473360B2 Synchronous semiconductor memory device capable of high speed reading and writing 失效
标题翻译：能够高速读写的同步半导体存储器件
公开(公告)号：US06473360B2
公开(公告)日：2002-10-29
申请号：US09882037
申请日：2001-06-18
申请人： Tsukasa Ooishi
发明人： Tsukasa Ooishi
IPC分类号： G11C1300
CPC分类号： G11C29/842 , G11C7/1072 , G11C8/18
摘要： An address input is received earlier than data input, and a result of decoding of a column address at the time of writing and results of substitution determination for a redundancy memory column are held in a latch circuit corresponding to each bank. When the data arrives at the bank, the data is immediately written to each bank, utilizing the results of address processing. Operation frequency of the chip is not limited by the conventionally experienced wasteful wait time for the data in the process of writing, and efficient data input/output is possible.
摘要翻译：在数据输入之前接收地址输入，并且在写入时对列地址的解码结果以及冗余存储器列的替换结果的结果被保存在与每个存储体对应的锁存电路中。当数据到达银行时，利用地址处理结果将数据立即写入每个银行。芯片的工作频率不受传统的写入过程中数据浪费的等待时间的限制，有效的数据输入/输出也是可能的。

80. 发明授权

US06445625B1 Memory device redundancy selection having test inputs 有权
标题翻译：具有测试输入的存储器件冗余选择
公开(公告)号：US06445625B1
公开(公告)日：2002-09-03
申请号：US09648923
申请日：2000-08-25
申请人： Ebrahim Abedifard
发明人： Ebrahim Abedifard
IPC分类号： G11C700
CPC分类号： G11C29/24 , G11C29/842
摘要： Memory devices having redundancy selection circuitry are adapted to introduce test input signals into the redundancy selection path. The memory devices include a redundancy selection circuit having a latch for latching an incoming redundancy match signal. The latch includes a pair of reverse-coupled inverters. The latch is further coupled to receive one or more test input signals. The latch is responsive to one or more control signals to selectively generate the latched match signal from the incoming redundancy match signal or one of the test input signals. When the latched match signal is generated from the incoming redundancy match signal, the logic level of the latched match signal is independent of the logic level of any of the test input signals. When the latched match signal is generated from one of the test input signals, the logic level of the latched match signal is independent of the logic level of the incoming redundancy match signal. Such latch circuits are useful for controlling selection of a redundant element in a memory device during testing without significantly impacting the speed path of the redundancy selection circuitry during normal operation of the memory device.
摘要翻译：具有冗余选择电路的存储器件适于将测试输入信号引入到冗余选择路径中。存储器件包括冗余选择电路，其具有用于锁存进入的冗余匹配信号的锁存器。锁存器包括一对反向耦合的反相器。锁存器还被耦合以接收一个或多个测试输入信号。锁存器响应于一个或多个控制信号，以从输入的冗余匹配信号或测试输入信号中的一个选择性地产生锁存的匹配信号。当从输入冗余匹配信号产生锁存的匹配信号时，锁存的匹配信号的逻辑电平与任何测试输入信号的逻辑电平无关。当从一个测试输入信号产生锁存的匹配信号时，锁存的匹配信号的逻辑电平与进入的冗余匹配信号的逻辑电平无关。这样的锁存电路可用于在测试期间控制存储器装置中的冗余元件的选择，而不会在存储器件的正常操作期间显着影响冗余选择电路的速度路径。

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