专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明授权

US07742336B2 Trap-charge non-volatile switch connector for programmable logic 有权
公开(公告)号：US07742336B2
公开(公告)日：2010-06-22
申请号：US11982172
申请日：2007-11-01
申请人： Tomoko Ogura , Seiki Ogura , Nori Ogura
发明人： Tomoko Ogura , Seiki Ogura , Nori Ogura
IPC分类号： G11C16/04
CPC分类号： G11C16/0466 , G11C16/0475 , H01L27/115
摘要： A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.

72. 发明申请

US20100149899A1 TABLE LOOKUP VOLTAGE COMPENSATION FOR MEMORY CELLS 有权
标题翻译：表记忆体电池的电压补偿
公开(公告)号：US20100149899A1
公开(公告)日：2010-06-17
申请号：US12710153
申请日：2010-02-22
申请人： Boon-Aik ANG , Derric J.H. LEWIS
发明人： Boon-Aik ANG , Derric J.H. LEWIS
IPC分类号： G11C5/14
CPC分类号： G11C16/30 , G11C16/0458 , G11C16/0475
摘要： Systems and methods of regulating voltage at a memory cell are disclosed. An address for the memory cell is determined. Table lookups based on the address are performed. The table lookups yield voltage compensation parameters that can be used to set voltages on the terminals (e.g., source and drain) of the memory cell.
摘要翻译：公开了一种在存储器单元上调节电压的系统和方法。确定存储单元的地址。执行基于地址的表查找。表查找产生可用于设置存储器单元的端子（例如，源极和漏极）上的电压的电压补偿参数。

73. 发明申请

US20100149880A1 WINDOW ENLARGEMENT BY SELECTIVE ERASE OF NON-VOLATILE MEMORY CELLS 有权
标题翻译：通过选择性消除非易失性记忆细胞的窗口扩增
公开(公告)号：US20100149880A1
公开(公告)日：2010-06-17
申请号：US12485510
申请日：2009-06-16
申请人： Po Chou Chen , I Chen Yang , Hui Chih Lin , Yao Wen Chang
发明人： Po Chou Chen , I Chen Yang , Hui Chih Lin , Yao Wen Chang
IPC分类号： G11C16/04
CPC分类号： G11C16/0475 , G11C16/10 , G11C16/16
摘要： A method is described for enlarging a programming window of charge trapping memory cells in a virtual ground charge trapping memory EEPROM array. The method substantially eliminates second bit effects and program disturbances to nearby charge trapping memory cells.
摘要翻译：描述了一种用于放大虚拟地电荷俘获存储器EEPROM阵列中的电荷俘获存储器单元的编程窗口的方法。该方法基本上消除了附近电荷俘获存储器单元的第二位效应和程序干扰。

74. 发明申请

US20100117139A1 Methods of Operating Non-Volatile Memory Devices 有权
标题翻译：操作非易失性存储器件的方法
公开(公告)号：US20100117139A1
公开(公告)日：2010-05-13
申请号：US12614171
申请日：2009-11-06
申请人： Hang-Ting Lue
发明人： Hang-Ting Lue
IPC分类号： H01L29/792
CPC分类号： G11C16/0475 , G11C16/0483 , H01L27/115 , H01L27/11568
摘要： Methods of operating non-volatile memory devices are described. The memory devices comprise memory cells having an n-type semiconductor substrate and p-type source and drain regions disposed below a surface of the substrate and separated by a channel region. A tunneling dielectric layer is disposed above the channel region. A charge storage layer is disposed above the tunneling dielectric layer. An upper insulating layer is disposed above the charge storage layer, and a gate is disposed above the upper insulating multi-layer structure. A positive bias is applied to a word line of the memory device in a selected memory cell and a negative bias is applied to a bit line in the selected cell. In another memory device, opposite polarity voltages are applied to the bit line and the word line.
摘要翻译：描述操作非易失性存储器件的方法。存储器件包括具有n型半导体衬底的存储器单元和设置在衬底的表面下方并由沟道区分隔开的p型源极和漏极区域的存储器单元。隧道介电层设置在沟道区域的上方。电荷存储层设置在隧道电介质层的上方。上部绝缘层设置在电荷存储层上方，栅极设置在上绝缘多层结构的上方。对所选存储单元中的存储器件的字线施加正偏压，并将负偏压施加到所选择的单元中的位线。在另一个存储器件中，相反的极性电压被施加到位线和字线。

75. 发明授权

US07688612B2 Bit line structure for a multilevel, dual-sided nonvolatile memory cell array 失效
标题翻译：用于多层双面非易失性存储单元阵列的位线结构
公开(公告)号：US07688612B2
公开(公告)日：2010-03-30
申请号：US12080894
申请日：2008-04-07
申请人： Peter Wung Lee , Fu-Chang Hsu
发明人： Peter Wung Lee , Fu-Chang Hsu
IPC分类号： G11C5/06 , G11C5/02 , G11C16/04
CPC分类号： G11C16/24 , G11C11/5671 , G11C16/0475 , H01L27/115 , H01L27/11568 , H01L29/7923
摘要： A nonvolatile memory array includes a plurality of dual-sided charge-trapping dual-sided charge-trapping nonvolatile memory cells arranged in rows and columns. The dual-sided charge-trapping dual-sided charge-trapping nonvolatile memory cells on each column form at least one grouping that is arranged in a NAND series string of dual-sided charge-trapping dual-sided charge-trapping nonvolatile memory cells. Each NAND series string has a top select transistor and a bottom select transistor. Pairs of braided bit lines are connected in a braided columnar bit line structure such that each column of the dual-sided charge-trapping dual-sided charge-trapping nonvolatile memory cells is connected to an associated pair of braided bit lines.
摘要翻译：非易失性存储器阵列包括以行和列布置的多个双面电荷俘获双面电荷俘获非易失性存储器单元。每列上的双面电荷俘获双面电荷俘获非易失性存储器单元形成至少一个分组，其被布置在双面电荷俘获双面电荷俘获非易失性存储器单元的NAND串联串中。每个NAND串联串具有顶部选择晶体管和底部选择晶体管。编织的位线对被连接在编织柱状位线结构中，使得双面电荷捕获双面电荷捕获非易失性存储单元的每一列连接到相关的一对编织位线。

76. 发明申请

US20100074008A1 SECTOR CONFIGURE REGISTERS FOR A FLASH DEVICE GENERATING MULTIPLE VIRTUAL GROUND DECODING SCHEMES 有权
标题翻译：用于生成多个虚拟接地解码方案的闪存器件的部署配置寄存器
公开(公告)号：US20100074008A1
公开(公告)日：2010-03-25
申请号：US12234738
申请日：2008-09-22
申请人： Allan Parker
发明人： Allan Parker
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0475 , G11C11/5628 , G11C16/10 , G11C16/3477 , G11C16/3486 , H01L27/11568
摘要： Flash memory systems and methodologies are provided for providing multiple virtual ground decoding schemes in a flash device. The flash device can include sector configure registers for selecting a specific ground scheme at sector level. The sector configure registers can select a decoding scheme from multiple virtual ground decoding schemes including a conventional dual bit decoding scheme and a single program and erase entity decoding scheme. Since the single program and erase entity decoding scheme can emulate EEPROM functionality in a flash device, the combination of the conventional dual bit decoding scheme and the single program and erase entity decoding scheme can provide both dual bit high density storage and EEPROM emulation in a single flash device.
摘要翻译：闪存系统和方法被提供用于在闪存设备中提供多个虚拟地面解码方案。闪存器件可以包括用于在扇区级别选择特定接地方案的扇区配置寄存器。扇区配置寄存器可以从多个虚拟地解码方案中选择解码方案，包括常规双位解码方案和单个编程和擦除实体解码方案。由于单个编程和擦除实体解码方案可以模拟闪存器件中的EEPROM功能，传统的双位解码方案和单个编程和擦除实体解码方案的组合可以在单个编程和擦除实体解码方案中提供双位高密度存储和EEPROM仿真闪存设备。

77. 发明申请

US20100074007A1 FLASH MIRROR BIT ARCHITECTURE USING SINGLE PROGRAM AND ERASE ENTITY AS LOGICAL CELL 有权
标题翻译：使用单个程序和擦除实体作为逻辑单元的闪存镜像架构
公开(公告)号：US20100074007A1
公开(公告)日：2010-03-25
申请号：US12234737
申请日：2008-09-22
申请人： Allan Parker
发明人： Allan Parker
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0475 , G11C11/5628 , G11C16/10 , G11C16/3477 , G11C16/3486 , G11C2211/5641 , H01L27/11568
摘要： Flash memory systems and methods are provided for facilitating a single logical cell erasure in a flash memory device. Logical cell mapping is changed from using a single physical cell to using pair physical cells, thereby creating a single program and erase entity as a single logical cell. By mapping two adjacent physical cells as a single logical cell, the flash memory device can be programmed and erased on a single bit or variable bit length basis with conventional technologies. Various operations can be performed on a flash device on a basis of the single program and erase entity.
摘要翻译：闪存系统和方法被提供用于促进闪存设备中的单个逻辑单元擦除。逻辑单元映射从使用单个物理单元改变为使用对物理单元，从而创建单个程序并将实体擦除为单个逻辑单元。通过将两个相邻的物理单元映射为单个逻辑单元，可以使用常规技术以单个位或可变位长度编程和擦除闪存器件。可以在单个程序和擦除实体的基础上在闪存装置上执行各种操作。

78. 发明申请

US20100074005A1 EEPROM EMULATION IN FLASH DEVICE 有权
标题翻译：闪存器件中的EEPROM仿真
公开(公告)号：US20100074005A1
公开(公告)日：2010-03-25
申请号：US12234734
申请日：2008-09-22
申请人： Allan Parker
发明人： Allan Parker
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0475 , G11C11/5628 , G11C16/10 , G11C16/3477 , G11C16/3486 , G11C2211/5641 , H01L27/11568
摘要： Flash memory systems and methodologies are provided herein for providing byte alterability in a flash device. Logical cell mapping is changed from using a single physical memory cell to using two adjacent physical cells as a logical cell for emulating byte alterability. By mapping two adjacent physical cells as a single logical cell, the logical cell is a combination of neighboring drain/source regions, thereby creating a single program and erase entity. The single program and erase entities can allow for logical cell erase and program in either direction of a low voltage state or a high voltage state on a single bit or variable bit length basis. By employing the single program and erase entity, the subject innovation can provide a cost-effective approach to emulating electrically EEPROM in a flash device.
摘要翻译：本文提供了闪存系统和方法，用于在闪存设备中提供字节可变性。逻辑单元映射从使用单个物理存储器单元改变为使用两个相邻的物理单元作为用于模拟字节可变性的逻辑单元。通过将两个相邻的物理单元映射为单个逻辑单元，逻辑单元是相邻的漏极/源极区域的组合，由此创建单个的程序和擦除实体。单个程序和擦除实体可以允许在单个位或可变位长度的基础上在低电压状态或高电压状态的任一方向上进行逻辑单元擦除和编程。通过采用单个程序和擦除实体，本发明可以提供在闪存器件中仿真电EEPROM的成本有效的方法。

79. 发明申请

US20100027350A1 FLASH MEMORY PROGRAMMING AND VERIFICATION WITH REDUCED LEAKAGE CURRENT 有权
标题翻译：具有降低漏电流的闪存存储器编程和验证
公开(公告)号：US20100027350A1
公开(公告)日：2010-02-04
申请号：US12557721
申请日：2009-09-11
申请人： Ashot MELIK-MARTIROSIAN , Ed RUNNION , Mark RANDOLPH , Meng DING
发明人： Ashot MELIK-MARTIROSIAN , Ed RUNNION , Mark RANDOLPH , Meng DING
IPC分类号： G11C16/06 , G11C7/00 , G11C16/04
CPC分类号： G11C16/0475 , G11C16/12 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459
摘要： A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are biased with a positive source bias voltage to reduce or eliminate leakage current that might otherwise conduct through the target memory cells. A positive source bias voltage may also be applied to target memory cells during verification operations (program verify, soft program verify, erase verify) to reduce or eliminate leakage current that might otherwise introduce errors in the verification operations.
摘要翻译：根据本发明的示例性实施例配置的闪存系统采用虚拟接地阵列架构。在编程操作期间，目标存储器单元被偏置为正的源偏置电压，以减少或消除否则可能通过目标存储器单元传导的漏电流。在验证操作（程序验证，软程序验证，擦除验证）期间，也可以将正源偏置电压施加到目标存储器单元，以减少或消除可能在验证操作中引入错误的泄漏电流。

80. 发明申请

US20100008139A1 Memory devices having volatile and non-volatile memory characteristics and methods of operating the same 有权
标题翻译：具有易失性和非易失性存储器特性的存储器件及其操作方法
公开(公告)号：US20100008139A1
公开(公告)日：2010-01-14
申请号：US12458299
申请日：2009-07-08
申请人： Dong-Il Bae
发明人： Dong-Il Bae
IPC分类号： G11C16/04 , G11C14/00 , G11C7/00 , G11C7/06
CPC分类号： G11C11/404 , G11C11/005 , G11C14/0018 , G11C16/0475 , G11C2211/4016
摘要： Multi-bit semiconductor memory devices having both volatile and nonvolatile memory characteristics and methods of operating the same are disclosed, the semiconductor memory device including a floating body on an upper region of a substrate, a gate electrode on the floating body and electrically insulated from the floating body, source and drain regions on the substrate adjacent to the gate electrode and a charge trap layer between the floating body and the gate electrode, where first bit data is written in one of the charge trap layer and the floating body, and second bit data is written in one of the charge trap layer and the floating body in which first bit data is not written.
摘要翻译：公开了具有易失性和非易失性存储器特性的两位半导体存储器件及其操作方法，该半导体存储器件包括在衬底的上部区域上的浮体，浮动体上的栅电极，与栅电极相邻的衬底上的浮体，源极和漏极区域以及浮动体和栅电极之间的电荷陷阱层，其中第一位数据被写入电荷陷阱层和浮体之一，以及第二位数据被写入电荷陷阱层和不写第一位数据的浮动体之一。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式