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71. 发明申请

US20120042131A1 Flexible use of extended cache using a partition cache footprint 失效
标题翻译：灵活使用扩展缓存使用分区缓存占用空间
公开(公告)号：US20120042131A1
公开(公告)日：2012-02-16
申请号：US12856682
申请日：2010-08-15
申请人： Diane Garza Flemming , William A. Maron , Ram Raghavan , Mysore Sathyanarayana Srinivas , Basu Vaidyanathan
发明人： Diane Garza Flemming , William A. Maron , Ram Raghavan , Mysore Sathyanarayana Srinivas , Basu Vaidyanathan
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0811 , G06F12/0284 , G06F2212/502 , G06F2212/604
摘要： An approach is provided to identifying cache extension sizes that correspond to different partitions that are running on a computer system. The approach extends a first hardware cache associated with a first processing core that is included in the processor's silicon substrate with a first memory allocation from a system memory area, with the system memory area being external to the silicon substrate and the first memory allocation corresponding to one of the plurality of cache extension sizes that corresponds to one of the partitions that is running on the computer system. The approach further extends a second hardware cache associated with a second processing core also included in the processor's silicon substrate with a second memory allocation from the system memory area with the second memory allocation corresponding to another of the cache extension sizes that corresponds to a different partitions that is being executed by the second processing core.
摘要翻译：提供了一种方法来识别对应于在计算机系统上运行的不同分区的高速缓存扩展大小。该方法利用来自系统存储器区域的第一存储器分配来扩展与包括在处理器的硅衬底中的第一处理核心相关联的第一硬件高速缓存，系统存储器区域在硅衬底外部，并且第一存储器分配对应于多个缓存扩展大小中的一个对应于在计算机系统上运行的分区之一。该方法进一步扩展与第二处理核心相关联的第二硬件高速缓存，该第二处理核心还包括在处理器的硅衬底中，具有来自系统存储区域的第二存储器分配，其中第二存储器分配对应于对应于不同分区的另一个高速缓存扩展大小正在由第二处理核心执行。

72. 发明授权

US08103834B2 Coherence protocol with dynamic privatization 有权
标题翻译：一致性协议与动态私有化
公开(公告)号：US08103834B2
公开(公告)日：2012-01-24
申请号：US12260220
申请日：2008-10-29
申请人： Robert E. Cypher , Haakan E. Zeffer
发明人： Robert E. Cypher , Haakan E. Zeffer
IPC分类号： G06F12/00
CPC分类号： G06F12/0817 , G06F2212/502
摘要： Embodiments of the present invention provide a system that maintains coherence between cache lines in a computer system by using dynamic privatization. During operation, the system starts by receiving a request for a read-only copy of a cache line from a processor. The system then determines if the processor has privately requested the cache line a predetermined number of times. If so, the system provides a copy of the cache line to the processor in an exclusive state. Otherwise, the system provides a copy of the cache line to the processor in a shared state.
摘要翻译：本发明的实施例提供一种通过使用动态私有化来维持计算机系统中的高速缓存行之间的一致性的系统。在操作期间，系统从处理器接收到对高速缓存行的只读副本的请求开始。然后，系统确定处理器是否已经私人地请求高速缓存行预定次数。如果是这样，系统会以独占状态向处理器提供高速缓存行的副本。否则，系统将共享状态的缓存行的副本提供给处理器。

73. 发明授权

US07958309B2 Dynamic selection of a memory access size 有权
标题翻译：动态选择内存访问大小
公开(公告)号：US07958309B2
公开(公告)日：2011-06-07
申请号：US12024476
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Jerry D. Lewis , Warren E. Maule
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Jerry D. Lewis , Warren E. Maule
IPC分类号： G06F12/04
CPC分类号： G06F12/0886 , G06F12/0831 , G06F2212/1016 , G06F2212/502
摘要： A method of data processing in a processing unit supported by a memory hierarchy includes the processing unit performing a plurality of memory accesses to the memory hierarchy. The plurality of memory accesses includes one or more memory accesses targeting a full cache line of data. The processing unit monitors utilization of data accessed by the plurality of memory accesses, and based upon the utilization of the data, dynamically alters a memory access mode of operation so that a subsequent storage-modifying memory access targets less than a full cache line of data.
摘要翻译：由存储器层级支持的处理单元中的数据处理方法包括执行对存储器层次的多个存储器访问的处理单元。多个存储器访问包括针对全缓存数据行的一个或多个存储器访问。处理单元监视由多个存储器访问访问的数据的利用，并且基于数据的利用，动态地改变存储器访问操作模式，使得后续存储修改存储器访问目标小于完整高速缓存行数据。

74. 发明申请

US20110078382A1 Adaptive Linesize in a Cache 失效
标题翻译：缓存中的自适应线性化
公开(公告)号：US20110078382A1
公开(公告)日：2011-03-31
申请号：US12570440
申请日：2009-09-30
申请人： Kerry Bernstein , Moinuddin K. Qureshi
发明人： Kerry Bernstein , Moinuddin K. Qureshi
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0886 , G06F12/0864 , G06F2212/1016 , G06F2212/502
摘要： A mechanism is provided in a cache for emulating larger linesize in a substrate with smaller linesize using gang fetching and gang replacement. Gang fetching fetches multiple lines on a cache miss to ensure that all smaller lines that make up the larger line are resident in cache at the same time. Gang replacement evicts all smaller lines in cache that would have been evicted had the cache linesize been larger. The mechanism provides adaptive linesize using set dueling by dynamically selecting between multiple linsizes depending on which linesize performs the best at runtime. Set dueling dedicates a portion of sets of the cache to always use smaller linesize and dedicates one or more portions of the sets of cache to always emulate larger linesizes. One or more counters keep track of which linesize has the best performance. The cache uses that linesize for the remainder of the sets.
摘要翻译：在缓存中提供了一种机制，用于在使用帮派取出和帮派替换的较小线条模拟衬底中较大的线条化。 Gang提取在高速缓存未命中获取多行，以确保组成较大行的所有较小行同时驻留在缓存中。如果缓存线条化较大，Gang替换会将缓存中的所有较小的行排除在被驱逐之后。该机制通过根据哪些linesize在运行时执行最好的多个linsizes之间的动态选择，提供使用集合决策的自适应线性化。设置决斗专用于缓存的一部分，以始终使用较小的线条化，并且专用于高速缓存集中的一个或多个部分来始终模拟较大的线条。一个或多个计数器跟踪哪些linesize具有最佳性能。缓存使用其余集合的linesize。

75. 发明申请

US20100199050A1 PROACTIVE TECHNIQUE FOR REDUCING OCCURRENCE OF LONG WRITE SERVICE TIME FOR A STORAGE DEVICE WITH A WRITE CACHE 失效
标题翻译：用于通过写入缓存来降低存储设备长时间写入服务时间的实用技术
公开(公告)号：US20100199050A1
公开(公告)日：2010-08-05
申请号：US12363266
申请日：2009-01-30
申请人： Lee Charles LaFrese , Christopher Michael Sansone , Dana Fairbairn Scott , Yan Xu , Olga Yiparaki
发明人： Lee Charles LaFrese , Christopher Michael Sansone , Dana Fairbairn Scott , Yan Xu , Olga Yiparaki
IPC分类号： G06F12/08
CPC分类号： G06F12/0804 , G06F2212/502
摘要： Provided are techniques for introducing a delay in responding to host write requests. A percentage of fullness of a write cache is determined. Based on the determined percentage of fullness of the write cache (f), a low cache threshold (L), alpha (α), and k, an amount of delay to introduce into responding to a host write request is determined. Techniques wait the amount of the delay before responding to the host write request although the host write request processing has completed.
摘要翻译：提供了用于引入响应主机写请求的延迟的技术。确定写入高速缓存的百分比。基于所确定的写入高速缓存（f）的百分比，确定低速缓存阈值（L），α（α）和k，引入对主机写入请求的响应的延迟量。尽管主机写入请求处理已经完成，技术仍然等待主机写请求响应之前的延迟量。

76. 发明授权

US07721043B2 Managing write requests in cache directed to different storage groups 有权
标题翻译：管理针对不同存储组的缓存中的写入请求
公开(公告)号：US07721043B2
公开(公告)日：2010-05-18
申请号：US11621061
申请日：2007-01-08
申请人： Binny Sher Gill , Michael Thomas Benhase , Joseph Smith Hyde, II , Thomas Charles Jarvis , Bruce McNutt , Dharmendra Shantilal Modha
发明人： Binny Sher Gill , Michael Thomas Benhase , Joseph Smith Hyde, II , Thomas Charles Jarvis , Bruce McNutt , Dharmendra Shantilal Modha
IPC分类号： G06F12/00
CPC分类号： G06F12/0804 , G06F12/0873 , G06F12/121 , G06F2212/502
摘要： Provided are a method, system, and article of manufacture for managing write requests in cache directed to different storage groups. A determination is made of a high and low thresholds for a plurality of storage groups configured in a storage, wherein the high and low thresholds for one storage group indicate a high and low percentage of a cache that may be used to store write requests to the storage group. A determination is made of a number of tasks to assign to the storage groups based on the determined high and low thresholds for the storage groups, wherein each task assigned to one storage group destages write requests from the cache to the storage group.
摘要翻译：提供了一种用于管理针对不同存储组的缓存中的写请求的方法，系统和制品。确定在存储器中配置的多个存储组的高和低阈值，其中一个存储组的高和低阈值指示高速和低百分比的高速缓存，其可用于将写请求存储到存储组。基于确定的存储组的高和低阈值来确定分配给存储组的多个任务，其中分配给一个存储组的每个任务将来自高速缓存的写入请求转发到存储组。

77. 发明申请

US20090198915A1 DATA PROCESSING SYSTEM, PROCESSOR AND METHOD THAT DYNAMICALLY SELECT A MEMORY ACCESS SIZE 有权
标题翻译：数据处理系统，处理器和动态地选择存储器访问大小的方法
公开(公告)号：US20090198915A1
公开(公告)日：2009-08-06
申请号：US12024476
申请日：2008-02-01
申请人： LAKSHMINARAYANA B. ARIMILLI , Ravi K. Arimilli , Jerry D. Lewis , Warren E. Maule
发明人： LAKSHMINARAYANA B. ARIMILLI , Ravi K. Arimilli , Jerry D. Lewis , Warren E. Maule
IPC分类号： G06F12/08
CPC分类号： G06F12/0886 , G06F12/0831 , G06F2212/1016 , G06F2212/502
摘要： A method of data processing in a processing unit supported by a memory hierarchy includes the processing unit performing a plurality of memory accesses to the memory hierarchy. The plurality of memory accesses includes one or more memory accesses targeting a full cache line of data. The processing unit monitors utilization of data accessed by the plurality of memory accesses, and based upon the utilization of the data, dynamically alters a memory access mode of operation so that a subsequent storage-modifying memory access targets less than a full cache line of data.
摘要翻译：由存储器层级支持的处理单元中的数据处理方法包括执行对存储器层次的多个存储器访问的处理单元。多个存储器访问包括针对全缓存数据行的一个或多个存储器访问。处理单元监视由多个存储器访问访问的数据的利用，并且基于数据的利用，动态地改变存储器访问操作模式，使得后续存储修改存储器访问目标小于完整高速缓存行数据。

78. 发明申请

US20090049237A1 Methods and systems for multi-caching 有权
标题翻译：多缓存的方法和系统
公开(公告)号：US20090049237A1
公开(公告)日：2009-02-19
申请号：US12228171
申请日：2008-08-11
申请人： Raghupathy Sivakumar , Aravind Velayutham , Zhenyun Zhuang
发明人： Raghupathy Sivakumar , Aravind Velayutham , Zhenyun Zhuang
IPC分类号： G06F12/08 , G06F12/00 , G06F12/02
CPC分类号： G06F12/0813 , G06F12/0815 , G06F12/126 , G06F2212/502 , H04L67/2842 , H04L67/288
摘要： Provided are methods and systems for multi-caching. The methods and systems provided can enhance network content delivery performance in terms of reduced response time and increased throughput, and can reduce communication overhead by decreasing the amount of data that have to be transmitted over the communication paths.
摘要翻译：提供了多缓存的方法和系统。所提供的方法和系统可以在减少的响应时间和增加的吞吐量方面增强网络内容传递性能，并且可以通过减少必须通过通信路径发送的数据量来减少通信开销。

79. 发明申请

US20080168220A1 USING DIFFERENT ALGORITHMS TO DESTAGE DIFFERENT TYPES OF DATA FROM CACHE 有权
标题翻译：使用不同的算法从缓存中减少不同类型的数据
公开(公告)号：US20080168220A1
公开(公告)日：2008-07-10
申请号：US11621057
申请日：2007-01-08
申请人： Binny Sher Gill , Michael Thomas Benhase , Joseph Smith Hyde , Thomas Charles Jarvis , Bruce McNutt , Dharmendra Shantilal Modha
发明人： Binny Sher Gill , Michael Thomas Benhase , Joseph Smith Hyde , Thomas Charles Jarvis , Bruce McNutt , Dharmendra Shantilal Modha
IPC分类号： G06F12/08
CPC分类号： G06F12/0804 , G06F12/0866 , G06F12/124 , G06F2212/502
摘要： Provided are a method, system, and article of manufacture for using different algorithms to destage different types of data from cache. A first destaging algorithm is used to destage a first type of data to a storage for a first duration. A second destaging algorithm is used to destage a second type of data to the storage for a second duration.
摘要翻译：提供了一种使用不同算法从缓存中去除不同类型的数据的方法，系统和制品。使用第一个降级算法将第一类型的数据转储到第一个持续时间的存储器。第二种去度数算法被用于在第二持续时间内将存储的第二类型的数据转移到存储器中。

80. 发明申请

US20080147977A1 DESIGN STRUCTURE FOR AUTONOMIC MODE SWITCHING FOR L2 CACHE SPECULATIVE ACCESSES BASED ON L1 CACHE HIT RATE 审中-公开
标题翻译：基于L1高速缓存速率的L2高速缓存接入的自动模式切换设计结构
公开(公告)号：US20080147977A1
公开(公告)日：2008-06-19
申请号：US12037378
申请日：2008-02-26
申请人： Farnaz Toussi
发明人： Farnaz Toussi
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F11/3452 , G06F12/0897 , G06F2201/88 , G06F2201/885 , G06F2212/1016 , G06F2212/502
摘要： A design structure of a speculative access mechanism in a memory subsystem monitors hit rate of an L1 cache, and autonomically switches modes of speculative accesses to an L2 cache accordingly. If the L1 hit rate is less than a threshold, such as 50%, the speculative load mode for the L2 cache is set to load-cancel. If the L1 hit rate is greater than or equal to the threshold, the speculative load mode for the L2 cache is set to load-confirm. By autonomically adjusting the mode of speculative accesses to an L2 cache as the L1 hit rate changes, the performance of a computer system that uses speculative accesses to an L2 cache improves.
摘要翻译：存储器子系统中的推测访问机制的设计结构监视L1高速缓存的命中率，并相应地自主地切换对L2缓存的推测访问模式。如果L1命中率小于阈值（例如50％），则将L2高速缓存的推测负载模式设置为加载取消。如果L1命中率大于或等于阈值，则将L2高速缓存的推测加载模式设置为加载确认。通过自动调整L1命中率改变对L2缓存的推测访问模式，可以提高使用对L2缓存的推测性访问的计算机系统的性能。

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