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71. 发明申请

US20150124797A1 PRECISE TIME TAGGING OF EVENTS OVER AN IMPRECISE LINK 有权
标题翻译：精确时间标签的事件在一个明确的链接
公开(公告)号：US20150124797A1
公开(公告)日：2015-05-07
申请号：US14335437
申请日：2014-07-18
申请人： Samsung Electronics Co., Ltd.
发明人： Daniel BABITCH , Henry FALK
IPC分类号： H04L7/04 , H04W56/00 , H04J3/06
CPC分类号： H04L7/041 , G06F1/04 , G06F13/38 , H04J3/0644 , H04J3/0697 , H04W56/001
摘要： A system for precise timing and synchronization of events is provided. The system includes a first terminal including one or more first counters and a packetizer configured to create a packetized data stream having one or more event tags. The system also includes a second terminal that includes one or more second counters and a depacketizer. The second counter(s) is/are configured to count clock pulses generated by a first clock of the first terminal at a first clock rate. The depacketizer is configured to receive the packetized data stream and detect the event tag(s). When the at least one event tag is detected, the second terminal calculates a time at which the first terminal created the packetized data stream based on a count value of the second counter(s) and a count value of the first counter(s) of the first terminal.
摘要翻译：提供了一种精确定时和事件同步的系统。该系统包括包括一个或多个第一计数器的第一终端和被配置为创建具有一个或多个事件标签的分组化数据流的分组器。该系统还包括第二终端，其包括一个或多个第二计数器和解封装器。第二计数器被配置为以第一时钟速率对由第一终端的第一时钟产生的时钟脉冲进行计数。解包器被配置为接收分组数据流并检测事件标签。当检测到至少一个事件标签时，第二终端基于第二计数器的计数值和第一计数器的计数值来计算第一终端创建分组化数据流的时间第一个终端。

72. 发明授权

US08995214B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US08995214B2
公开(公告)日：2015-03-31
申请号：US13831520
申请日：2013-03-14
申请人： Kabushiki Kaisha Toshiba
发明人： Hiromitsu Komai
IPC分类号： G11C7/00 , G06F3/06 , G06F13/38 , G11C16/00
CPC分类号： G06F3/0646 , G06F13/38 , G11C7/1048 , G11C16/00 , G11C16/24 , G11C2207/005 , G11C2207/2245
摘要： According to one embodiment, a memory includes a temporary storage area which temporary stores data in a read/write operation to an array. The temporary storage area comprises a clamp FET connected between a first data bus and a second data bus, a first precharge FET connected between the first data bus and first potential, a second precharge FET connected between the second data bus and the first potential, a first storage area connected to the first data bus, and a second storage area connected to the second data bus. The control circuit is configured to generate a precharge state in which the first data bus is precharged to the first potential and the second data bus is precharged to a second potential lower than the first potential, when the data is transferred from the second storage area to the first storage area.
摘要翻译：根据一个实施例，存储器包括暂时存储对阵列的读/写操作的数据的临时存储区域。临时存储区域包括连接在第一数据总线和第二数据总线之间的钳位FET，连接在第一数据总线与第一电位之间的第一预充电FET，连接在第二数据总线与第一电位之间的第二预充电FET，连接到第一数据总线的第一存储区域和连接到第二数据总线的第二存储区域。控制电路被配置为当数据从第二存储区域传送到第一数据总线时被预充电到第一电位并且第二数据总线被预充电到低于第一电位的第二电位的预充电状态第一个存储区域。

73. 发明授权

US08990469B2 Portable electronic device docking station 有权
标题翻译：便携式电子设备对接站
公开(公告)号：US08990469B2
公开(公告)日：2015-03-24
申请号：US13365754
申请日：2012-02-03
申请人： Ryan Gordon Benhard , Ronald DeCamp
发明人： Ryan Gordon Benhard , Ronald DeCamp
IPC分类号： G06F1/00 , G06F13/14 , G06F13/38
CPC分类号： G06F1/1632 , G06F1/00 , G06F13/14 , G06F13/38 , H05K5/0247
摘要： A universal docking station for portable electronic devices is disclosed. In some embodiments, the docking station may utilize a universal interface to communicatively couple a portable electronic device to one or more inputs, displays, and/or accessory devices. In some embodiments, the universal interface may be a high-speed and/or super-speed universal data interface. In further embodiments, the universal docking station may be configured to provide electrical power to a portable electronic device. By utilizing a universal data interface, the universal docking station may be utilized with any portable electronic device having the universal data interface regardless of the manufacturer of the portable electronic devices.
摘要翻译：公开了一种用于便携式电子设备的通用坞站。在一些实施例中，对接站可以利用通用接口将便携式电子设备通信地耦合到一个或多个输入，显示器和/或附件设备。在一些实施例中，通用接口可以是高速和/或超速通用数据接口。在另外的实施例中，通用对接站可以被配置为向便携式电子设备提供电力。通过使用通用数据接口，通用对接站可以与具有通用数据接口的任何便携式电子设备一起使用，而不管便携式电子设备的制造商如何。

74. 发明申请

US20150032941A1 NON-VOLATILE MEMORY INTERFACE 有权
标题翻译：非易失性存储器接口
公开(公告)号：US20150032941A1
公开(公告)日：2015-01-29
申请号：US14128669
申请日：2013-07-25
申请人： Eng Hun Ooi , Robert J. Royer, JR. , Michael W. Williams , Jeffrey R. Wilcox , Ritesh B. Trivedi , Blaise Fanning
发明人： Eng Hun Ooi , Robert J. Royer, JR. , Michael W. Williams , Jeffrey R. Wilcox , Ritesh B. Trivedi , Blaise Fanning
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F3/0679 , G06F12/02 , G06F13/12 , G06F13/16 , G06F13/1668 , G06F13/38 , G06F13/4234 , G06F2212/7202
摘要： In an embodiment, a memory interface may send an indication that a request is being sent. The indication may be sent to a non-volatile memory via a point-to-point bus between a memory interface and the non-volatile memory. The memory interface may send the request to the non-volatile memory via the bus. The request may include an address that may be used to identify a location for storing or reading data. The non-volatile memory may acquire the request from the bus and process the request. After processing the request, the non-volatile memory may send an indication to the memory interface that indicates the non-volatile memory has a response to send to the memory interface. The memory interface may grant access to the bus to the non-volatile memory. After being granted access to the bus, the non-volatile memory may send the response to the memory interface.
摘要翻译：在一个实施例中，存储器接口可以发送请求被发送的指示。该指示可以经由存储器接口和非易失性存储器之间的点对点总线发送到非易失性存储器。存储器接口可以经由总线将请求发送到非易失性存储器。请求可以包括可用于标识用于存储或读取数据的位置的地址。非易失性存储器可以从总线获取请求并处理请求。在处理请求之后，非易失性存储器可以向存储器接口发送指示非易失性存储器具有发送到存储器接口的响应的指示。存储器接口可以向总线授予对非易失性存储器的访问。在被允许访问总线之后，非易失性存储器可以将响应发送到存储器接口。

75. 发明申请

US20140351469A1 Dynamic Address Change Optimizations 有权
标题翻译：动态地址更改优化
公开(公告)号：US20140351469A1
公开(公告)日：2014-11-27
申请号：US14456012
申请日：2014-08-11
申请人： Lexmark International, Inc.
发明人： Zachary Nathan Fister , Gregory Scott Woods
IPC分类号： G06F13/42 , G06F13/364
CPC分类号： G06K15/4095 , B41J2/17546 , G03G15/0863 , G03G2215/0697 , G06F12/0661 , G06F12/1433 , G06F13/364 , G06F13/38 , G06F13/404 , G06F13/4295
摘要： A method of setting an address of a component that includes determining a characterization value associated with a consumable, calculating a number of address change operations based upon the characterization value, and setting a last address generated from the number of address change operations as the new address of the component, wherein the characterization value is determined based upon a usage of the consumable.
摘要翻译：一种设置部件的地址的方法，包括确定与消耗品相关联的表征值，基于表征值计算地址变化操作的数量，以及将从地址改变操作数生成的最后地址设置为新地址，其中所述表征值是基于所述消耗品的使用来确定的。

76. 发明申请

US20140327685A1 IMAGE TRANSMITTING APPARATUS, IMAGE RECEIVING APPARATUS, AND CONTROL METHODS THEREOF 审中-公开
标题翻译：图像发送装置，图像接收装置及其控制方法
公开(公告)号：US20140327685A1
公开(公告)日：2014-11-06
申请号：US14069506
申请日：2013-11-01
申请人： Samsung Electronics Co., Ltd.
发明人： Chang-won LEE , Hak-jae KIM , Jung-keun KIM
IPC分类号： G06T1/20 , G06F13/38
CPC分类号： G06T1/20 , G06F13/38 , G09G5/006 , G09G2350/00 , G09G2370/04 , G09G2370/045 , G09G2370/10 , G09G2370/14 , H04N21/234354 , H04N21/2385 , H04N21/44209 , H04N21/6379
摘要： An image transmitting apparatus including: a processor to process image content; an interface to transmit a data stream of the processed image content to an image receiving apparatus; and a controller to control the data stream to be transmitted from the interface based on a transfer method, to receive status information indicating a status of the image receiving apparatus while the data stream is transmitted, and to change at least one of the transfer method of the data stream and information quantity of the data stream transmitted per unit time in response to the status of the image receiving apparatus being determined to be changed based on the status information.
摘要翻译：一种图像发送装置，包括：处理器，用于处理图像内容; 将经处理的图像内容的数据流发送到图像接收装置的接口; 以及控制器，其基于传送方法来控制要从接口发送的数据流，以在数据流被发送时接收指示图像接收装置的状态的状态信息，并且改变至少一个传送方法响应于基于状态信息确定要改变的图像接收装置的状态，每单位时间发送的数据流的数据流和信息量。

77. 发明申请

US20140307723A1 PERSONAL AREA NETWORK APPARATUS 审中-公开
标题翻译：个人网络设备
公开(公告)号：US20140307723A1
公开(公告)日：2014-10-16
申请号：US14252687
申请日：2014-04-14
申请人： Tri-County Excelsior Foundation
发明人： Robert J. Donaghey
IPC分类号： H04W4/00
CPC分类号： H04W4/008 , G06F13/10 , G06F13/38 , H04B7/2612 , H04L12/66 , H04L29/12254 , H04L51/00 , H04L51/08 , H04L61/2038 , H04L61/2069 , H04L67/02 , H04W4/80 , H04W8/245 , H04W48/16 , H04W60/00 , H04W76/00 , H04W76/10 , H04W84/12 , Y02D10/14 , Y02D10/151
摘要： A portable endpoint device comprises a first virtual device and a second virtual device integrated in a same single unit and configured such that the first virtual device and the second virtual device are configured to allow communication therewith as virtually different physical devices despite being integrated in the same single unit. In operation, the device is configured to receive a first signal from another endpoint device to indicate the availability of the another endpoint device for attachment; send, to the another endpoint device a second signal utilizing first scheduling-related information, the second signal including a first one of a plurality of identifiers for unique identification in association with the portable endpoint device; receive, from the another endpoint device a third signal that is sent in response to the second signal; and receive, from the another endpoint device data utilizing a second one of the identifiers for identification in association with the portable endpoint device.
摘要翻译：便携式终端设备包括集成在相同单个单元中的第一虚拟设备和第二虚拟设备，并且被配置为使得第一虚拟设备和第二虚拟设备被配置为允许与其通信作为实际上不同的物理设备，尽管集成在同一单元中单一单位在操作中，设备被配置为从另一端点设备接收第一信号以指示用于附接的另一端点设备的可用性; 使用第一调度相关信息向所述另一终端设备发送第二信号，所述第二信号包括与所述便携式终端设备相关联的用于唯一标识的多个标识符中的第一标识符; 从所述另一端点设备接收响应于所述第二信号发送的第三信号; 并且从所述另一端点设备接收使用与所述便携式终端设备相关联的用于标识的第二标识符的数据。

78. 发明申请

US20140281107A1 EFFICIENT INPUT/OUTPUT (I/O) OPERATIONS 有权
标题翻译：有效的输入/输出（I / O）操作
公开(公告)号：US20140281107A1
公开(公告)日：2014-09-18
申请号：US13835000
申请日：2013-03-15
申请人： GOOGLE INC.
发明人： Luiz Andre Barroso , James Laudon
IPC分类号： G06F13/40
CPC分类号： G06F13/4045 , G06F13/38 , G06F13/382 , G06F2213/0026
摘要： A system includes a bus, a processor operably coupled to the bus, a memory operably coupled to the bus, a plurality of input/output (I/O) devices operably coupled to the bus, where each of the I/O devices has a set of control registers, and a first shared I/O unit operably coupled to the bus. The first shared I/O unit has a plurality of shared functions and is configured to perform the shared functions, where the shared I/O functions are not included as functions on the I/O devices and the I/O devices and the processor interact with the first shared I/O unit to use one or more of the shared functions performed by the first shared I/O unit.
摘要翻译：系统包括总线，可操作地耦合到总线的处理器，可操作地耦合到总线的存储器，可操作地耦合到总线的多个输入/输出（I / O）设备，其中每个I / O设备具有一组控制寄存器，以及可操作地耦合到总线的第一共享I / O单元。第一共享I / O单元具有多个共享功能，并且被配置为执行共享功能，其中共享I / O功能不包括在I / O设备和I / O设备和处理器相互作用之间的功能中第一共享I / O单元使用由第一共享I / O单元执行的一个或多个共享功能。

79. 发明授权

US08811553B2 Edge based partial response equalization 有权
标题翻译：基于边缘的部分响应均衡
公开(公告)号：US08811553B2
公开(公告)日：2014-08-19
申请号：US13932561
申请日：2013-07-01
申请人： Rambus Inc.
发明人： Brian S. Leibowitz , Hae-Chang Lee , Jihong Ren , Ruwan Ratnayake
IPC分类号： H03H7/30 , H04B1/10 , H04L27/06 , H04L7/00
CPC分类号： H04L25/03057 , G06F13/38 , H04L25/03019 , H04L25/0307 , H04L2025/03369 , H04L2025/03617
摘要： A device implements data reception with edge-based partial response decision feedback equalization. In an example embodiment, the device implements a tap weight adapter circuit that sets the tap weights that are used for adjustment of a received data signal. The tap weight adapter circuit sets the tap weights based on previously determined data values and input from an edge analysis of the received data signal using a set of edge samplers. The edge analysis may include adjusting the sampled data signal by the tap weights determined by the tap weight adapter circuit. A clock generation circuit generates an edge clock signal to control the edge sampling performed by the set of edge samplers. The edge clock signal may be generated as a function of the signals of the edge samplers and prior data values determined by the equalizer.
摘要翻译：设备实现基于边缘的部分响应判决反馈均衡的数据接收。在一个示例性实施例中，该设备实现一个抽头权重适配器电路，其设置用于调整接收到的数据信号的抽头权重。抽头重量适配器电路基于先前确定的数据值设置抽头权重，并使用一组边缘采样器从接收数据信号的边缘分析输入。边缘分析可以包括通过由抽头权重适配器电路确定的抽头权重来调整采样的数据信号。时钟发生电路产生边沿时钟信号，以控制由边缘采样器组执行的边缘采样。可以根据边缘采样器的信号和由均衡器确定的先前数据值来生成边沿时钟信号。

80. 发明申请

US20140226178A1 USING A GRAPHICS ENGINE TO PROCESS PRINT REQUESTS 有权
标题翻译：使用图形引擎来处理打印请求
公开(公告)号：US20140226178A1
公开(公告)日：2014-08-14
申请号：US13997065
申请日：2011-10-01
申请人： Michael F. Fallon , Myles Wilde , Matthew J. Adiletta , Stewart Taylor
发明人： Michael F. Fallon , Myles Wilde , Matthew J. Adiletta , Stewart Taylor
IPC分类号： G06F3/12
CPC分类号： G06F3/1205 , G03G15/50 , G03G15/5083 , G06F3/122 , G06F3/1247 , G06F3/126 , G06F3/1279 , G06F3/1284 , G06F13/38 , G06K15/1856
摘要： Systems and methods of operating a computing system may involve utilizing an graphics engine to complete a print request. Upon receiving a request to print a scheduling management application may direct an application programming interface call to the graphics engine, and the graphics engine may process a print imaging instruction.
摘要翻译：操作计算系统的系统和方法可以涉及利用图形引擎来完成打印请求。在接收到打印调度管理应用程序的请求时，可以将应用编程接口调用指向图形引擎，并且图形引擎可以处理打印成像指令。

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