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71. 发明授权

US5966028A Programming architecture for a programmable integrated circuit employing test antifuses and test transistors 失效
标题翻译：采用测试反熔丝和测试晶体管的可编程集成电路的编程架构
公开(公告)号：US5966028A
公开(公告)日：1999-10-12
申请号：US929654
申请日：1997-09-17
申请人： James M. Apland
发明人： James M. Apland
IPC分类号： H02H9/00 , H03K17/22 , H03K19/177
CPC分类号： H03K19/17764 , H03K17/223 , H03K19/17736 , H03K19/1778 , H03K19/17796
摘要： A programmable integrated circuit (see FIG. 5) has a plurality of linearly extending wire segments with antifuses disposed between each wire segment and a plurality of linearly extending programming conductors that are perpendicular to the wire segments. A plurality of programming transistors are disposed between a corresponding respective one of the wire segments and a corresponding respective one of the programming conductors. A programming control conductor extending from a programming control driver is coupled to the gate electrode of each of the programming transistors as well as the gate electrode of a test transistor. A test antifuse is coupled in series with the test transistor. When the programming control conductor can drive the test transistor with an adequately high voltage to program the test antifuse, it is assumed that the programming control conductor can drive the programming transistor with an adequately high voltage to program the antifuses. The test transistor may be disposed on the programming control conductor at the opposite end from the programming control driver.
摘要翻译：可编程集成电路（参见图5）具有多个线性延伸的线段，其中反熔丝设置在每个线段和垂直于线段的多个线性延伸的编程导体之间。多个编程晶体管被布置在相应的一个线段和对应的相应的一个编程导体之间。从编程控制驱动器延伸的编程控制导体耦合到每个编程晶体管的栅电极以及测试晶体管的栅电极。测试反熔丝与测试晶体管串联耦合。当编程控制导体可以用足够高的电压驱动测试晶体管来对测试反熔丝进行编程时，假设编程控制导体可以用足够高的电压来驱动编程晶体管来编程反熔丝。测试晶体管可以设置在与编程控制驱动器相对的编程控制导体上。

72. 发明授权

US5898776A Security antifuse that prevents readout of some but not other information from a programmed field programmable gate array 失效
标题翻译：防止从编程的现场可编程门阵列读出一些而不是其他信息的安全反熔丝
公开(公告)号：US5898776A
公开(公告)日：1999-04-27
申请号：US754461
申请日：1996-11-21
申请人： James M. Apland , David D. Eaton , Andrew K. Chan
发明人： James M. Apland , David D. Eaton , Andrew K. Chan
IPC分类号： G01R31/317 , G01R31/3185 , H04L9/00
CPC分类号： G01R31/318519 , G01R31/31719 , G01R31/318555 , G01R31/31702 , G01R31/318558
摘要： A field programmable gate array has a security antifuse which when programmed prevents readout of data indicative of how the interconnect structure is programmed but which does not prevent readout of data indicative of which other antifuses are programmed. In some embodiments, the programming control shift registers adjacent the left and right sides are the field programmable gate array are disabled when the security antifuse is programmed but the programming control shift registers adjacent the top and bottom sides of the field programmable gate array are not disabled. A second security antifuse is also provided which when programmed disables a JTAG boundary scan register but does not disable a JTAG bypass register. Information can therefore be shifted through the JTAG test circuitry without allowing the JTAG circuitry to be used to extract information indicative of how the interconnect structure is programmed. Logic module and interface cell scan paths are provided and special test instructions are supported which allow test vectors to be loaded into the logic module and interface cell scan paths.
摘要翻译：现场可编程门阵列具有安全反熔丝，其在编程时防止读出指示互连结构如何编程的数据，但是不防止读出指示哪个其它反熔丝被编程的数据。在一些实施例中，当安全反熔丝被编程但是与现场可编程门阵列的顶侧和底侧相邻的编程控制移位寄存器未被禁用时，与左侧和右侧相邻的编程控制移位寄存器被禁用，。还提供了第二个安全反熔丝，当编程时禁用JTAG边界扫描寄存器，但不禁用JTAG旁路寄存器。因此，信息可以通过JTAG测试电路转移，而不允许JTAG电路提取指示互连结构如何编程的信息。提供逻辑模块和接口单元扫描路径，并支持特殊测试指令，允许将测试向量加载到逻辑模块和接口单元扫描路径中。

73. 发明授权

US5892370A Clock network for field programmable gate array 失效
标题翻译：现场可编程门阵列的时钟网络
公开(公告)号：US5892370A
公开(公告)日：1999-04-06
申请号：US781985
申请日：1997-01-03
申请人： David D. Eaton , Mukesh T. Lulla , Ker-Ching Liu
发明人： David D. Eaton , Mukesh T. Lulla , Ker-Ching Liu
IPC分类号： H02H9/00 , H03K17/22 , H03K19/177 , H03K7/38 , H03K19/00
CPC分类号： H03K17/223 , H03K19/177
摘要： A clock network of a field programmable gate array has a first clock bus extending across the chip in a first dimension. A clock pad can be coupled to the first clock bus if the clock network is to be driven from the clock pad. An output of a selected logic cell can be coupled to the first clock bus if the clock network is to be driven from a logic cell. To increase speed of the clock network, the first clock bus is segmented (in one embodiment, collinearly extending segments can be selectively coupled together via selectively programmable antifuses) so that only a short piece of the first clock bus is used to couple either the pad or the logic cell to the clock network in high speed applications.
摘要翻译：现场可编程门阵列的时钟网络具有在第一维度上跨越芯片延伸的第一时钟总线。如果时钟网络要从时钟焊盘驱动，则时钟焊盘可以耦合到第一个时钟总线。如果要从逻辑单元驱动时钟网络，则所选逻辑单元的输出可以耦合到第一时钟总线。为了增加时钟网络的速度，第一时钟总线被分段（在一个实施例中，共线延伸段可以通过有选择地可编程的反熔丝选择性地耦合在一起），使得仅使用第一时钟总线的短片来耦合焊盘或逻辑单元到高速应用中的时钟网络。

74. 发明授权

US5729468A Reducing propagation delays in a programmable device 失效
标题翻译：减少可编程器件中的传播延迟
公开(公告)号：US5729468A
公开(公告)日：1998-03-17
申请号：US520441
申请日：1995-08-29
申请人： William D. Cox
发明人： William D. Cox
IPC分类号： G06F17/50 , H03K19/177 , G06F17/10
CPC分类号： G06F17/5054 , H03K19/17704
摘要： Select sets of a logic function corresponding to an output of a first logic circuit are determined. These select sets are used to obtain a second logic circuit, the logic function corresponding to the output of which is the same as the logic function corresponding to the output of the first logic circuit. A propagation delay through the second logic circuit may be smaller than a corresponding delay through the first logic circuit. Sometimes, such a smaller propagation delay through the second logic circuit results in the second logic circuit having a smaller critical path delay. The second logic circuit may therefore have a greater maximum operating speed than the first logic circuit.
摘要翻译：确定与第一逻辑电路的输出对应的逻辑功能的选择集。这些选择组用于获得第二逻辑电路，对应于其输出的逻辑功能与对应于第一逻辑电路的输出的逻辑功能相同。通过第二逻辑电路的传播延迟可以小于通过第一逻辑电路的对应延迟。有时，通过第二逻辑电路的这种较小的传播延迟导致第二逻辑电路具有较小的关键路径延迟。因此，第二逻辑电路可以具有比第一逻辑电路更大的最大工作速度。

75. 发明授权

US5682106A Logic module for field programmable gate array 失效
标题翻译：现场可编程门阵列逻辑模块
公开(公告)号：US5682106A
公开(公告)日：1997-10-28
申请号：US755758
申请日：1996-09-18
申请人： William D. Cox , Benjamin W. Blair , Paige A. Kolze , Hua-Thye Chua
发明人： William D. Cox , Benjamin W. Blair , Paige A. Kolze , Hua-Thye Chua
IPC分类号： G11C17/18 , H03K19/177 , H03K7/38 , H03K19/173
CPC分类号： H03K19/17776 , G11C17/18 , H03K19/17704 , H03K19/17728 , H03K19/1778 , H03K19/17792
摘要： A programmable ASIC architecture allows the size of programming transistors to be reduced along with other parts of the device as advances in processing technology are made. Programming enable circuits are used to allow a programming address shift register having fewer bits to be used in the programming of antifuses. Methods of simultaneously programming multiple corresponding antifuses to speed ASIC programming are disclosed. Aspects of the architecture allow output protection for digital logic elements in modules to be eliminated, some testing transistors to be eliminated, the sizes of other testing transistors to be reduced, capacitances on interconnect wire segments to be reduced, some programming transistors to be eliminated, and the sizes of other programming transistors to be reduced.
摘要翻译：随着处理技术的进步，可编程ASIC架构允许与设备的其他部分一起减少编程晶体管的尺寸。编程使能电路用于允许在反熔丝的编程中使用具有较少位的编程地址移位寄存器。公开了同时编程多个对应的反熔丝以加速ASIC编程的方法。架构方面允许消除模块中的数字逻辑元件的输出保护，要消除一些测试晶体管，要降低其他测试晶体管的尺寸，减少互连线段上的电容，要消除的一些编程晶体管，并减小其他编程晶体管的尺寸。

76. 发明授权

US5600262A Integrated circuit facilitating simultaneous programming of multiple antifuses 失效
标题翻译：集成电路，便于同时编程多个反熔丝
公开(公告)号：US5600262A
公开(公告)日：1997-02-04
申请号：US540726
申请日：1995-10-11
申请人： Paige A. Kolze
发明人： Paige A. Kolze
IPC分类号： G11C17/18 , H03K19/177
CPC分类号： G11C17/18
摘要： To facilitate the simultaneous programming of multiple antifuses on an integrated circuit, a first current path is established from a first programming terminal (VPP1) of a programmable logic device through a first antifuse to be programmed and a second current path is established from a second programming terminal (VPP2) of the programmable logic device through a second antifuse to be programmed. By supplying the programming current for programming the first antifuse from a different terminal than the programming current for programming the second antifuse, the two antifuses can be programmed simultaneously with an adequate amount of programming current being supplied to each antifuse. A programming current multiplexer circuit is disclosed for selectively coupling either a first programming voltage (VPP1) terminal, a second programming voltage (VPP2), or a ground terminal (GND) to a programming bus and/or to an antifuse to be programmed. The first and second current paths can be established using multiple such programming current multiplexer circuits.
摘要翻译：为了便于在集成电路上同时对多个反熔丝进行编程，从可编程逻辑器件的第一编程端（VPP1）通过待编程的第一反熔丝建立第一电流路径，并且从第二编程建立第二电流路径可编程逻辑器件的端子（VPP2）通过要编程的第二反熔丝。通过提供用于编程来自不同于用于编程第二反熔丝的编程电流的不同端子的第一反熔丝的编程电流，可以在向每个反熔丝提供足够数量的编程电流的同时对两个反熔丝进行编程。公开了一种编程电流多路复用器电路，用于将第一编程电压（VPP1）端子，第二编程电压（VPP2）或接地端子（GND））选择性地耦合到编程总线和/或将要编程的反熔丝。可以使用多个这样的编程电流多路复用器电路来建立第一和第二电流路径。

77. 发明授权

US5502315A Electrically programmable interconnect structure having a PECVD amorphous silicon element 失效
标题翻译：具有PECVD非晶硅元件的电可编程互连结构
公开(公告)号：US5502315A
公开(公告)日：1996-03-26
申请号：US161504
申请日：1993-12-02
申请人： Hua-Thye Chua , Andrew K. Chan , John M. Birkner , Ralph G. Whitten , Richard L. Bechtel , Mammen Thomas
发明人： Hua-Thye Chua , Andrew K. Chan , John M. Birkner , Ralph G. Whitten , Richard L. Bechtel , Mammen Thomas
IPC分类号： H01L23/525 , H02L27/02
CPC分类号： H01L23/5252 , H01L2924/0002
摘要： In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for for forming a field programmable gate array with antifuses.
摘要翻译：在形成具有显着降低的漏电流的非晶硅反熔丝的一种方法中，在两个电极之间的反熔丝通孔中形成非晶硅膜。非晶硅膜使用等离子体增强化学气相沉积，优选在硅烷 - 氩气环境中并在200-500℃的温度下沉积，或者以各种反应性气体反应溅射。在另一种方法中，将氧化物层放置在两个非晶硅膜层之间。在另一种方法中，围绕氧化物层的非晶硅膜之一被掺杂。在另一个实施例中，在非晶硅膜上或下形成导电的，高度可扩散的材料层。选择非晶硅膜的特征尺寸和厚度，以在提供期望的编程电压的同时进一步最小化漏电流。还描述了用于形成具有反熔丝的现场可编程门阵列的方法。

78. 发明授权

US5448184A Method and apparatus for programming anti-fuse devices 失效
公开(公告)号：US5448184A
公开(公告)日：1995-09-05
申请号：US210000
申请日：1994-03-11
申请人： John O. Paivinen
发明人： John O. Paivinen
IPC分类号： G11C17/18 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1735 , G11C17/18
摘要： Improved apparatus and methods for programming anti-fuse devices utilized in programmable semiconductor chips are described. An anti-fuse device circuit is disclosed wherein an anti-fuse device is connected between two programming transistors, and each programming transistor is connected to a separate voltage supply bus and to a control bus network having, for example, a common control bus or separate control buses. Interconnection structures of anti-fuse devices can be formed and a targeted anti-fuse device can be programmed by connecting a programming voltage to the first associated supply bus, by connecting another voltage or ground potential to the second associated supply bus, and by turning on the appropriate control bus line or lines so that the programming transistors conduct to provide a voltage differential across the targeted anti-fuse device. Several anti-fuse device interconnection embodiments are discussed, and the choice of a particular scheme to use for fabricating a programmable chip is dependent on the desired design features and on ease of software implementation.

79. 发明授权

US5396127A Programmable application specific integrated circuit and logic cell therefor 失效
公开(公告)号：US5396127A
公开(公告)日：1995-03-07
申请号：US222726
申请日：1994-03-29
申请人： Andrew K. Chan , Hua-Thye Chua
发明人： Andrew K. Chan , Hua-Thye Chua
IPC分类号： H03K3/356 , H03K17/00 , H03K19/173 , H03K19/177
CPC分类号： H03K19/17736 , H03K19/1737 , H03K19/17704 , H03K19/17728 , H03K19/1774 , H03K19/1778 , H03K19/17792
摘要： A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.

80. 发明授权

US5327024A Field programmable antifuse device and programming method therefor 失效
标题翻译：现场可编程反熔丝装置及其编程方法
公开(公告)号：US5327024A
公开(公告)日：1994-07-05
申请号：US907904
申请日：1992-07-02
申请人： William D. Cox
发明人： William D. Cox
IPC分类号： G11C17/16 , H03K19/177
CPC分类号： H03K19/17748 , G11C17/16 , H03K19/17704 , H03K19/17736 , H03K19/1778 , H03K19/17796
摘要： A method for reducing the resistance of a programming path through a programmable antifuse from a programming voltage to ground. A previously programmed helper antifuse connected somewhere along a two branch programming path is connected to either the programming voltage or to ground. As a result, a three branch programming path is established from the programming voltage to the antifuse to be programmed and from the antifuse to be programmed to ground. By adding the third branch to the programming path, the resistance of the programming path is reduced, thereby allowing a higher voltage to be dropped across the antifuse to be programmed during programming and thereby allowing increased current flow through the antifuse to be programmed during programming. In another embodiment, two or more helper antifuses are used to establish a four or more branch programming path having a still lower resistance from the programming voltage to ground. In yet another embodiment, the programming of antifuses occurs in two steps. First, multiple antifuses are partially programmed separately. Second, these partially programmed antifuses are connected together in series so that a programming current can flow through all of the partially programmed antifuses at once to complete programming of the multiple antifuses.
摘要翻译：一种用于将通过可编程反熔丝的编程路径的电阻从编程电压降低到地的方法。连接在两个分支编程路径的某处的先前编程的辅助反熔丝连接到编程电压或接地。结果，从编程电压到要编程的反熔丝和从反熔丝编程到地的三个分支编程路径被建立。通过将第三分支添加到编程路径中，编程路径的电阻降低，从而允许在编程期间在待编程的反熔丝之间降低更高的电压，从而允许在编程期间通过反熔丝增加的电流流动被编程。在另一个实施例中，使用两个或更多个辅助反熔丝来建立四个或更多个分支编程路径，其具有从编程电压到地的更低的电阻。在另一个实施例中，反熔丝的编程分两步进行。首先，单独部分编程多个反熔丝。第二，这些部分编程的反熔丝串联连接在一起，使得编程电流可以一次流过所有部分编程的反熔丝，以完成对多个反熔丝的编程。

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