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71. 发明申请

US20100140680A1 Double Polysilicon Process for Non-Volatile Memory 审中-公开
标题翻译：用于非易失性存储器的双重多晶硅工艺
公开(公告)号：US20100140680A1
公开(公告)日：2010-06-10
申请号：US12331263
申请日：2008-12-09
申请人： Jeong Y. Choi , Kameswara K. Rao
发明人： Jeong Y. Choi , Kameswara K. Rao
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/66825
摘要： A process flow for creating a non-volatile memory cell, the process flow including the steps of forming a doped well in a semiconducting portion of a substrate, forming a gate dielectric layer on top of the substrate, depositing a first polysilicon layer on top of the gate dielectric layer, patterning and etching the first polysilicon layer, selectively oxidizing the first polysilicon layer, implanting lightly-doped source/drain regions into the well, forming sidewall spacers adjacent the first polysilicon layer, implanting source/drain regions into the well, thereby forming a channel area, depositing a dielectric layer on top of the first polysilicon layer, depositing a second polysilicon layer on top of the dielectric layer, forming a masking layer on the second polysilicon layer, and etching both the second polysilicon layer and the dielectric layer using the masking layer.
摘要翻译：一种用于产生非易失性存储器单元的工艺流程，所述工艺流程包括以下步骤：在衬底的半导体部分中形成掺杂阱，在所述衬底的顶部上形成栅极电介质层，在所述衬底的顶部上形成第一多晶硅层; 栅极电介质层，图案化和蚀刻第一多晶硅层，选择性地氧化第一多晶硅层，将轻掺杂的源极/漏极区域注入到阱中，形成与第一多晶硅层相邻的侧壁间隔物，将源极/漏极区域注入到阱中，从而形成通道区域，在第一多晶硅层的顶部上沉积电介质层，在介电层的顶部上沉积第二多晶硅层，在第二多晶硅层上形成掩模层，并蚀刻第二多晶硅层和电介质层层使用掩模层。

72. 发明授权

US07671401B2 Non-volatile memory in CMOS logic process 有权
标题翻译： CMOS逻辑过程中的非易失性存储器
公开(公告)号：US07671401B2
公开(公告)日：2010-03-02
申请号：US11262141
申请日：2005-10-28
申请人： Gang-feng Fang , Dennis Sinitsky , Wingyu Leung
发明人： Gang-feng Fang , Dennis Sinitsky , Wingyu Leung
IPC分类号： H01L29/788
CPC分类号： G11C16/0416 , G11C2216/10 , H01L27/115 , H01L27/11521 , H01L27/11558
摘要： A method, apparatus, and system in which an embedded memory fabricated in accordance with a conventional logic process includes one or more electrically-alterable non-volatile memory cells, each having a programming transistor, a read transistor and a control capacitor, which share a common floating gate electrode. The under-diffusion of the source/drain regions of the programming transistor and control capacitor are maximized. In one embodiment, the source/drain regions of the programming transistor are electrically shored by transistor punch-through (or direct contact).
摘要翻译：一种方法，装置和系统，其中根据常规逻辑处理器制造的嵌入式存储器包括一个或多个电可更改的非易失性存储单元，每个具有编程晶体管，读取晶体管和控制电容器，其共享一个普通浮栅电极。编程晶体管和控制电容器的源极/漏极区域的不足扩散最大化。在一个实施例中，编程晶体管的源极/漏极区域通过晶体管穿通（或直接接触）电触发。

73. 发明授权

US07633811B2 Non-volatile memory embedded in a conventional logic process and methods for operating same 有权
公开(公告)号：US07633811B2
公开(公告)日：2009-12-15
申请号：US12021286
申请日：2008-01-28
申请人： Gang-feng Fang , Wingyu Leung
发明人： Gang-feng Fang , Wingyu Leung
IPC分类号： G11C11/34 , G11C16/04 , G11C11/24
CPC分类号： H01L27/115 , G11C16/0416 , G11C16/10 , G11C16/3477 , G11C2216/10 , H01L27/11519 , H01L27/11521 , H01L27/11558
摘要： A non-volatile memory system including an array of cells, each having an access transistor and a capacitor sharing a floating gate. The access transistors in each row are fabricated in separate well regions, which are independently biased. Within each row, the source of each access transistor is coupled to a corresponding virtual ground line, and each capacitor structure is coupled to a corresponding word line. Alternately, the source of each access transistor in a column is coupled to a corresponding virtual ground line. Within each column, the drain of each access transistor is coupled to a corresponding bit line. Select memory cells in each row are programmed by band-to-band tunneling. Bit line biasing prevents programming of non-selected cells of the row. Programming is prevented in non-selected rows by controlling the well region voltages of these rows. Sector erase operations are implemented by Fowler-Nordheim tunneling.

74. 发明授权

US07533222B2 Dual-port SRAM memory using single-port memory cell 有权
标题翻译：使用单端口存储单元的双端口SRAM存储器
公开(公告)号：US07533222B2
公开(公告)日：2009-05-12
申请号：US11427785
申请日：2006-06-29
申请人： Wingyu Leung
发明人： Wingyu Leung
IPC分类号： G06F13/00
CPC分类号： G11C7/1075 , G11C11/406 , G11C11/40603
摘要： A dual-port memory system is implemented using single-port memory cells. An access arbiter having a synchronization circuit is used to prioritize and synchronize the access requests associated with the two ports. The access arbiter can also prioritize and synchronize refresh requests, in the case where the single-port memory cells require refresh. Access requests on the two ports and the refresh requests can be asynchronous. The access arbiter synchronizes the various requests by latching the requests into first-stage registers when a row access signal (RAS) is activated, and subsequently latching the contents of the first-stage registers into second-stage registers after a selected delay.
摘要翻译：使用单端口存储器单元实现双端口存储器系统。具有同步电路的访问仲裁器用于对与两个端口相关联的访问请求进行优先级排列和同步。在单端口存储器单元需要刷新的情况下，访问仲裁器还可以对刷新请求进行优先级排序并同步。两个端口上的访问请求和刷新请求可以是异步的。接入仲裁器通过在行接入信号（RAS）被激活时将请求锁存到第一级寄存器中，并且随后在选择的延迟之后将第一级寄存器的内容锁存到第二级寄存器中来同步各种请求。

75. 发明授权

US07447104B2 Word line driver for DRAM embedded in a logic process 有权
标题翻译：用于嵌入在逻辑过程中的DRAM的字线驱动器
公开(公告)号：US07447104B2
公开(公告)日：2008-11-04
申请号：US11559870
申请日：2006-11-14
申请人： Wingyu Leung
发明人： Wingyu Leung
IPC分类号： G11C8/00 , G11C7/00 , G11C5/14 , G11C7/02
CPC分类号： G11C8/08 , G11C11/4085 , G11C2207/104 , H01L27/10897
摘要： A word line driver is provided for accessing a DRAM cell embedded in a conventional logic process. The DRAM cell includes a p-channel access transistor coupled to a cell capacitor. The word line driver includes an n-channel transistor located in a p-well, wherein the p-well is located in a deep n-well. The deep n-well is located in a p-type substrate. A word line couples the drain of the n-channel transistor to the gate of the p-channel access transistor. A negative boosted voltage supply applies a negative boosted voltage to the p-well and the source of the n-channel transistor. The negative boosted voltage is less than ground by an amount equal to or greater than the threshold voltage of the p-channel access transistor. The deep n-well and the p-type substrate are coupled to ground. The various polarities can be reversed in another embodiment.
摘要翻译：提供了用于访问嵌入在常规逻辑处理中的DRAM单元的字线驱动器。 DRAM单元包括耦合到单元电容器的p沟道存取晶体管。字线驱动器包括位于p阱中的n沟道晶体管，其中p阱位于深n阱中。深n阱位于p型衬底中。字线将n沟道晶体管的漏极耦合到p沟道存取晶体管的栅极。负升压电压对p沟道和n沟道晶体管的源极施加负升压电压。负升压电压小于接地，等于或大于p沟道存取晶体管的阈值电压。深n阱和p型衬底耦合到地面。在另一个实施例中，各种极性可以颠倒。

76. 发明申请

US20080137438A1 Non-Volatile Memory Embedded In A Conventional Logic Process And Methods For Operating Same 有权
公开(公告)号：US20080137438A1
公开(公告)日：2008-06-12
申请号：US12021280
申请日：2008-01-28
申请人： Gang-feng Fang , Wingyu Leung
发明人： Gang-feng Fang , Wingyu Leung
IPC分类号： G11C16/04
CPC分类号： H01L27/115 , G11C16/0416 , G11C16/10 , G11C16/3477 , G11C2216/10 , H01L27/11519 , H01L27/11521 , H01L27/11558
摘要： A non-volatile memory system including an array of cells, each having an access transistor and a capacitor sharing a floating gate. The access transistors in each row are fabricated in separate well regions, which are independently biased. Within each row, the source of each access transistor is coupled to a corresponding virtual ground line, and each capacitor structure is coupled to a corresponding word line. Alternately, the source of each access transistor in a column is coupled to a corresponding virtual ground line. Within each column, the drain of each access transistor is coupled to a corresponding bit line. Select memory cells in each row are programmed by band-to-band tunneling. Bit line biasing prevents programming of non-selected cells of the row. Programming is prevented in non-selected rows by controlling the well region voltages of these rows. Sector erase operations are implemented by Fowler-Nordheim tunneling.

77. 发明授权

US6078547A Method and structure for controlling operation of a DRAM array 失效
标题翻译：用于控制DRAM阵列的操作的方法和结构
公开(公告)号：US6078547A
公开(公告)日：2000-06-20
申请号：US76608
申请日：1998-05-12
申请人： Wingyu Leung
发明人： Wingyu Leung
IPC分类号： G11C8/18 , G11C8/00
CPC分类号： G11C8/18
摘要： A method and structure for handling the refresh of a DRAM array so that the refresh has no effect on the external access. A system clock signal initiates activation and deactivation of elements of the DRAM array using a sequencer which subdivides each system clock signal period into three parts, thus providing four control signals fixed phase relationship per clock period.
摘要翻译：一种用于处理DRAM阵列的刷新以使刷新对外部访问没有影响的方法和结构。系统时钟信号使用将每个系统时钟信号周期分为三个部分的定序器来启动DRAM阵列的元件的激活和去激活，从而在每个时钟周期提供四个控制信号固定的相位关系。

78. 发明申请

US20190332274A1 PROCESSING ENGINES COUPLED WITH READ WRITE MODIFY MEMORY 审中-公开
公开(公告)号：US20190332274A1
公开(公告)日：2019-10-31
申请号：US16174268
申请日：2018-10-29
申请人： MoSys, Inc.
发明人： Michael J. Miller , Jay B. Patel , Michael J. Morrison
IPC分类号： G06F3/06 , H04L29/08 , G06F12/0895 , G06F12/00 , H04L29/12 , G06F9/38 , G06F12/0875
摘要： System, method, and apparatus for integrated main memory (MM) and configurable coprocessor (CP) chip for processing subset of network functions. Chip supports external accesses to MM without additional latency from on-chip CP. On-chip memory scheduler resolves all bank conflicts and configurably load balances MM accesses. Instruction set and data on which the CP executes instructions are all disposed on-chip with no on-chip cache memory, thereby avoiding latency and coherency issues. Multiple independent and orthogonal threading domains used: a FIFO-based scheduling domain (SD) for the I/O; a multi-threaded processing domain for the CP. The CP is an array of independent, autonomous, unsequenced processing engines processing on-chip data tracked by SD of external CMD and reordered per FIFO CMD sequence before transmission. Paired I/O ports tied to unique global on-chip SD allow multiple external processors to slave chip and its resources independently and autonomously without scheduling between the external processors.

79. 发明授权

US10339043B1 System and method to match vectors using mask and count 有权
公开(公告)号：US10339043B1
公开(公告)日：2019-07-02
申请号：US15853707
申请日：2017-12-22
申请人： MoSys, Inc.
发明人： Michael J Miller
IPC分类号： H04L12/745 , G06F12/02 , H04L29/12
摘要： An apparatus, system, and method is described for calculating a composite index into a customizable hybrid address space that is at least partially compressed to locate a longest prefix match (“LPM”) of a prefix string comprised of a plurality of multi-bit strides (“MBSs”). The device comprises: a mask-and-count logic for generating a base index into memory for a first MBS whose addresses are not compressed; a logical-shift apparatus that selectively uses a variable portion of the second MBS to generate an offset index from the given base index per an amount the second MBS addresses were actually compressed; and an add logic that adds the base index to the offset index to form the composite index that locates the LPM using a single access into memory. A compressed vector contains compression information of the second MBS in an information density format greater than a single bit to a single address.

80. 发明申请

US20180173433A1 Integrated Main Memory And Coprocessor With Low Latency 审中-公开
公开(公告)号：US20180173433A1
公开(公告)日：2018-06-21
申请号：US15898659
申请日：2018-02-18
申请人： MoSys, Inc.
发明人： Michael J. Miller , Jay B. Patel , Michael J. Morrison
IPC分类号： G06F3/06 , G06F12/0895 , G06F9/38 , G06F12/00 , G06F12/0875 , H04L29/12 , H04L29/08
CPC分类号： G06F3/0611 , G06F3/0659 , G06F3/067 , G06F9/3877 , G06F12/00 , G06F12/0875 , G06F12/0895 , G06F2212/1024 , G06F2212/452 , G06F2212/604 , H04L29/12 , H04L67/1017 , H04L67/2842
摘要： System, method, and apparatus for integrated main memory (MM) and configurable coprocessor (CP) chip for processing subset of network functions. Chip supports external accesses to MM without additional latency from on-chip CP. On-chip memory scheduler resolves all bank conflicts and configurably load balances MM accesses. Instruction set and data on which the CP executes instructions are all disposed on-chip with no on-chip cache memory, thereby avoiding latency and coherency issues. Multiple independent and orthogonal threading domains used: a FIFO-based scheduling domain (SD) for the I/O; a multi-threaded processing domain for the CP. The CP is an array of independent, autonomous, unsequenced processing engines processing on-chip data tracked by SD of external CMD and reordered per FIFO CMD sequence before transmission. Paired I/O ports tied to unique global on-chip SD allow multiple external processors to slave chip and its resources independently and autonomously without scheduling between the external processors.

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