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71. 发明申请

US20060140192A1 Flexible mesh structure for hierarchical scheduling 有权
标题翻译：灵活的网格结构，用于分层调度
公开(公告)号：US20060140192A1
公开(公告)日：2006-06-29
申请号：US11024957
申请日：2004-12-29
申请人： Sanjeev Jain , Gilbert Wolrich
发明人： Sanjeev Jain , Gilbert Wolrich
IPC分类号： H04J3/14 , H04J1/16 , H04L1/00 , H04L12/26 , H04L12/56 , H04L12/28
CPC分类号： H04L47/24 , H04L47/50
摘要： Systems and methods employing a flexible mesh structure for hierarchical scheduling are disclosed. The method generally includes reading a packet grouping configured in a two dimensional mesh structure of N columns, each containing M packets, selecting and promoting a column best packet from each column to a final row containing N packets, reading, selecting and promoting a final best packet from the final row to a next level in the hierarchy. Each time a final best packet is selected and promoted, the mesh structure can be refreshed by replacing the packet corresponding to the final best packet, and reading, selecting and promoting a column best packet from the column containing the replacement packet to the final row. As only the column containing the replacement packet and the final row are read and compared for each refresh, the mesh structure results in reduced read and compare cycles for schedule determination.
摘要翻译：公开了采用柔性网格结构进行分层调度的系统和方法。该方法通常包括读取以N列的二维网格结构配置的分组分组，每个分组包含M个分组，从每列选择并提升列最佳分组到包含N个分组的最后一行，读取，选择和促进最终最佳分组从最后一行到层次结构中的下一个级别。每次选择和提升最终最佳分组时，可以通过替换与最终最佳分组相对应的分组来刷新网格结构，并从包含替换分组的列到最后一行读取，选择和促进列最佳分组。由于只有包含替换数据包和最后一行的列被读取并进行比较才能进行每次刷新，所以网格结构导致读取和比较周期减少以用于计划确定。

72. 发明申请

US20060062159A1 Determining the presence of IP multicast routers 有权
公开(公告)号：US20060062159A1
公开(公告)日：2006-03-23
申请号：US11265432
申请日：2005-11-01
申请人： Claus Jensen
发明人： Claus Jensen
IPC分类号： H04L12/28
CPC分类号： H04L12/1886 , H04L12/185 , H04L45/02 , H04L45/026 , H04L45/16
摘要： A method for determining the presence of the multicast routers using existing protocols is disclosed. The method includes setting a time interval between a first set of query messages to each of a plurality of routers to a number greater than a querier timeout period used by the routers. The querier timeout period transitions each of the routers into a querier. The presence of each of the routers is revealed by sending a second set of query messages. Membership report messages are then sent to the routers.

73. 发明申请

US20050212563A1 Efficient detection of multiple assertions in a bus 有权
标题翻译：在总线中有效检测多个断言
公开(公告)号：US20050212563A1
公开(公告)日：2005-09-29
申请号：US10796957
申请日：2004-03-11
申请人： Shane Bell
发明人： Shane Bell
IPC分类号： G06F13/42 , H03K19/20
CPC分类号： G06F13/4243
摘要： A mechanism detects multiple assertions in a bus efficiently by encoding each of N bus lines with log2(N) pairs of bit lines.
摘要翻译：一种机制通过用N个总线与N（N）个对（N）位对N总线进行编码来有效地检测总线中的多个断言。

74. 发明申请

US20050198400A1 Systems and methods using nic-based prefetching for host TCP context lookup 失效
标题翻译：使用基于nic的预取来进行主机TCP上下文查找的系统和方法
公开(公告)号：US20050198400A1
公开(公告)日：2005-09-08
申请号：US10748415
申请日：2003-12-30
申请人： David Minturn
发明人： David Minturn
IPC分类号： G06F15/16
CPC分类号： H04L49/901 , G06F12/1018 , G06F12/1081 , G06F2212/303 , H04L49/90
摘要： Systems and methods using network interface card-based (NIC-based) prefetching for host TCP context lookup are disclosed. The process generally includes hashing, by the NIC, a packet received over the network, computing a host hash table cache line in a host memory using the hash value and using a hash table pages table containing host memory physical page addresses of a host hash table, and computing a host context table cache line in a host memory using the hash value and using a context table pages table containing host memory physical page addresses of a host context table. The NIC may be initialized with the hash table pages table and the context table pages table as well as with the a set number of hash node entries in the hash table of the host memory.
摘要翻译：公开了使用基于网络接口卡（基于NIC）的预取主机TCP上下文查找的系统和方法。该过程通常包括由NIC散布通过网络接收的分组，使用散列值计算主机存储器中的主机散列表高速缓存行并使用包含主机存储器的主机存储器物理页地址的哈希表页表，以及使用散列值计算主机存储器中的主机上下文表高速缓存行，并使用包含主机上下文表的主机存储器物理页地址的上下文表页表。可以使用哈希表页表和上下文表页表以及主机存储器的散列表中的一组哈希节点条目来初始化NIC。

75. 发明申请

US20050140432A1 Supplying a ramp voltage to an amplifier 有权
标题翻译：向放大器提供斜坡电压
公开(公告)号：US20050140432A1
公开(公告)日：2005-06-30
申请号：US10748200
申请日：2003-12-31
申请人： Vijayakumaran Nair , Kevin McCarville
发明人： Vijayakumaran Nair , Kevin McCarville
IPC分类号： H03F1/30 , H03G3/34 , H03F1/02
CPC分类号： H03F1/305 , H03G3/348
摘要： A common mode ramp voltage generator may be used in generating a ramp voltage for the amplifier and thereby eliminating or reducing pop noise.
摘要翻译：可以使用共模斜坡电压发生器来产生放大器的斜坡电压，从而消除或减少流行噪声。

76. 发明申请

US20050033884A1 Communication between processors 有权
标题翻译：处理器之间的通信
公开(公告)号：US20050033884A1
公开(公告)日：2005-02-10
申请号：US10931454
申请日：2004-09-01
申请人： Gilbert Wolrich , Debra Bernstein , Matthew Adiletta
发明人： Gilbert Wolrich , Debra Bernstein , Matthew Adiletta
IPC分类号： G06F13/42 , G06F13/12
CPC分类号： G06F13/4269
摘要： A method of communicating between a first and a second processor includes the first processor sending a datum over a common control bus, and the second processor receiving the datum from the common control bus.
摘要翻译：在第一和第二处理器之间进行通信的方法包括：第一处理器通过公共控制总线发送数据，第二处理器从公共控制总线接收数据。

77. 发明申请

US20050013293A1 Statistics collection framework for a network processor 失效
标题翻译：网络处理器的统计收集框架
公开(公告)号：US20050013293A1
公开(公告)日：2005-01-20
申请号：US10620488
申请日：2003-07-15
申请人： Ravi Sahita
发明人： Ravi Sahita
IPC分类号： H04L12/26 , H04L12/56
CPC分类号： H04L45/7453 , H04L43/028
摘要： Methods and devices for wire-speed packet statistics collection in a network processor are disclosed. A control-plane process maintains a dynamic packet rule set, each rule specifying a packet offset, a data pattern to be found at that offset, and an action to be taken if that data pattern is found. One or more packet processing engines process the packet rule set for incoming packets and take actions such as updating counters in a counter table when a rule evaluates true. The control-plane process can access the counter table to monitor which rules are triggered by packet traffic with what frequency.
摘要翻译：公开了网络处理器中线速分组统计信息收集的方法和装置。控制平面过程维护动态分组规则集，每个规则指定分组偏移量，在该偏移处找到的数据模式，以及如果找到该数据模式将采取的动作。一个或多个分组处理引擎处理传入分组的分组规则集，并且当规则评估为真时，采取诸如在计数器表中更新计数器的动作。控制平面过程可以访问计数器表，以监视以什么频率的数据包流量触发哪些规则。

78. 发明申请

US20040255019A1 Speed sensitive content delivery in a client-server network 有权
标题翻译：在客户端 - 服务器网络中快速敏感的内容传送
公开(公告)号：US20040255019A1
公开(公告)日：2004-12-16
申请号：US10840067
申请日：2004-05-05
申请人： Intel Corporation, a Delaware corporation
发明人： Cary A. Jardin , Eric Varsanyi , Phil J. Duclos , Vincent M. Padua , Robert C. Trescott JR.
IPC分类号： G06F015/173
CPC分类号： H04L29/12594 , H04L29/06 , H04L29/12009 , H04L29/12783 , H04L29/1282 , H04L47/10 , H04L47/263 , H04L47/283 , H04L61/30 , H04L61/35 , H04L61/6013 , H04L67/02 , H04L67/306 , H04L67/42 , H04L69/28 , H04L69/329
摘要： The response time from a client on a network is measured and a destination address is selected based on the measured response time. The client requests an address from the network. The network may be a local network or a wide area network such as the Internet. The response time of the client is measured to determine the optimum speed at which the client may operate. The measured response time is communicated to the server, where a destination address is selected based on the requested address and the measured response time. The client may then be connected to the destination address.
摘要翻译：测量来自网络上的客户端的响应时间，并且基于测量的响应时间来选择目的地地址。客户端从网络请求一个地址。网络可以是本地网络或诸如因特网的广域网。测量客户端的响应时间以确定客户端可以操作的最佳速度。测量的响应时间被传送到服务器，其中基于所请求的地址和测量的响应时间来选择目的地地址。客户端然后可以连接到目的地址。

79. 发明申请

US20040205316A1 Method for memory allocation and management using push/pop apparatus 失效
公开(公告)号：US20040205316A1
公开(公告)日：2004-10-14
申请号：US10746876
申请日：2003-12-23
申请人： Intel Corporation, a Delaware corporation
发明人： Donald F. Hooper , Gilbert Wolrich , Matthew J. Adiletta , William R. Wheeler
IPC分类号： G06F012/00
CPC分类号： G06F12/023
摘要： An apparatus and method for memory allocation with digital processing systems comprises a first memory bank, a hardware register, and a processing circuit configured to write the contents of the hardware register to a memory address in the first memory bank, and to write the memory address to the hardware register. In an embodiment, a pointer list containing memory pointer values may be maintained in the first memory bank. The first memory bank may contain associated data buffers, and a second memory bank may contain corresponding data buffers such that an associated data buffer and a corresponding data buffer may be located from a single memory pointer value.

80. 发明申请

US20040188704A1 Buffering and interleaving data transfer between a chipset and memory modules 有权
公开(公告)号：US20040188704A1
公开(公告)日：2004-09-30
申请号：US10777921
申请日：2004-02-11
申请人： Intel Corporation, a Delaware corporation
发明人： John B. Halbert , Jim M. Dodd , Chung Lam , Randy M. Bonella
IPC分类号： H01L031/111
CPC分类号： G06F13/4234
摘要： Providing electrical isolation between the chipset and the memory data is disclosed. The disclosure includes providing at least one buffer in a memory interface between a chipset and memory modules. Each memory module includes a plurality of memory ranks. The buffers allow the memory interface to be split into first and second sub-interfaces. The first sub-interface is between the chipset and the buffers. The second sub-interface is between the buffers and the memory modules. The method also includes interleaving output of the buffers, and configuring the buffers to properly latch the data being transferred between the chipset and the memory modules. The first and second sub-interfaces operate independently but in synchronization with each other.

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