专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明申请

US20100115228A1 Unified address space architecture 有权
标题翻译：统一的地址空间架构
公开(公告)号：US20100115228A1
公开(公告)日：2010-05-06
申请号：US12263321
申请日：2008-10-31
申请人： Michael Parker , Timothy J. Johnson , Laurence S. Kaplan , Steven L. Scott , Robert Alverson , Skef Iterum
发明人： Michael Parker , Timothy J. Johnson , Laurence S. Kaplan , Steven L. Scott , Robert Alverson , Skef Iterum
IPC分类号： G06F12/00 , G06F15/173
CPC分类号： G06F12/0284
摘要： A multiprocessor computer system has a plurality of first processors having a first addressable memory space, and a plurality of second processors having a second addressable memory space. The second addressable memory space is of a different size than the first addressable memory space, and the first addressable memory space and second addressable memory space comprise a part of the same common address space.
摘要翻译：多处理器计算机系统具有多个具有第一可寻址存储器空间的第一处理器和具有第二可寻址存储器空间的多个第二处理器。第二可寻址存储器空间的尺寸与第一可寻址存储器空间不同，并且第一可寻址存储器空间和第二可寻址存储器空间包括相同公共地址空间的一部分。

72. 发明申请

US20090292900A1 MULTIPROCESSOR NODE CONTROL TREE 有权
标题翻译：多处理器节点控制树
公开(公告)号：US20090292900A1
公开(公告)日：2009-11-26
申请号：US12124796
申请日：2008-05-21
申请人： Michael Karo
发明人： Michael Karo
IPC分类号： G06F15/163 , G06F9/00
CPC分类号： G06F15/17
摘要： Control messages are sent from a control processor to a plurality of attached processors via a control tree structure comprising the plurality of attached processors and branching from the control processor, such that two or more of the plurality of attached processor nodes are operable to send messages to other attached processor nodes in parallel.
摘要翻译：控制消息经由包括多个附加处理器的控制树结构从控制处理器发送到多个附属处理器，并且从控制处理器分支，使得多个附加处理器节点中的两个或更多个可操作以将消息发送到其他连接的处理器节点并行。

73. 发明授权

US07577816B2 Remote translation mechanism for a multinode system 有权
标题翻译：多节点系统的远程翻译机制
公开(公告)号：US07577816B2
公开(公告)日：2009-08-18
申请号：US10643758
申请日：2003-08-18
申请人： Kitrick Sheets , Andrew B. Hastings
发明人： Kitrick Sheets , Andrew B. Hastings
IPC分类号： G06F12/08
CPC分类号： G06F12/1036 , G06F12/1072
摘要： The present invention provides a method of initializing shared memory in a multinode system. The method includes building a local address space in each of a plurality of nodes and exporting the local address space from each of the plurality of nodes to a Remote Translation Table (RTT) in each of the plurality of nodes. The present invention further provides system including a plurality of nodes, each node having one or more processors and a memory controller operatively coupled to the one or more processors, wherein the memory controller includes a RTT for holding translation information for an entire virtual memory address space for the node, further wherein the RTT is initialized upon the start of a process by building a local address space in the node, and exporting the local address space from the node to a RTT in each of the plurality of other nodes.
摘要翻译：本发明提供了一种在多节点系统中初始化共享存储器的方法。该方法包括在多个节点的每一个中构建本地地址空间，并将多个节点中的每一个节点的本地地址空间导出到多个节点中的每个节点中的远程转换表（RTT）。本发明还提供了包括多个节点的系统，每个节点具有一个或多个处理器和可操作地耦合到一个或多个处理器的存储器控制器，其中存储器控制器包括用于保持整个虚拟存储器地址空间的翻译信息的RTT 对于所述节点，进一步其中，通过在所述节点中构建本地地址空间，并且在所述多个其他节点中的每一个中将所述本地地址空间从所述节点导出到RTT，在所述进程开始时初始化所述RTT。

74. 发明申请

US20080313621A1 SCALAR CODE REDUCTION USING SHORTEST PATH ROUTING 有权
标题翻译：使用SHORTEST路径路由减少标量代码
公开(公告)号：US20080313621A1
公开(公告)日：2008-12-18
申请号：US11763990
申请日：2007-06-15
申请人： James C. Beyer
发明人： James C. Beyer
IPC分类号： G06F9/45
CPC分类号： G06F8/4441
摘要： This document discusses, among other things, a system and method computing the shortest path expression in a loop having a plurality of expressions. Candidate expressions in the loop are identified and partitioned into sets. A cost matrix is computed as a function of the sets. Paths are found through the cost matrix and, if there are cycles in the paths, the cycles are broken. One or more shortest path expressions are generated as a function of the paths and one or more of the expressions in the loop are replaced with the shortest path expressions.
摘要翻译：该文件尤其涉及一种在具有多个表达式的循环中计算最短路径表达式的系统和方法。循环中的候选表达式被识别并分割成集合。作为集合的函数计算成本矩阵。通过成本矩阵找到路径，如果路径中有循环，则循环被破坏。生成一个或多个最短路径表达式作为路径的函数，并且循环中的一个或多个表达式被最短路径表达式替换。

75. 发明授权

US07421565B1 Method and apparatus for indirectly addressed vector load-add -store across multi-processors 有权
标题翻译：跨多处理器间接寻址矢量加载存储的方法和装置
公开(公告)号：US07421565B1
公开(公告)日：2008-09-02
申请号：US10643727
申请日：2003-08-18
申请人： James R. Kohn
发明人： James R. Kohn
IPC分类号： G06F9/35 , G06F7/02
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/30043 , G06F9/345 , G06F9/3455
摘要： A method and apparatus to correctly compute a vector-gather, vector-operate (e.g., vector add), and vector-scatter sequence, particularly when elements of the vector may be redundantly presented, as with indirectly addressed vector operations. For an add operation, one vector register is loaded with the “add-in” values, and another vector register is loaded with address values of “add to” elements to be gathered from memory into a third vector register. If the vector of address values has a plurality of elements that point to the same memory address, the algorithm should add all the “add in” values from elements corresponding to the elements having the duplicated addresses. An indirectly addressed load performs the “gather” operation to load the “add to” values. A vector add operation then adds corresponding elements from the “add in” vector to the “add to” vector. An indirectly addressed store then performs the “scatter” operation to store the results.
摘要翻译：如同间接寻址的向量操作一样，特别是可以冗余地呈现向量的元素时，正确地计算向量收集，向量操作（例如向量加法）和向量 - 散布序列的方法和装置。对于加法运算，一个向量寄存器加载了“加载项”值，另一个向量寄存器加载了要从存储器收集到第三个向量寄存器的“add to”元素的地址值。如果地址值的向量具有指向相同存储器地址的多个元素，则该算法应该添加与具有重复地址的元素相对应的元素的所有“加入”值。间接寻址的负载执行“收集”操作以加载“添加”值。向量添加操作然后将相应的元素从“添加”向量添加到“添加到”向量中。间接寻址的存储然后执行“分散”操作来存储结果。

76. 发明授权

US07392525B2 Inter-thread long jumps in a multithreaded environment 有权
标题翻译：在多线程环境中进行跨线程跳转
公开(公告)号：US07392525B2
公开(公告)日：2008-06-24
申请号：US10676680
申请日：2003-10-01
申请人： Gail A. Alverson , Charles David Callahan, II , Susan L. Coatney , Brian D. Koblenz , Richard D. Korry , Burton J. Smith
发明人： Gail A. Alverson , Charles David Callahan, II , Susan L. Coatney , Brian D. Koblenz , Richard D. Korry , Burton J. Smith
IPC分类号： G06F9/46 , G06F3/00 , G06F9/44 , G06F13/00
CPC分类号： G06F9/485 , G06F9/461 , G06F9/4812 , G06F9/52 , G06F2209/481
摘要： A method and system that prepares a task for being swapped out from processor utilization that is executing on a computer with multiple processors that each support multiple streams. The task has one or more teams of threads, where each team represents threads executing on a single processor. The task designates, for each stream that is executing a thread, one stream as a team master stream and one stream as a task master stream. For each team master stream, the task notifies the operating system that the team is ready to be swapped out when each other thread of the team has saved its state and has quit its stream. Finally, for the task master stream, the task notifies the operating system that the task is ready to be swapped when it has saved its state and each other team has notified that it is ready to be swapped out.
摘要翻译：一种方法和系统，准备一个从处理器利用率交换的任务，该处理器利用率在每台支持多个流的多个处理器的计算机上执行。该任务具有一个或多个线程团队，每个团队都表示在单个处理器上执行的线程。该任务为执行线程的每个流指定一个流作为团队主流，一个流作为任务主流。对于每个团队主流，任务通知操作系统，当团队的每个其他线程已保存其状态并已退出其流时，该团队已准备好进行交换。最后，对于任务主流，任务通知操作系统当任务准备好被交换时，它已经保存了状态，并且每个其他的团队已经通知它已经准备好被换出了。

77. 发明申请

US20080123679A1 ROUTING TABLE ARCHITECTURE 有权
标题翻译：路由表架构
公开(公告)号：US20080123679A1
公开(公告)日：2008-05-29
申请号：US11932457
申请日：2007-10-31
申请人： Steven L. Scott , Robert Alverson
发明人： Steven L. Scott , Robert Alverson
IPC分类号： H04L12/28
CPC分类号： H04L45/00 , G06F11/0724 , G06F11/0781 , H04L45/40 , H04L45/54 , H04L45/60 , H04L45/742
摘要： A system and method for routing a packet between ports for use in a router having a plurality of ports, including a first and a second port, wherein each port includes a plurality of look-up tables (LUTs) and a look-up table select connected to the LUTs. Routing information is loaded into each of the plurality of LUTs while LUT selection information is loaded in the look-up table select. A packet having a plurality of destination bits is received at the first port and a destination port selected within the router to receive the packet. The destination port is selected by applying two or more of the destination bits to the plurality of LUTs in the first port and selecting an output of the plurality of LUTs as a function of one or more of the destination bits, wherein the selected output indicates the port selected to receive the packet. The packet is then routed to the output of the selected port.
摘要翻译：一种用于在具有包括第一和第二端口的多个端口的路由器中的端口之间路由分组的系统和方法，其中每个端口包括多个查找表（LUT）和查找表选择连接到LUT。路线信息被加载到多个LUT中的每一个中，而LUT选择信息被加载在查找表选择中。在第一端口处接收到具有多个目的地比特的分组，以及在路由器内选择的目的端口来接收分组。通过将两个或多个目的位应用于第一端口中的多个LUT并选择多个LUT的输出作为一个或多个目的地位的函数来选择目的地端口，其中所选择的输出指示选择端口接收数据包。然后将数据包路由到所选端口的输出。

78. 发明申请

US20080016478A1 PARASITIC IMPEDANCE ESTIMATION IN CIRCUIT LAYOUT 审中-公开
标题翻译：电路布局中的PARASITIC阻抗估计
公开(公告)号：US20080016478A1
公开(公告)日：2008-01-17
申请号：US11777094
申请日：2007-07-12
申请人： Robert Lutz , Joel Ficke
发明人： Robert Lutz , Joel Ficke
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： The present invention in one embodiment performs estimation of parasitic impedances in a circuit. Leaf cells of circuit components are evaluated such that their parasitic impedances are estimated, and the leaf cells are placed in a physical layout. Parasitic impedances of interconnect wiring is evaluated, and the interconnect wire routing is placed. Parasitic impedance within the circuit is then estimated using a parasitic reduction process.
摘要翻译：本发明在一个实施例中执行电路中寄生阻抗的估计。对电路元件的叶细胞进行评估，以便估计其寄生阻抗，并将叶细胞置于物理布局中。评估互连布线的寄生阻抗，布置布线。然后使用寄生减少过程来估计电路内的寄生阻抗。

79. 发明申请

US20070283127A1 METHOD AND APPARATUS FOR INDIRECTLY ADDRESSED VECTOR LOAD-ADD-STORE ACROSS MULTI-PROCESSORS 有权
标题翻译：用于通过多处理器的间接寻址矢量加载存储器的方法和装置
公开(公告)号：US20070283127A1
公开(公告)日：2007-12-06
申请号：US11771931
申请日：2007-06-29
申请人： James Kohn
发明人： James Kohn
IPC分类号： G06F9/34
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/30043 , G06F9/345 , G06F9/3455
摘要： A method and apparatus to correctly compute a vector-gather, vector-operate (e.g., vector add), and vector-scatter sequence, particularly when elements of the vector may be redundantly presented, as with indirectly addressed vector operations. For an add operation, one vector register is loaded with the “add-in” values, and another vector register is loaded with address values of “add to” elements to be gathered from memory into a third vector register. If the vector of address values has a plurality of elements that point to the same memory address, the algorithm should add all the “add in” values from elements corresponding to the elements having the duplicated addresses. An indirectly addressed load performs the “gather” operation to load the “add to” values. A vector add operation then adds corresponding elements from the “add in” vector to the “add to” vector. An indirectly addressed store then performs the “scatter” operation to store the results.
摘要翻译：如同间接寻址的向量操作一样，特别是可以冗余地呈现向量的元素时，正确地计算向量收集，向量操作（例如向量加法）和向量 - 散布序列的方法和装置。对于加法运算，一个向量寄存器加载了“加载项”值，另一个向量寄存器加载了要从存储器收集到第三个向量寄存器的“add to”元素的地址值。如果地址值的向量具有指向相同存储器地址的多个元素，则该算法应该添加与具有重复地址的元素相对应的元素的所有“加入”值。间接寻址的负载执行“收集”操作以加载“添加”值。向量添加操作然后将相应的元素从“添加”向量添加到“添加到”向量中。间接寻址的存储然后执行“分散”操作来存储结果。

80. 发明申请

US20070279861A1 Heat-spreading devices for cooling computer systems and associated methods of use 有权
标题翻译：用于冷却计算机系统和相关使用方法的散热装置
公开(公告)号：US20070279861A1
公开(公告)日：2007-12-06
申请号：US11447469
申请日：2006-06-05
申请人： Wade J. Doll
发明人： Wade J. Doll
IPC分类号： H05K7/20
CPC分类号： G06F1/20 , G06F2200/201 , Y10T29/49345
摘要： Cooling systems for use with computer systems are disclosed herein. In one embodiment, a computer system includes a first computer module spaced apart from a second computer module to define a space therebetween. The computer system further includes a cooling system positioned in the space between the first and second computer modules. The cooling system includes a first heat exchanging portion containing a working fluid that absorbs heat from an electronic device mounted to the first computer module. The cooling system further includes a second heat exchanging portion that receives the heated working fluid from the first heat exchanging portion to cool the heated working fluid. A fluid mover is operably coupled to the first and second heat exchanging portions to circulate the working fluid through the first and second heat exchanging portions.
摘要翻译：本文公开了与计算机系统一起使用的冷却系统。在一个实施例中，计算机系统包括与第二计算机模块间隔开以在其间限定空间的第一计算机模块。计算机系统还包括位于第一和第二计算机模块之间的空间中的冷却系统。冷却系统包括第一热交换部分，其包含从安装到第一计算机模块的电子装置吸收热量的工作流体。冷却系统还包括第二热交换部分，其接收来自第一热交换部分的加热的工作流体以冷却加热的工作流体。流体移动器可操作地联接到第一和第二热交换部分以使工作流体循环通过第一和第二热交换部分。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式