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71. 发明授权

US5170445A Document decompressing system 失效
标题翻译：文件解压系统
公开(公告)号：US5170445A
公开(公告)日：1992-12-08
申请号：US455888
申请日：1989-12-21
申请人： John E. Nelson , Gerard J. Papa , Teddy W. Berwin
发明人： John E. Nelson , Gerard J. Papa , Teddy W. Berwin
IPC分类号： H04N1/417
CPC分类号： H04N1/4175
摘要： A code parser decodes coded compressed image information into an intermediate code. A code expander operating asynchronously relative to the code parser decompresses the compressed image information in accordance with such decoded information. A window register in the code parser has a length at least as long as the longest code in the intermediate code. When the intermediate code indicates a pattern in one line in a raster scan of an image corresponding to a pattern in an immediately preceding line, the window register and associated circuitry scan the one line and provide for the decompression in such line in accordance with the decompression at the corresponding positions in the preceding line. Such associated circuitry may include two memories, one for even scan lines and the other for odd scan lines. Alternate ones of the memories are activated for information comparison between adjacent lines during alternate line scans. When the same color is to be printed at a number of successive positions in a line, a counter is set to count such number in the expanded line. During this count, the same color is output. The code parser requests successive codes from an external source and acknowledges the receipt of such successive codes. The code expander receives new codes and expansion instructions from the code parser and acknowledges the receipt of such codes. Under certain circumstances, the code parser may not operate on the next code until the code expander has decompressed the information represented by the previous code.
摘要翻译：代码解析器将编码的压缩图像信息解码为中间代码。相对于代码解析器异步操作的代码扩展器根据这样的解码信息解压缩压缩的图像信息。代码解析器中的窗口寄存器的长度至少与中间代码中最长的代码一样长。当中间代码在与前一行中的图案相对应的图像的光栅扫描中指示一行中的图案时，窗口寄存器和相关联的电路扫描一行并根据解压缩来提供在这样一行中的解压缩在前一行的相应位置。这种相关电路可以包括两个存储器，一个用于偶数扫描线，另一个用于奇数扫描线。在交替行扫描期间，备用的存储器被激活用于相邻行之间的信息比较。当在一行中连续的多个位置上打印相同的颜色时，设置一个计数器对扩展的行中的这个数进行计数。在此计数期间，输出相同的颜色。代码解析器从外部源请求连续代码，并确认接收到这样的连续代码。代码扩展器从代码解析器接收新的代码和扩展指令，并确认收到这样的代码。在某些情况下，代码解析器可能不会对下一个代码进行操作，直到代码扩展器已经解压缩了先前代码所表示的信息。

72. 发明授权

US5099205A Balanced cascode current mirror 失效
标题翻译：平衡共源共栅电流镜
公开(公告)号：US5099205A
公开(公告)日：1992-03-24
申请号：US619399
申请日：1990-11-29
申请人： Lanny L. Lewyn
发明人： Lanny L. Lewyn
IPC分类号： G05F3/26 , H03F1/22 , H03F3/343 , H03F3/345 , H03F3/347
CPC分类号： G05F3/262 , H03F3/3455
摘要： A balanced cascode current mirror includes first and second current paths respectively defined by first and second transistors and by third and fourth transistors. Each current path may include the sources and drains of the transistors in such path. Connections may respectively extend between the gates of the first and third transistors and between the gates of the second and fourth transistors to provide the first and third transistors with substantially identical source, gate, and drain impedances. An input current is introduced to the drain of the second transistor and an output current with substantially identical characteristics is obtained from the drain of the fourth transistor. A capacitance may be connected between the drain of the second transistor and the gate of the first transistor to produce a flow of current at high frequencies through the first current path corresponding to the input current at the drain of the second transistor. A fifth transistor may be connected in a circuit with a constant current source to regulate the current through the first and second transistors to be substantially equal to the input current at low frequencies. The gate of the fifth transistor may be connected to the drain of the second transistor, and the source of the fifth transistor may be connected to the gate of the first transistor, to provide this current regulation. The gates of the second and fourth transistors and the drain of the fifth transistor may have a common reference potential such as ground.

73. 发明授权

US4899103A Current meter 失效
标题翻译：电流表
公开(公告)号：US4899103A
公开(公告)日：1990-02-06
申请号：US74256
申请日：1987-07-16
申请人： Henry S. Katzenstein
发明人： Henry S. Katzenstein
IPC分类号： G01R15/18
CPC分类号： G01R15/185
摘要： A variable electrical current in a first winding on a magnetizable core produces a magnetomotive force in the core. A second core winding produces an opposing magnetomotive force digitally adjustable periodically by a third core winding, a pair of switches and a flip-flop coupled to a center tap for alternately closing such switches when triggered to opposite states. The flip-flop is triggered between opposite states when the third winding current reaches a particular magnitude. In each cycle, the time differences for producing the particular magnitudes and the opposite polarities are dependent upon the remanent core flux. Such time differences are counted digitally upwardly and downwardly for opposite polarities. The second winding current is adjusted digitally in each cycle in a direction to minimize such count. The magnitudes of successive adjustments may be compared periodically by adaptive tracking techniques to control the magnitudes of subsequent adjustments. With large magnitudes of the variable current, the first winding on the core may receive a stepped-down current from a first winding on a second core having a second winding to receive the variable current. Windings on the first and second cores may be connected in a closed loop, or windings on a third core produce in the first core a magnetomotive force aiding the magnetomotive force from the current in the second winding on the second core to compensate for energy losses as a result of such current. The second core may be notched to prevent core becoming saturation.
摘要翻译：可磁化芯上的第一绕组中的可变电流在芯中产生磁动势。第二芯线圈产生由第三芯线圈，一对开关和耦合到中心抽头的触发器周期性数字可调整的相对磁动势，用于当触发到相反状态时交替地闭合这样的开关。当第三绕组电流达到特定幅度时，触发器在相反状态之间触发。在每个周期中，用于产生特定幅度和相反极性的时间差取决于剩余磁芯通量。这样的时间差异以相反的极性数字向上和向下计数。第二绕组电流在每个周期中以一定方向进行数字调整，以使这种计数最小化。可以通过自适应跟踪技术定期比较连续调整的幅度，以控制后续调整的幅度。在具有可变电流的大幅度的情况下，芯上的第一绕组可以接收来自具有第二绕组的第二绕组上的第一绕组的降压电流以接收可变电流。第一和第二芯上的绕组可以连接在闭环中，或者第三芯上的绕组在第一芯中产生磁动势，以促进来自第二绕组中的电流的磁动势，以补偿第二磁芯上的能量损耗这样的结果。第二个核心可能被缺口以防止核心饱和。

74. 发明授权

US4860011A Flash analog-to-digital converter 失效
标题翻译：闪存模数转换器
公开(公告)号：US4860011A
公开(公告)日：1989-08-22
申请号：US923632
申请日：1986-10-27
申请人： Joseph H. Colles
发明人： Joseph H. Colles
IPC分类号： H03M1/00
CPC分类号： H03M1/0648
摘要： First and second reference voltages of different value are introduced to opposite ends of a first line disposed on an IC chip and made from a suitable material (e.g. ion-implanted polysilicon). An input voltage having a value between such reference voltages is provided on a second line on the chip. The second line may be substantially parallel to the first line and made from a suitable material (e.g. polysilicon heavily implanted with ions) to provide an identical voltage at every line position. Bridging layers substantially perpendicularly disposed between the lines at progressive positions on the lines may be made from polysilicon heavily implanted with ions. The magnitudes of the line and reference voltages at each bridging layer are compared in a differential amplifier to produce a signal with a polarity dependent upon such relative magnitudes. The signals from the differential amplifiers are combined in pluralities of logical networks. Each network includes two series transistors, one receiving the signal from one comparator with a relatively low reference voltage to produce a signal with a first logic level and the other receiving the signal from another comparator with an increased reference voltage to produce a signal with a second logic level. Each network has a binary significance dependent upon the relative values of the binary signals introduced to the transistors in the network. The networks of each binary significance are connected to a binary bit line of corresponding binary significance to produce on such line a signal representing the input voltage.
摘要翻译：将不同值的第一和第二参考电压引入设置在IC芯片上并由合适材料（例如离子注入的多晶硅）制成的第一线的相对端。在芯片上的第二条线上提供具有这种参考电压之间的值的输入电压。第二线可以基本上平行于第一条线并由合适的材料（例如，多重注入离子的多晶硅）制成，以在每个线位置提供相同的电压。基本上垂直地设置在线路上的行进位置处的线之间的桥接层可以由重离子注入离子的多晶硅制成。在差分放大器中比较每个桥接层的线路和参考电压的大小，以产生具有取决于这种相对幅度的极性的信号。来自差分放大器的信号被组合在多个逻辑网络中。每个网络包括两个串联晶体管，一个接收来自一个比较器的信号具有相对较低的参考电压，以产生具有第一逻辑电平的信号，另一个接收来自具有增加的参考电压的另一个比较器的信号，以产生具有第二逻辑电平的信号逻辑电平。每个网络具有取决于引入到网络中的晶体管的二进制信号的相对值的二进制重要性。每个二进制有效性的网络连接到具有相应二进制重要性的二进制位线，以在该行上产生表示输入电压的信号。

75. 发明授权

US4847621A Apparatus for converting data between digital and analog values 失效
标题翻译：用于在数字和模拟值之间转换数据的装置
公开(公告)号：US4847621A
公开(公告)日：1989-07-11
申请号：US026539
申请日：1987-03-13
申请人： Joseph H. Colles
发明人： Joseph H. Colles
IPC分类号： H03M1/00
CPC分类号： H03M1/74
摘要： A converter converts to an analog value a plurality of digital signals each having characteristics representing an individual digital value. A plurality of switches are disposed in sets with the switches in each set being responsive to an individual one of the digital signals. The number of switches in each set is related to the digital significance of the set, preferably on an inverse basis. The switches are connected in a repetitive array to output members and a line to provide for the connection for progressive ones of the members to the output line in accordance with the pattern of the switches in the conductive and non-conductive states in representation of progressive increases in the digital value. The repetitive also provides, with such progressive increases in the digital values, output members previously connected to the line. The repetitive array may be responsive to the digital signals in a single delay time. The output members progressively connected to the line preferably have a linear disposition. A current flows through each of such output members to indicate the analog value on a cumulative basis. In the converter, each of the ouput members may be connected to an individual one of the switches in the sub-set of least digital significance, alternate ones of the remaining output members may be connected to the control switches in the sub-set of next remaining digital significance; and the other output members may be connected to the switches in the sub-sets of progressive digital significance in a corresponding pattern.
摘要翻译： A转换器将模拟值转换成具有表示各个数字值的特征的多个数字信号。多个开关以组合的形式设置，每组中的开关响应于数字信号中的单独一个。每组中的开关数目与集合的数字有意义有关，优选地是反向的。开关以重复的阵列连接到输出构件和线，以根据导电和非导电状态中的开关的图案提供到输出线的渐进的连接，以表示逐渐增加在数字价值。重复性还提供了数字值的逐渐增加，以前连接到线路的输出成员。重复阵列可以在单个延迟时间内响应数字信号。逐渐连接到线路的输出构件优选地具有线性配置。电流流过每个这样的输出构件以在累积的基础上指示模拟值。在转换器中，每个输出构件可以以至少数字有意义的子组连接到开关中的单独一个，其余输出构件中的另一个可以连接到下一个子组中的控制开关剩下的数字意义并且其它输出构件可以以相应图案以逐行数字有意义的子集连接到开关。

76. 发明授权

US4831282A CMOS input circuit 失效
标题翻译： CMOS输入电路
公开(公告)号：US4831282A
公开(公告)日：1989-05-16
申请号：US104690
申请日：1987-10-05
申请人： Joseph H. Colles
发明人： Joseph H. Colles
IPC分类号： H03K17/041 , H03M1/68 , H03M1/74
CPC分类号： H03M1/685 , H03K17/04106 , H03M1/747
摘要： A digital value represented by first and second pluralities of signals is converted into an analog value represented by an analog signal. The converter and the associated circuitry described above are preferably disposed on an integrated circuit chip formed from MOS transistors. Circuitry provides output currents of optimal waveforms from the digital-to-analog converters for driving stages subsequent to such converters. The circuits of this invention are advantageous because they operate satisfactorily at frequencies in excess of eighty-five megahertz (85 mhz). The circuits facilitate the production of the signals at such high frequencies by employing the distributed capacitances in a first transistor to expedite the response of a second transistor to binary input signals introduced to the first transistor. A servo system is also provided for controlling the magnitude of a biasing voltage introduced to the second transistor and for maintaining substantially constant the currents flowing at all times through one or the other of the first and second transistors.
摘要翻译：由第一和第二多个信号表示的数字值被转换成由模拟信号表示的模拟值。上述转换器和相关电路优选地设置在由MOS晶体管形成的集成电路芯片上。电路提供来自数模转换器的最佳波形的输出电流，用于这些转换器之后的驱动级。本发明的电路是有利的，因为它们在超过八十五兆赫（85mhz）的频率下令人满意地工作。这些电路通过采用第一晶体管中的分布电容来促进在这样的高频率下的信号的产生，以加速第二晶体管对引入到第一晶体管的二进制输入信号的响应。还提供一种伺服系统，用于控制引入到第二晶体管的偏置电压的大小，并且用于保持始终流过第一和第二晶体管中的一个或另一个的电流基本恒定。

77. 发明授权

US4814688A Reference generator 失效
标题翻译：参考发生器
公开(公告)号：US4814688A
公开(公告)日：1989-03-21
申请号：US163646
申请日：1988-03-03
申请人： Joseph H. Colles
发明人： Joseph H. Colles
IPC分类号： H03M1/74 , G05F1/575 , G09G1/00 , G09G1/28 , H03M1/00 , G05F3/16
CPC分类号： G05F1/575
摘要： A reference generator is used in a digital-to-analog converter to provide for a replication of colors in accordance with binary information introduced to the converter. The generator is responsive to binary signals each having first and second logic levels respectively representing binary "1" and binary "0" and each representing a different one of the binary colors red, green and blue. Each of the binary signals is introduced to an individual one of transistors in a first plurality. An energizing voltage is also introduced to the transistors to obtain a flow of current through such transistors in accordance with the logic levels of such input signals and the magnitude of the energizing voltage. A substantially constant current is provided at first particular times and a reference voltage is provided at other times. An impedance may be common to the circuit for the substantially constant current and the reference voltage. A first control is responsive to the constant current to maintain the energizing voltage at a substantially constant value. A second control is responsive to the reference voltage to maintain the energizing voltage at the substantially constant value. When the reference voltage is produced, the production of the substantially constant voltage from the constant current is overridden. The first and second controls for each of the different colors are disposed in an electrical circuit to provide an output from the circuit only in accordance with the logic levels of the binary signals. The first and second controls may respectively include transistors in second and third pluralities.

78. 发明授权

US4813023A System employing negative feedback for decreasing the response time of a cell 失效
标题翻译：采用负反馈的系统来减小单元的响应时间
公开(公告)号：US4813023A
公开(公告)日：1989-03-14
申请号：US921530
申请日：1986-10-21
申请人： Michael J. Brunolli
发明人： Michael J. Brunolli
IPC分类号： G11C11/413 , G11C7/06 , G11C11/417 , G11C7/00
CPC分类号： G11C7/062
摘要： First and second lines respectively receive first and second complementary input signals representing a binary bit. Each of the input signals has first and second logic levels respectively corresponding to a binary "1" and a binary "0". The input signals produce a current through a load in accordance with the relative logic levels of the first and second input signals. The difference between the logic levels of the input signals is amplified and introduced as a negative feedback to a particular one of the first and second lines in accordance with the relative logic levels of the signals on the lines. The feedback causes a current to be produced in the load with a polarity opposite to the polarity of the current produced in the load by the input signals and with a magnitude less than the magnitude of the current produced in the load by the input signals. The negative feedback is effective in minimizing the time for the load to respond to changes in the relative logic levels of the first and second input signals. In this way, the frequency of response of a system including the circuitry of this invention can be significantly increased. The embodiment described above may be used in a system in which first particular input signals are provided to identify a selected word and second particular input signals are provided to identify a bit in the word one and in which a cell (a load) is selected common to the selected word and the selected bit. The circuitry described above may be included to minimize the time for producing in the load a signal representative of the selective of such cell.
摘要翻译：第一和第二行分别接收表示二进制位的第一和第二互补输入信号。每个输入信号具有分别对应于二进制“1”和二进制“0”的第一和第二逻辑电平。输入信号根据第一和第二输入信号的相对逻辑电平产生通过负载的电流。根据线路上的信号的相对逻辑电平，输入信号的逻辑电平之间的差被放大并作为负反馈引入到第一和第二行中的特定一个。该反馈使得在负载中产生与负载中产生的电流的极性相反的负载的电流，并且其输入信号的幅度小于输入信号在负载中产生的电流的大小。负反馈有效地最小化负载响应第一和第二输入信号的相对逻辑电平的变化的时间。以这种方式，可以显着增加包括本发明的电路的系统的响应频率。上述实施例可以用于其中提供第一特定输入信号以识别所选择的字的系统，并且提供第二特定输入信号以识别单词1中的位，并且其中选择单元（负载）是公共的到所选择的字和所选位。可以包括上述电路以最小化在负载中产生表示这种电池的选择性的信号的时间。

79. 发明授权

US4794282A TTL to CMOS voltage level translator 失效
标题翻译： TTL到CMOS电压电平转换器
公开(公告)号：US4794282A
公开(公告)日：1988-12-27
申请号：US106179
申请日：1987-10-07
申请人： Joseph H. Colles
发明人： Joseph H. Colles
IPC分类号： H03K17/041 , H03K19/0185 , H03M1/68 , H03M1/74 , H03K19/092 , H03K17/687 , H03L5/00
CPC分类号： H03K19/018521 , H03K17/04106 , H03M1/685 , H03M1/747
摘要： A digital value represented by first and second pluralities of signals is converted into an analog value represented by an analog signal. The converter and the associated circuitry described above are preferably disposed on an integrated circuit chip formed from C-MOS transistors. Circuitry is also provided for converting signal levels from TTL logic devices external to the chip into signals for operating the C-MOS transistors on the chip by adjusting the voltages from the TTL logic devices into voltages optimal for operating the C-MOS transistors. The circuits of this invention are advantageous because they operate satisfactorily at frequencies in excess of eighty-five megahertz (85 mhz).
摘要翻译：由第一和第二多个信号表示的数字值被转换成由模拟信号表示的模拟值。上述转换器和相关电路优选地设置在由C-MOS晶体管形成的集成电路芯片上。还提供电路，用于将来自芯片外部的TTL逻辑器件的信号电平转换为通过将TTL逻辑器件的电压调整为用于操作C-MOS晶体管的最佳电压来操作芯片上的C-MOS晶体管的信号。本发明的电路是有利的，因为它们在超过八十五兆赫（85mhz）的频率下令人满意地工作。

80. 发明授权

US4658240A Apparatus for converting data between analog and digital values 失效
标题翻译：用于在模拟和数字值之间转换数据的装置
公开(公告)号：US4658240A
公开(公告)日：1987-04-14
申请号：US607736
申请日：1984-05-07
申请人： James A. Bixby
发明人： James A. Bixby
IPC分类号： H03M1/00 , H03K13/02
CPC分类号： H03M1/148
摘要： Signals representing individual digital values are introduced to pluralities of switches of corresponding digital significance to provide for the conductivity of an individual one of the switches in each pair in accordance with the digital value represented by such signals. A plurality of conductive output members to provide paths through a matrix relationship of the switches and through the output members to one of two output lines. This matrix provides for progressive increases in the number of the output members connected to a particular one of the output lines with progressive increases in the digital value and for a continued connection to the particular output line of output members previously connected to the particular output line with such progressive increases in the digital value. The cumulative current through the particular output line is indicative of the analog value. The output members are disposed on an integrated circuit chip in groups each having a common centroid arrangement to offset correlated errors in the output members in the group. The members in each group may be disposed in pairs relative to the common centroid to provide offsets in the correlated errors in the output members in each pair. The output members in the groups having intermediate digital values in the range of digital values may be disposed relative to the common centroid in positions providing minimum correlation errors. Coincidentally, the output members in groups having extreme digital values in the range of digital values may be disposed relative to the common centroid in positions providing increased correlation errors.
摘要翻译：将表示各个数字值的信号引入到相应数字有意义的多个开关中，以根据由这些信号表示的数字值来提供每对中的每个开关中的每个开关的导电性。多个导电输出构件，用于提供穿过开关的矩阵关系并通过输出构件到两条输出线之一的路径。该矩阵提供连续到输出线路中的特定输出线路的输出部件的数量的逐渐增加，数字值逐渐增加，并且连续连接到先前连接到特定输出线路上的输出部件的特定输出线路，这种逐渐增加的数字价值。通过特定输出线的累积电流表示模拟值。输出构件以分组的方式设置在集成电路芯片上，每一组具有共同的质心布置以抵消组中的输出构件中的相关误差。每个组中的成员可以相对于公共质心成对配置，以在每对中的输出成员中的相关误差中提供偏移。可以在提供最小相关误差的位置中相对于公共质心布置具有数字值范围内的中间数字值的组中的输出构件。巧合的是，在数字值范围内具有极端数字值的组中的输出构件可以相对于提供增加的相关误差的位置中的公共质心来布置。

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