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71. 发明申请

US20080273028A1 UNIVERSAL RASTERIZATION OF GRAPHIC PRIMITIVES 有权
标题翻译：图形主义的通用移植
公开(公告)号：US20080273028A1
公开(公告)日：2008-11-06
申请号：US11742753
申请日：2007-05-01
申请人： Guofang Jiao , William Torzewski , Chun Yu , Brian Ruttenberg
发明人： Guofang Jiao , William Torzewski , Chun Yu , Brian Ruttenberg
IPC分类号： G06T17/10
CPC分类号： G06T11/40 , G06T15/30 , G06T2210/12
摘要： A technique for universally rasterizing graphic primitives used in computer graphics is described. Configurations of the technique include determining three edges and a bounded region in a retrofitting bounding box. Each primitive has real and intrinsic edges. The process uses no more than three real edges of any one graphic primitive. In the case of a line, a third edge is set coincident with one of its two real edges. The area between the two real edges is enclosed by opposing perimeter edges of the bounding box. In the case of a rectangle, only three real edges are used. The fourth edge corresponds to a bounding edge provided by the retrofitting bounding box. In exemplary applications, the technique may be used in mobile video-enabled devices, such as cellular phones, video game consoles, PDAs, laptop computers, video-enabled MP3 players, and the like.
摘要翻译：描述了用于计算机图形中使用的用于普遍光栅化图形原语的技术。该技术的配置包括确定三个边缘和改进边界框中的有界区域。每个原语具有真实和内在的边缘。该过程使用任何一个图形图元的不超过三个实际边缘。在线的情况下，第三边缘被设置成与其两个实际边缘中的一个一致。两个实际边缘之间的区域由边界框的相对的周边边缘包围。在矩形的情况下，仅使用三个实际边。第四边缘对应于由改装边界框提供的边界边缘。在示例性应用中，该技术可以用于移动视频使能设备，例如蜂窝电话，视频游戏机，PDA，膝上型计算机，支持视频的MP3播放器等。

72. 发明授权

US08643644B2 Multi-stage tessellation for graphics rendering 有权
标题翻译：图形渲染的多阶段镶嵌
公开(公告)号：US08643644B2
公开(公告)日：2014-02-04
申请号：US12052628
申请日：2008-03-20
申请人： Jian Wei , Guofang Jiao , Ning Bi , Chehui Wu
发明人： Jian Wei , Guofang Jiao , Ning Bi , Chehui Wu
IPC分类号： G06T15/30 , G06T17/20
CPC分类号： G06T11/203
摘要： This disclosure describes a multi-stage tessellation technique for tessellating a curve during graphics rendering. In particular, a first tessellation stage tessellates the curve into a first set of line segments that each represents a portion of the curve. A second tessellation stage further tessellates the portion of the curve represented by each of the line segments of the first set into additional line segments that more finely represent the shape of the curve. In this manner, each portion of the curve that was represented by only one line segment after the first tessellation stage is represented by more than one line segment after the second tessellation stage. In some instances, more than two tessellation stages may be performed to tessellate the curve.
摘要翻译：本公开描述了用于在图形渲染期间细分曲线的多阶段镶嵌技术。特别地，第一细分阶段将曲线细分为第一组线段，每组线段表示曲线的一部分。第二细分阶段进一步将由第一组的每个线段表示的曲线的部分细分为更精细地表示曲线形状的附加线段。以这种方式，在第一细分阶段之后仅由一个线段表示的曲线的每个部分在第二细分阶段之后被多于一个线段表示。在一些情况下，可以执行多于两个的细分阶段来细分曲线。

73. 发明授权

US08495602B2 Shader compile system and method 有权
标题翻译：着色器编译系统和方法
公开(公告)号：US08495602B2
公开(公告)日：2013-07-23
申请号：US11864563
申请日：2007-09-28
申请人： Lin Chen , Guofang Jiao , Chihong Zhang , Junhong Sun
发明人： Lin Chen , Guofang Jiao , Chihong Zhang , Junhong Sun
IPC分类号： G06F9/45
CPC分类号： G06T15/50 , G06F8/41
摘要： The present disclosure includes a shader compiler system and method. In an embodiment, a shader compiler includes a decoder to translate an instruction having a vector representation to a unified instruction representation. The shader compiler also includes an encoder to translate an instruction having a unified instruction representation to a processor executable instruction.
摘要翻译：本公开包括着色器编译器系统和方法。在一个实施例中，着色器编译器包括将具有向量表示的指令转换为统一指令表示的解码器。着色器编译器还包括将具有统一指令表示的指令转换为处理器可执行指令的编码器。

74. 发明申请

US20090085919A1 SYSTEM AND METHOD OF MAPPING SHADER VARIABLES INTO PHYSICAL REGISTERS 有权
标题翻译：将SHADER变量映射到物理寄存器的系统和方法
公开(公告)号：US20090085919A1
公开(公告)日：2009-04-02
申请号：US11864484
申请日：2007-09-28
申请人： Lin Chen , Junhong Sun , Guofang Jiao , Chihong Zhang , Lingjun Chen
发明人： Lin Chen , Junhong Sun , Guofang Jiao , Chihong Zhang , Lingjun Chen
IPC分类号： G06F13/14 , G09G5/36
CPC分类号： G06T15/005 , G06F8/441
摘要： The present disclosure includes system and method of mapping shader variables into physical registers. In an embodiment, a graphics processing unit (GPU) and a memory coupled to the GPU are disclosed. The memory includes a processor readable data file that has a register file portion. The register file portion has a rectangular structure including a plurality of data items. At least two of the plurality of data items corresponding to data elements of a shader program. The data elements have different data storage types.
摘要翻译：本公开包括将着色器变量映射到物理寄存器的系统和方法。在一个实施例中，公开了一种图形处理单元（GPU）和耦合到GPU的存储器。存储器包括具有寄存器文件部分的处理器可读数据文件。寄存器文件部分具有包括多个数据项的矩形结构。与着色器程序的数据元素对应的多个数据项中的至少两个。数据元素具有不同的数据存储类型。

75. 发明授权

US07652677B2 Graphics system employing pixel mask 有权
标题翻译：采用像素掩码的图形系统
公开(公告)号：US07652677B2
公开(公告)日：2010-01-26
申请号：US11499200
申请日：2006-08-03
申请人： Angus M. Dorbie , Guofang Jiao
发明人： Angus M. Dorbie , Guofang Jiao
IPC分类号： G09G5/00
CPC分类号： G06T11/40
摘要： The system includes a bounds primitive rasterizer that rasterizes a bounds primitive into a selection of primitive pixels. The selection of primitive pixels bounds a shape to be rendered to a screen. The system also includes a pixel mask generator that generates a pixel mask for the shape. The pixel mask includes mask pixels that each corresponds to one of the primitive pixels. A mask pixel is a covered pixel when the shape covers at least a threshold portion of the mask pixel and is an uncovered pixel when the shape does not cover the mask pixel. The system also includes a pixel screener configured to retain primitive pixels that correspond to covered mask pixels and to discard primitive pixels that correspond to uncovered mask pixels.
摘要翻译：该系统包括边界原始光栅化器，其将边界原语光栅化为原始像素的选择。原始像素的选择限制要呈现到屏幕的形状。该系统还包括产生形状的像素掩模的像素掩码生成器。像素掩模包括每个对应于原始像素之一的掩模像素。当形状覆盖掩模像素的至少阈值部分时，掩模像素是被覆盖的像素，并且当形状不覆盖掩模像素时，掩模像素是未覆盖的像素。该系统还包括被配置为保留对应于被覆盖的掩模像素的原始像素并且丢弃对应于未覆盖的掩码像素的原始像素的像素筛选器。

76. 发明申请

US20060209065A1 Method and apparatus for occlusion culling of graphic objects 审中-公开
标题翻译：图形对象遮挡剔除的方法和装置
公开(公告)号：US20060209065A1
公开(公告)日：2006-09-21
申请号：US11298167
申请日：2005-12-08
申请人： Eugene Lapidous , Jianbo Zhang , Guofang Jiao , Bozhan Chen , Ji Zhou
发明人： Eugene Lapidous , Jianbo Zhang , Guofang Jiao , Bozhan Chen , Ji Zhou
IPC分类号： G06T15/40
CPC分类号： G06T15/40
摘要： A method of occlusion culling of graphic objects, comprising the steps of storing a first mask and one or more depth values associated with areas inside and outside the mask for a pre-defined region, and evaluating the visibility of the primitive covering the same region, wherein visibility evaluation begins after the computation of the coverage mask of the primitive in the region, and the computation of one or more depth values representing the pixels of the primitive. The method of the present invention is a real-time method of generating per-region coverage mask and associated Z values after the second primitive is rendered in the same region, which can maximize the bandwidth savings for Z read for both overlapping and non-overlapping primitives, with different relations between their depth values.
摘要翻译：一种图形对象的遮挡剔除方法，包括以下步骤：存储第一掩码和与掩模内部和外部的区域相关联的一个或多个深度值用于预定义区域，以及评估覆盖相同区域的图元的可视性，其中在计算区域中的原语的覆盖掩码之后开始可视性评估，以及计算表示图元的像素的一个或多个深度值。本发明的方法是在将第二原语呈现在相同区域中之后生成每区域覆盖掩码和相关联的Z值的实时方法，这可以使重叠和非重叠的Z读取的带宽节省最大化原始图像，其深度值之间具有不同的关系。

77. 发明申请

US20120262493A1 PIXEL VALUE COMPACTION FOR GRAPHICS PROCESSING 有权
标题翻译：用于图形处理的像素值压缩
公开(公告)号：US20120262493A1
公开(公告)日：2012-10-18
申请号：US13085855
申请日：2011-04-13
申请人： Ming-Chang Tsai , Guofang Jiao
发明人： Ming-Chang Tsai , Guofang Jiao
IPC分类号： G06F13/14 , G06T3/40
CPC分类号： G06T15/005 , G06F2213/0038 , G06T1/20
摘要： In general, aspects of this disclosure describe example techniques for efficient usage of the fixed data rate processing of a graphics processing unit (GPU) for a variable data rate processing. For example, the GPU may be coupled to a pixel value processing unit that receives pixel values for pixels in an image processed by the GPU. The pixel value processing unit may determine whether the pixel values are for pixels that require further processing, and store the pixel values for the pixels that are required for further processing in a buffer.
摘要翻译：通常，本公开的方面描述了用于有效使用用于可变数据速率处理的图形处理单元（GPU）的固定数据速率处理的示例技术。例如，GPU可以耦合到像素值处理单元，其接收由GPU处理的图像中的像素的像素值。像素值处理单元可以确定像素值是否用于需要进一步处理的像素，并且将用于进一步处理所需的像素的像素值存储在缓冲器中。

78. 发明授权

US08269792B2 Efficient scissoring for graphics application 有权
标题翻译：图形应用程序的高效剪裁
公开(公告)号：US08269792B2
公开(公告)日：2012-09-18
申请号：US11562379
申请日：2006-11-21
申请人： Guofang Jiao , Angus M. Dorbie
发明人： Guofang Jiao , Angus M. Dorbie
IPC分类号： G06T11/00
CPC分类号： G06T15/30 , G06T2200/28
摘要： Scissoring for any number of scissoring regions is performed in a sequential order by drawing one scissoring region at a time on a drawing surface and updating scissor values for pixels within each scissoring region. A scissor value for a pixel may indicate the number of scissoring regions covering the pixel and may be incremented for each scissoring region covering the pixel. A scissor value for a pixel may also be a bitmap, and a bit for a scissoring region may be set to one if the pixel is within the scissoring region. Pixels within a region of interest are passed and rendered, and pixels outside of the region are discarded. This region may be defined by a reference value, which may be set to (a) one for the union of all scissoring regions, for a scissoring UNION operation, or (b) larger than one for the intersection of multiple (e.g., all) scissoring regions, for a scissoring AND operation.
摘要翻译：通过在绘图面上一次绘制一个剪切区域并且更新每个剪切区域内的像素的剪刀值，以顺序的顺序执行任意数量的剪切区域的剪切。像素的剪刀值可以指示覆盖像素的剪切区域的数量，并且可以针对覆盖像素的每个剪切区域增加剪裁值。像素的剪刀值也可以是位图，并且如果像素在剪切区域内，则可以将剪切区域的位设置为1。传递和渲染感兴趣区域内的像素，并且丢弃该区域外的像素。该区域可以由参考值定义，其可以被设置为（a）用于所有剪切区域的联合，用于剪切UNION操作，或者（b）对于多个（例如，全部）的交点大于一个，剪切区域，用于剪切和操作。

79. 发明申请

US20070139421A1 Methods and systems for performance monitoring in a graphics processing unit 审中-公开
标题翻译：用于图形处理单元中性能监控的方法和系统
公开(公告)号：US20070139421A1
公开(公告)日：2007-06-21
申请号：US11314184
申请日：2005-12-21
申请人： Wen Chen , John Brothers , Guofang Jiao
发明人： Wen Chen , John Brothers , Guofang Jiao
IPC分类号： G06T1/00
CPC分类号： G06T1/20
摘要： Provided is a system for monitoring the performance in a computer graphics processor having a plurality of pipeline processing blocks in a graphics pipeline. The system includes: performance monitoring logic, configured to gather data corresponding to graphics pipeline performance; a plurality of counting logic blocks, located within the performance monitoring logic; a plurality of logical counters, located in each of the plurality of pipeline processing blocks, configured to transmit a plurality of count signals to the performance monitoring logic; a plurality of counter configuration registers, configured to map a portion of the plurality of logical counters to the plurality of counting logic blocks; and a command processor configured to provide a plurality of commands to the performance monitoring logic.
摘要翻译：提供了一种用于在图形管线中监视具有多个流水线处理块的计算机图形处理器中的性能的系统。该系统包括：性能监控逻辑，配置为收集对应于图形流水线性能的数据; 多个计数逻辑块，位于性能监视逻辑内; 多个逻辑计数器，位于多个流水线处理块中的每一个中，被配置为将多个计数信号发送到性能监视逻辑; 多个计数器配置寄存器，被配置为将所述多个逻辑计数器的一部分映射到所述多个计数逻辑块; 以及命令处理器，被配置为向所述性能监视逻辑提供多个命令。

80. 发明授权

US08832417B2 Program flow control for multiple divergent SIMD threads using a minimum resume counter 有权
标题翻译：使用最小恢复计数器对多个发散SIMD线程进行程序流控制
公开(公告)号：US08832417B2
公开(公告)日：2014-09-09
申请号：US13227274
申请日：2011-09-07
申请人： Lin Chen , David Rigel Garcia Garcia , Andrew E. Gruber , Guofang Jiao
发明人： Lin Chen , David Rigel Garcia Garcia , Andrew E. Gruber , Guofang Jiao
IPC分类号： G06F9/38
CPC分类号： G06F9/3887 , G06F9/322 , G06F9/3851
摘要： This disclosure describes techniques for handling divergent thread conditions in a multi-threaded processing system. In some examples, a control flow unit may obtain a control flow instruction identified by a program counter value stored in a program counter register. The control flow instruction may include a target value indicative of a target program counter value for the control flow instruction. The control flow unit may select one of the target program counter value and a minimum resume counter value as a value to load into the program counter register. The minimum resume counter value may be indicative of a smallest resume counter value from a set of one or more resume counter values associated with one or more inactive threads. Each of the one or more resume counter values may be indicative of a program counter value at which a respective inactive thread should be activated.
摘要翻译：本公开描述了用于处理多线程处理系统中的发散线程状况的技术。在一些示例中，控制流程单元可以获得由存储在程序计数器寄存器中的程序计数器值所标识的控制流程指令。控制流程指令可以包括指示控制流程指令的目标程序计数器值的目标值。控制流程单元可以选择目标程序计数器值和最小恢复计数器值之一作为加载到程序计数器寄存器中的值。最小恢复计数器值可以指示与一个或多个非活动线程相关联的一个或多个恢复计数器值的集合中的最小恢复计数器值。一个或多个恢复计数器值中的每一个可以指示应该激活相应的非活动线程的程序计数器值。

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