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71. 发明授权

US07675733B2 Multilayer capacitor 有权
标题翻译：多层电容器
公开(公告)号：US07675733B2
公开(公告)日：2010-03-09
申请号：US12237837
申请日：2008-09-25
申请人： Byoung Hwa Lee , Sung Kwon Wi , Sang Soo Park , Min Cheol Park , Dong Seok Park , Hae Suk Chung
发明人： Byoung Hwa Lee , Sung Kwon Wi , Sang Soo Park , Min Cheol Park , Dong Seok Park , Hae Suk Chung
IPC分类号： H01G4/228
CPC分类号： H01G4/232 , H01G4/012 , H01G4/30
摘要： There is provided a multilayer capacitor including an inner connecting conductor of at least one polarity; a plurality of first and second outer electrodes formed on a surface of the body, wherein the inner connecting conductor is connected to a corresponding one of the outer electrodes having identical polarity, a corresponding one of the inner electrodes having identical polarity to the inner connecting conductor includes a plurality of groups each including at least one of the inner electrodes, wherein the inner electrodes of the respective groups are connected to the outer electrodes having identical polarity that are different from one another for each of the groups and electrically connected to the inner connecting conductor through the connected outer electrode.
摘要翻译：提供一种包括至少一个极性的内连接导体的多层电容器; 形成在所述主体的表面上的多个第一和第二外部电极，其中所述内部连接导体连接到具有相同极性的对应的一个外部电极，相应的一个所述内部电极具有与所述内部连接导体包括多个组，每个组包括至少一个内部电极，其中各组的内部电极连接到具有与每个组相互不同的极性相同的外部电极，并且电连接到内部连接导体通过连接的外部电极。

72. 发明申请

US20090279228A1 MULTILAYER CHIP CAPACITOR 有权
标题翻译：多层芯片电容器
公开(公告)号：US20090279228A1
公开(公告)日：2009-11-12
申请号：US12267112
申请日：2008-11-07
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/30
CPC分类号： H01G4/30 , H01G4/012 , H01G4/232
摘要： A multilayer chip capacitor includes a capacitor body provided by a stack of a plurality of dielectric layers, a plurality of internal electrodes disposed in the capacitor body such that the internal electrodes of opposite polarities are alternately disposed to face each other with the dielectric layer interposed between each facing set of the internal electrodes, and a plurality of external electrodes disposed on an outer face of the capacitor body and electrically connected with the internal electrode. Each of the plurality of internal electrodes includes a main electrode part, and at least one lead extending from the main electrode part to a side face of the capacitor body and connected to a corresponding one of the external electrodes. The lead extends to the corresponding external electrode to be inclined with respect to the main electrode part thereof.
摘要翻译：多层片状电容器包括：由多个电介质层的堆叠体构成的电容器主体，设置在电容器主体中的多个内部电极，使得相互极性的内部电极交替地配置成彼此面对，其中介电层介于每个面对的内部电极组，以及多个外部电极，设置在电容器主体的外表面上并与内部电极电连接。多个内部电极中的每一个包括主电极部分和从电极主体的主电极部分延伸到侧面的至少一个引线，并连接到对应的一个外部电极。引线延伸到对应的外部电极，以相对于其主电极部分倾斜。

73. 发明授权

US07599166B2 Multilayer chip capacitor 有权
标题翻译：多层片式电容器
公开(公告)号：US07599166B2
公开(公告)日：2009-10-06
申请号：US11598672
申请日：2006-11-14
申请人： Byoung Hwa Lee , Hae Suk Chung , Dong Seok Park , Min Cheol Park , Sang Soo Park , Sung Kwon Wi
发明人： Byoung Hwa Lee , Hae Suk Chung , Dong Seok Park , Min Cheol Park , Sang Soo Park , Sung Kwon Wi
IPC分类号： H01G4/00 , H01G4/005
CPC分类号： H01G4/30 , H01G4/012 , H01G4/232
摘要： A multilayer chip capacitor includes a capacitor body having dielectric layers, and internal electrode layers separated from each other in the capacitor body by the dielectric layers. Each internal electrode layer has one or two leads and includes at least one coplanar electrode plate. External electrodes are electrically connected to the internal electrode layers via the leads. The internal electrode layers constitute a plurality of blocks stacked repeatedly. Each block includes a plurality of the internal electrode layers stacked successively. The leads extending to a face of the capacitor body are arranged in a zigzag shape along a stacking direction. The leads of vertically adjacent ones of the electrode plates having opposite polarities are arranged to be horizontally adjacent to each other.
摘要翻译：多层片状电容器包括具有电介质层的电容器主体，以及通过电介质层在电容器主体中彼此分离的内部电极层。每个内部电极层具有一个或两个引线并且包括至少一个共面电极板。外部电极通过引线电连接到内部电极层。内部电极层构成反复堆叠的多个块。每个块包括依次层叠的多个内部电极层。延伸到电容器主体的表面的引线沿堆叠方向布置成Z字形。具有相反极性的垂直相邻电极板的引线被布置成水平相邻。

74. 发明授权

US07595973B1 Multilayer chip capacitor and circuit board apparatus having the capacitor 有权
标题翻译：具有电容器的多层片状电容器和电路板装置
公开(公告)号：US07595973B1
公开(公告)日：2009-09-29
申请号：US12262909
申请日：2008-10-31
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/228
CPC分类号： H01G4/232 , H01G4/005 , H01G4/30 , H05K1/0231 , H05K1/113 , H05K2201/10636 , Y02P70/611
摘要： There is provided a multilayer chip capacitor including: a capacitor body including first and second capacitor units disposed in a laminated direction; first to fourth outer electrodes formed on side surfaces of the capacitor body, respectively; and at least one connecting conductor line connecting the first and third outer electrodes having identical polarity to each other and the second and fourth outer electrodes having identical polarity to each other, wherein the first capacitor body includes first and second inner electrodes, the second capacitor unit includes a plurality of third and fourth inner electrodes, the first to fourth outer electrodes are connected to the first to fourth inner electrodes, respectively, and an equivalent series resistance (R1) of the first capacitor unit and a combined equivalent series resistance (R2′) of the second capacitor and the connecting conductor line satisfy the Equation 0.7(R1)≦R2′≦1.3(R1).
摘要翻译：提供了一种多层片状电容器，包括：电容器主体，包括沿层叠方向设置的第一和第二电容器单元; 分别形成在电容器主体的侧表面上的第一至第四外部电极; 以及连接第一和第三外部电极的至少一个连接导线，彼此具有相同的极性，第二和第四外部电极彼此具有相同的极性，其中第一电容器主体包括第一和第二内部电极，第二电容器单元包括多个第三和第四内部电极，第一至第四外部电极分别连接到第一至第四内部电极，并且第一电容器单元的等效串联电阻（R1）和组合的等效串联电阻（R2' ）和连接导线满足公式0.7（R1）<= R2'<= 1.3（R1）。

75. 发明授权

US07567425B1 Multilayer chip capacitor 有权
标题翻译：多层片式电容器
公开(公告)号：US07567425B1
公开(公告)日：2009-07-28
申请号：US12339839
申请日：2008-12-19
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hong Yeon Cho , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hong Yeon Cho , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/228
CPC分类号： H01G4/30 , H01G4/012 , H01G4/232 , H01G4/38
摘要： There is provided a multilayer chip capacitor including: a capacitor body including first and second capacitor units; and first to fourth outer electrodes, wherein the first capacitor unit includes at least one pair of first and second inner electrodes, the second capacitor unit includes at least one pair of third and fourth inner electrodes, an alternate laminated portion is formed in one area within the capacitor body, the alternate laminated portion having the first to fourth inner electrodes sequentially laminated therein, and a capacitance adjusting portion is formed in another area within the capacitor body, the capacitance adjusting portion having at least one of the one pair of first and second inner electrodes and the one pair of third and fourth inner electrodes laminated repeatedly.
摘要翻译：提供了一种多层片状电容器，包括：电容器主体，包括第一和第二电容器单元; 和第一至第四外部电极，其中所述第一电容器单元包括至少一对第一和第二内部电极，所述第二电容器单元包括至少一对第三和第四内部电极，在一个区域内形成交替的层叠部分电容器主体，具有依次层叠的第一至第四内部电极的交替层叠部分和电容器体内的另一区域中形成电容调整部，电容调整部具有一对第一和第二电极中的至少一个内电极和一对第三和第四内电极重复层叠。

76. 发明申请

US20090086406A1 MULTILAYER CAPACITOR 有权
标题翻译：多层电容器
公开(公告)号：US20090086406A1
公开(公告)日：2009-04-02
申请号：US12238796
申请日：2008-09-26
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/228
CPC分类号： H01G4/228
摘要： There is provided a multilayer capacitor including: a capacitor body where a plurality of dielectric layers are laminated, the capacitor body including first and second surfaces opposing each other in a laminated direction, wherein the first surface provides a mounting surface; a plurality of first and second inner electrodes; an inner connecting conductor; and a plurality of first and second outer electrodes formed on an outer surface of the body, wherein a corresponding one of the outer electrodes having identical polarity to the inner connecting conductor includes at least one outer terminal formed on the first surface of the body to connect to the inner connecting conductor, and at least one outer connecting conductor formed on the second surface of the body to connect a corresponding one of the inner electrodes of identical polarity to the inner connecting conductor.
摘要翻译：提供了一种层叠电容器，其包括：层叠多个电介质层的电容器体，所述电容器主体包括在层叠方向上彼此相对的第一和第二表面，其中所述第一表面提供安装表面; 多个第一和第二内部电极; 内连接导体; 以及形成在所述主体的外表面上的多个第一外部电极和第二外部电极，其中与所述内部连接导体具有相同极性的相应的外部电极包括形成在所述主体的所述第一表面上的至少一个外部端子，以连接内部连接导体和形成在主体的第二表面上的至少一个外部连接导体，以将相当极性的相应的一个内部电极与内部连接导体相连接。

77. 发明申请

US20090073634A1 Circuit board for mounting multilayer chip capacitor and circuit board apparatus including the multilayer chip capacitor 有权
标题翻译：用于安装多层片状电容器的电路板和包括多层片状电容器的电路板装置
公开(公告)号：US20090073634A1
公开(公告)日：2009-03-19
申请号：US12155583
申请日：2008-06-06
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/005
CPC分类号： H01L23/50 , H01G4/35 , H01L23/49838 , H01L2924/0002 , H01L2924/3011 , H05K1/0231 , H05K1/113 , H05K2201/0792 , H05K2201/09309 , H05K2201/0979 , H05K2201/10636 , Y02P70/611 , H01L2924/00
摘要： A circuit board including: a substrate having a mounting area for mounting a vertical multilayer chip capacitor having first and second external electrodes of a first polarity and a third external electrode of a second polarity; first to third pads arranged on the mounting area, the first and second pads having the first polarity and disposed separately from each other on the mounting area, the third pad having the second polarity and disposed between the first and second pads to be connected to the third external electrode; at least one first via formed in the substrate and connected to the first pad; at least one second via formed in the substrate and connected to the second pad; and a plurality of third vias formed in the substrate and connected to the third pad. The first via is disposed adjacent to the third pad relative to a central line of the first pad, the second via is disposed adjacent to the third pad relative to a central line of the second pad, one or more of the third vias are disposed adjacent to the first via relative to a central line of the third pad, and the rest of the third vias are disposed adjacent to the second via relative to the central line of the third pad.
摘要翻译：一种电路板，包括：具有用于安装具有第一极性的第一和第二外部电极和第二极性的第三外部电极的垂直多层片状电容器的安装区域的基板; 布置在安装区域上的第一至第三焊盘，第一和第二焊盘具有第一极性并且在安装区域上彼此分开设置，第三焊盘具有第二极性并且设置在第一焊盘和第二焊盘之间以连接到第三外部电极; 至少一个第一通孔，其形成在所述基板中并连接到所述第一焊盘; 至少一个第二通孔，形成在所述衬底中并连接到所述第二衬垫; 以及形成在基板中并连接到第三焊盘的多个第三通孔。第一通孔相对于第一焊盘的中心线设置成与第三焊盘相邻，第二通孔相对于第二焊盘的中心线设置为与第三焊盘相邻，第一通孔中的一个或多个邻近相对于第三焊盘的中心线移动到第一通孔，并且第三通孔的其余部分相对于第三焊盘的中心线设置成与第二通孔相邻。

78. 发明申请

US20080165469A1 Multilayer chip capacitor 有权
标题翻译：多层片式电容器
公开(公告)号：US20080165469A1
公开(公告)日：2008-07-10
申请号：US12003884
申请日：2008-01-03
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/228 , H01G4/005
CPC分类号： H01G4/30 , H01G4/012 , H01G4/232
摘要： A multilayer chip capacitor including: a capacitor body formed of a lamination of a plurality of dielectric layers and having a bottom surface that is a mounting area; a plurality of internal electrodes disposed to be opposite to each other, interposing a dielectric layer there between in the capacitor body and having one lead extended to the bottom surface, respectively; and three or more external electrodes formed on the bottom surface and connected to corresponding internal electrodes via the leads, wherein the internal electrodes are vertically disposed on the bottom surface, and the leads of the internal electrodes having a different polarity from each other, adjacent to each other in a lamination direction, are disposed to be always adjacent to each other in a horizontal direction.
摘要翻译：一种多层片状电容器，包括：电容器本体，其由多个电介质层的叠层形成，并且具有作为安装区域的底面; 设置成彼此相对的多个内部电极，在电容器主体之间插入介电层，并具有分别延伸到底面的一个引线; 以及三个或更多个外部电极，形成在底表面上并且经由引线连接到相应的内部电极，其中内部电极垂直设置在底部表面上，并且内部电极的引线彼此具有不同的极性，彼此在层叠方向上彼此沿水平方向布置。

79. 发明授权

US07843702B2 Printed circuit board having embedded RF module power stage circuit 失效
标题翻译：具有嵌入式RF模块功率级电路的印刷电路板
公开(公告)号：US07843702B2
公开(公告)日：2010-11-30
申请号：US12437042
申请日：2009-05-07
申请人： Don Chul Choi , Jae Cheol Ju , Dong Hwan Lee , Sang Soo Park , Hee Soo Yoon
发明人： Don Chul Choi , Jae Cheol Ju , Dong Hwan Lee , Sang Soo Park , Hee Soo Yoon
IPC分类号： H05K1/18
CPC分类号： H05K1/023 , H01L24/24 , H01L24/82 , H01L2224/24226 , H01L2224/82039 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01019 , H01L2924/01033 , H01L2924/0104 , H01L2924/01046 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/04941 , H01L2924/10253 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30107 , H05K1/0233 , H05K1/112 , H05K1/16 , H05K1/162 , H05K3/4611 , H05K2201/09309 , H05K2201/09454 , H05K2201/09718 , H05K2201/10022 , H05K2201/1003 , H01L2924/00
摘要： Disclosed herein is a printed circuit board having an RF module power stage circuit embedded therein. Specifically, this invention relates to a printed circuit board having an RF module power stage circuit embedded therein, in which a terminal pad for a resistor, a bead, or an inductor is defined or formed on a power supply plane of a multilayered wired board to connect the resistor, the bead, or the inductor to the power supply plane, and the resistor, the bead, or the inductor is connected in parallel with a decoupling capacitor by using a via hole or by embedding the resistor, the bead or the inductor perpendicular to the power supply plane, thus decreasing the size of the RF module and improving the performance thereof.
摘要翻译：这里公开了具有嵌入其中的RF模块功率级电路的印刷电路板。具体地说，本发明涉及一种具有嵌入其中的RF模块功率级电路的印刷电路板，其中在多层有线电路板的电源平面上限定或形成用于电阻器，焊道或电感器的端子焊盘，将电阻器，焊道或电感器连接到电源平面，并且电阻器，焊道或电感器通过使用通孔或通过嵌入电阻器，焊道或电感器而与去耦电容器并联连接垂直于电源平面，从而减小RF模块的尺寸并提高其性能。

80. 发明申请

US20090268419A1 PRINTED CIRCUIT BOARD HAVING EMBEDDED RF MODULE POWER STAGE CIRCUIT 失效
公开(公告)号：US20090268419A1
公开(公告)日：2009-10-29
申请号：US12436996
申请日：2009-05-07
申请人： Don Chul Choi , Jae Cheol Ju , Dong Hwan Lee , Sang Soo Park , Hee Soo Yoon
发明人： Don Chul Choi , Jae Cheol Ju , Dong Hwan Lee , Sang Soo Park , Hee Soo Yoon
IPC分类号： H05K7/12
CPC分类号： H05K1/023 , H01L24/24 , H01L24/82 , H01L2224/24226 , H01L2224/82039 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01019 , H01L2924/01033 , H01L2924/0104 , H01L2924/01046 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/04941 , H01L2924/10253 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30107 , H05K1/0233 , H05K1/112 , H05K1/16 , H05K1/162 , H05K3/4611 , H05K2201/09309 , H05K2201/09454 , H05K2201/09718 , H05K2201/10022 , H05K2201/1003 , H01L2924/00
摘要： Disclosed herein is a printed circuit board having an RF module power stage circuit embedded therein. Specifically, this invention relates to a printed circuit board having an RF module power stage circuit embedded therein, in which a terminal pad for a resistor, a bead, or an inductor is defined or formed on a power supply plane of a multilayered wired board to connect the resistor, the bead, or the inductor to the power supply plane, and the resistor, the bead, or the inductor is connected in parallel with a decoupling capacitor by using a via hole or by embedding the resistor, the bead or the inductor perpendicular to the power supply plane, thus decreasing the size of the RF module and improving the performance thereof.

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