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71. 发明申请

US20090066424A1 Programmable Interpolative Voltage Controlled Oscillator with Adjustable Range 审中-公开
标题翻译：可编程内插电压控制振荡器，可调范围
公开(公告)号：US20090066424A1
公开(公告)日：2009-03-12
申请号：US11853905
申请日：2007-09-12
申请人： David W. Boerstler , Eskinder Hailu , Masaaki Kaneko , Jieming Qi
发明人： David W. Boerstler , Eskinder Hailu , Masaaki Kaneko , Jieming Qi
IPC分类号： H03L7/00
CPC分类号： H03L7/18 , H03L7/0998
摘要： A programmable interpolative voltage controlled oscillator (VCO) with adjustable frequency range output is provided. With the VCO, programmable delay cells whose size is modifiable based on control inputs to the programmable delay cells are utilized. A different set of control inputs may be provided to programmable delay cells of an inner sub-ring from the set of control inputs provided to programmable delay cells of a main ring of the VCO. The minimum frequency output of the VCO is governed by the main ring programmable delay cell strength with the maximum frequency output of the VCO being governed by a ratio of strengths of the main ring programmable delay cells to the inner sub-ring programmable delay cell. By modifying the control inputs to the inner sub-ring and main ring programmable delay cells, the minimum and maximum frequency outputs, and thus the range between these two frequency outputs, are made programmable.
摘要翻译：提供了具有可调频率范围输出的可编程内插压控振荡器（VCO）。利用VCO，可以利用基于可编程延迟单元的控制输入来修改尺寸的可编程延迟单元。从提供给VCO的主环的可编程延迟单元的控制输入的集合可以向内部子环的可编程延迟单元提供不同的一组控制输入。 VCO的最小频率输出由主环路可编程延迟单元强度控制，VCO的最大频率输出由主环可编程延迟单元与内部子环可编程延迟单元的强度比控制。通过修改内部子环和主环可编程延迟单元的控制输入，可以将最小和最大频率输出，从而将这两个频率输出之间的范围编程为可编程。

72. 发明申请

US20080229270A1 Design Structure for a Duty Cycle Correction Circuit 有权
标题翻译：一种占空比校正电路的设计结构
公开(公告)号：US20080229270A1
公开(公告)日：2008-09-18
申请号：US12128754
申请日：2008-05-29
申请人： David W. Boerstler , Eskinder Hailu , Jieming Qi
发明人： David W. Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： G06F17/50 , H03K3/017
CPC分类号： H03K5/1565 , H03K2005/00058 , H03K2005/00221
摘要： A design structure for a Duty Cycle Correction (DCC) circuit is provide in which pairs of field effect transistors (FETs) in known DCC circuit topologies are replaced with linear resistors coupled to switches of the DCC circuit such that when the switch is open, the input signal is routed through the linear resistors. The linear resistors are more tolerant of process, voltage and temperature (PVT) fluctuations than FETs and thus, the resulting DCC circuit provides a relatively smaller change in DCC correction range with PVT fluctuations than the known DCC circuit topology that employs FETs. The linear resistors may be provided in parallel with the switches and in series with a pair of FETs having relatively large resistance values. The linear resistors provide resistance that pulls-up or pulls-down the pulse width of the input signal so as to provide correction to the duty cycle of the input signal.
摘要翻译：提供了一种用于占空比校正（DCC）电路的设计结构，其中已知DCC电路拓扑中的场效应晶体管（FET）中的对被替换为与DCC电路的开关耦合的线性电阻器，使得当开关断开时，输入信号通过线性电阻器路由。线性电阻器比FET更容忍工艺，电压和温度（PVT）波动，因此，所得到的DCC电路与使用FET的已知DCC电路拓扑结构相比，具有PVT波动的DCC校正范围相对较小的变化。线性电阻器可以与开关并联设置并且与具有相对较大电阻值的一对FET串联。线性电阻器提供上拉或下拉输入信号的脉冲宽度的电阻，以便对输入信号的占空比提供校正。

73. 发明申请

US20080222585A1 INTERLEAVED VOLTAGE CONTROLLED OSCILLATOR 有权
标题翻译：交流电压控制振荡器
公开(公告)号：US20080222585A1
公开(公告)日：2008-09-11
申请号：US12126076
申请日：2008-05-23
申请人： David W. Boerstler , Eskinder Hailu , Jieming Qi , Mike Shen
发明人： David W. Boerstler , Eskinder Hailu , Jieming Qi , Mike Shen
IPC分类号： G06F17/50
CPC分类号： H03L7/0995 , H03K3/0315 , H03K5/133
摘要： A design structure embodied in a machine readable medium used in a design process includes an interleaved voltage-controlled oscillator, including a ring circuit of main logic inverter gates; a plurality of delay elements connected in parallel with a selected sequence of the main logic inverter gates; wherein each delay element comprises a feedforward section, comprising controls for regulating signal transmission through feedforward elements responsive to one or more control voltages; and a proportional section for regulating signal transmission through at least one logic inverter gate; at least one temperature compensation circuit responsive to a compensating voltage input that is proportional to temperature; an electronic circuit in communication with the temperature compensation circuit and configured to provide a voltage signal responsive to temperature; an amplifier in connection with the electronic circuit to amplify the voltage signal; and a DC offset generator configured to adjust the voltage of the amplified voltage signal.
摘要翻译：体现在设计过程中使用的机器可读介质中的设计结构包括交错压控振荡器，包括主逻辑逆变器门的环形电路; 多个延迟元件，与所述主逻辑反相器门的选定序列并联连接; 其中每个延迟元件包括前馈部分，其包括用于响应于一个或多个控制电压来调节通过前馈元件的信号传输的控制; 以及用于调节通过至少一个逻辑反相器门的信号传输的比例部分; 响应于与温度成比例的补偿电压输入的至少一个温度补偿电路; 与所述温度补偿电路通信并且被配置为提供响应于温度的电压信号的电子电路; 与电子电路相连的放大器，用于放大电压信号; 以及配置成调整放大的电压信号的电压的DC偏移发生器。

74. 发明授权

US07417480B2 Duty cycle correction circuit whose operation is largely independent of operating voltage and process 有权
标题翻译：工作循环校正电路的工作原理很大程度上与工作电压和工艺无关
公开(公告)号：US07417480B2
公开(公告)日：2008-08-26
申请号：US11457637
申请日：2006-07-14
申请人： David W. Boerstler , Eskinder Hailu , Jieming Qi
发明人： David W. Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A Duty Cycle Correction (DCC) circuit is provide in which pairs of field effect transistors (FETs) in known DCC circuit topologies are replaced with linear resistors coupled to switches of the DCC circuit such that when the switch is open, the input signal is routed through the linear resistors. The linear resistors are more tolerant of process, voltage and temperature (PVT) fluctuations than FETs and thus, the resulting DCC circuit provides a relatively smaller change in DCC correction range with PVT fluctuations than the known DCC circuit topology that employs FETs. The linear resistors may be provided in parallel with the switches and in series with a pair of FETs having relatively large resistance values. The linear resistors provide resistance that pulls-up or pulls-down the pulse width of the input signal so as to provide correction to the duty cycle of the input signal.
摘要翻译：提供了一种占空比校正（DCC）电路，其中已知DCC电路拓扑中的成对的场效应晶体管（FET）被连接到DCC电路的开关的线性电阻器代替，使得当开关断开时，输入信号被路由通过线性电阻。线性电阻器比FET更容忍工艺，电压和温度（PVT）波动，因此，所得到的DCC电路与使用FET的已知DCC电路拓扑结构相比，具有PVT波动的DCC校正范围相对较小的变化。线性电阻器可以与开关并联设置并且与具有相对较大电阻值的一对FET串联。线性电阻器提供上拉或下拉输入信号的脉冲宽度的电阻，以便对输入信号的占空比提供校正。

75. 发明授权

US07391277B2 Interleaved voltage controlled oscillator 有权
标题翻译：交错压控振荡器
公开(公告)号：US07391277B2
公开(公告)日：2008-06-24
申请号：US11458753
申请日：2006-07-20
申请人： David W. Boerstler , Eskinder Hailu , Jieming Qi , Mike Shen
发明人： David W. Boerstler , Eskinder Hailu , Jieming Qi , Mike Shen
IPC分类号： H03B27/00
CPC分类号： H03L7/0995 , H03K3/0315 , H03K5/133
摘要： An interleaved voltage-controlled oscillator (VCO) is disclosed. The VCO includes a ring circuit comprising a series connection of main logic inverter gates, a plurality of delay elements connected in parallel with a selected sequence of the main logic inverter gates, at least one temperature compensation circuit comprising a logic inverter gate in series connection with one or more field effect transistors, the field effect transistor responsive to a compensating voltage input that is proportional to temperature, and an electronic circuit in signal communication with the at least one temperature compensation circuit and configured to provide a voltage signal responsive to temperature. Each delay element includes a feedforward section, comprising controls for regulating signal transmission through feedforward elements responsive to one or more control voltages, and a proportional section, comprising controls for regulating signal transmission through at least one logic inverter gate.
摘要翻译：公开了一种交错压控振荡器（VCO）。 VCO包括环形电路，其包括主逻辑反相器门的串联连接，与主逻辑反相器门的选定序列并联连接的多个延迟元件，至少一个温度补偿电路，包括与一个或多个场效应晶体管，所述场效应晶体管响应于与温度成比例的补偿电压输入;以及电子电路，其与所述至少一个温度补偿电路进行信号通信，并且被配置为提供响应于温度的电压信号。每个延迟元件包括前馈部分，其包括用于响应于一个或多个控制电压来调节通过前馈元件的信号传输的控制，以及比例部分，包括用于调节通过至少一个逻辑反相器门的信号传输的控制。

76. 发明授权

US07360135B2 Apparatus and method for automatically self-calibrating a duty cycle circuit for maximum chip performance 有权
标题翻译：用于自动自校准占空比电路以实现最大芯片性能的装置和方法
公开(公告)号：US07360135B2
公开(公告)日：2008-04-15
申请号：US11848314
申请日：2007-08-31
申请人： David W. Boerstler , Eskinder Hailu , Jieming Qi
发明人： David W. Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： G01R31/28 , H03K3/017
CPC分类号： H03K5/1565 , G01R31/31727 , G01R31/3187
摘要： An apparatus and method for automatically calibrating a duty cycle circuit for maximum performance. A chip level built-in circuit automatically calibrates the duty cycle correction (DCC) circuit setting for each chip. The chip level built-in circuit includes a clock generation macro unit, a simple duty cycle correction (DCC) circuit, an array slice and built-in self test unit, and a DCC circuit controller. A built-in self test provides results, i.e. pass or fail, of an array to the DCC circuit controller. If the result of the built-in self test is a pass, then the current DCC circuit controller's DCC control bit setting is set as the setting for the chip. If the result from the built-in self test is a fail, the DCC circuit controller's DCC control bits setting is incremented to a next setting and the self-test is performed again.
摘要翻译：一种用于自动校准占空比电路以实现最大性能的装置和方法。芯片级内置电路自动校准每个芯片的占空比校正（DCC）电路设置。芯片级内置电路包括时钟生成宏单元，简单占空比校正（DCC）电路，阵列片和内置自检单元以及DCC电路控制器。内置的自检向DCC电路控制器提供阵列的结果，即通过或失败。如果内置自检的结果是通过，则将当前DCC电路控制器的DCC控制位设置设置为芯片的设置。如果内置自检的结果为失败，DCC电路控制器的DCC控制位设置将增加到下一个设置，并再次执行自检。

77. 发明申请

US20080018408A1 INTERLEAVED VOLTAGE CONTROLLED OSCILLATOR 有权
标题翻译：交流电压控制振荡器
公开(公告)号：US20080018408A1
公开(公告)日：2008-01-24
申请号：US11458753
申请日：2006-07-20
申请人： David W. Boerstler , Eskinder Hailu , Jieming Qi , Mike Shen
发明人： David W. Boerstler , Eskinder Hailu , Jieming Qi , Mike Shen
IPC分类号： H03K3/03
CPC分类号： H03L7/0995 , H03K3/0315 , H03K5/133
摘要： An interleaved voltage-controlled oscillator (VCO) is disclosed. The VCO includes a ring circuit comprising a series connection of main logic inverter gates, a plurality of delay elements connected in parallel with a selected sequence of the main logic inverter gates, at least one temperature compensation circuit comprising a logic inverter gate in series connection with one or more field effect transistors, the field effect transistor responsive to a compensating voltage input that is proportional to temperature, and an electronic circuit in signal communication with the at least one temperature compensation circuit and configured to provide a voltage signal responsive to temperature. Each delay element includes a feedforward section, comprising controls for regulating signal transmission through feedforward elements responsive to one or more control voltages, and a proportional section, comprising controls for regulating signal transmission through at least one logic inverter gate.
摘要翻译：公开了一种交错压控振荡器（VCO）。 VCO包括环形电路，其包括主逻辑反相器门的串联连接，与主逻辑反相器门的选定序列并联连接的多个延迟元件，至少一个温度补偿电路，包括与一个或多个场效应晶体管，所述场效应晶体管响应于与温度成比例的补偿电压输入;以及电子电路，其与所述至少一个温度补偿电路进行信号通信，并且被配置为提供响应于温度的电压信号。每个延迟元件包括前馈部分，其包括用于响应于一个或多个控制电压来调节通过前馈元件的信号传输的控制，以及比例部分，包括用于调节通过至少一个逻辑反相器门的信号传输的控制。

78. 发明申请

US20070071155A1 Information handling system capable of detecting frequency lock of signals downstream from a signal synthesized by frequency synthesizer 失效
标题翻译：信号处理系统能够检测由频率合成器合成的信号下行信号的频率锁定
公开(公告)号：US20070071155A1
公开(公告)日：2007-03-29
申请号：US11236834
申请日：2005-09-27
申请人： David Boerstler , Matthew Fernsler , Eskinder Hailu , Jieming Qi , Mack Riley
发明人： David Boerstler , Matthew Fernsler , Eskinder Hailu , Jieming Qi , Mack Riley
IPC分类号： H04B17/00 , H03D3/24
CPC分类号： G06F1/10 , H03L7/095
摘要： An information handling system including a frequency synthesizer lock detection system is disclosed that distributes a frequency synthesizer output signal across a distribution network to one or more receptor circuits. The distribution network may exhibit delay and other distortion that may cause the downstream signal arriving at the receptor circuit to lose frequency lock with both the frequency synthesizer output signal and a reference clock signal that controls the frequency of the synthesizer output signal. The lock detection system tests the downstream signal to determine if the downstream signal exhibits a lock with respect to the reference clock that determines the operating frequency of the frequency synthesizer. In this manner, lock of the downstream signal to the reference clock signal may be accurately assessed in one embodiment.
摘要翻译：公开了一种包括频率合成器锁定检测系统的信息处理系统，其将分频网络上的频率合成器输出信号分配到一个或多个接收器电路。分配网络可能表现出延迟和其他失真，这些失真可能导致下游信号到达接收器电路，同时使用频率合成器输出信号和控制合成器输出信号频率的参考时钟信号来失去频率锁定。锁定检测系统测试下行信号以确定下游信号是否相对于确定频率合成器的工作频率的参考时钟呈现锁定。以这种方式，可以在一个实施例中精确地评估下行信号到参考时钟信号的锁定。

79. 发明申请

US20060190746A1 System and method for automatic calibration of a reference voltage 失效
标题翻译：用于自动校准参考电压的系统和方法
公开(公告)号：US20060190746A1
公开(公告)日：2006-08-24
申请号：US11065549
申请日：2005-02-24
申请人： David Boerstler , Eskinder Hailu , Jieming Qi
发明人： David Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： G06F1/26
CPC分类号： G06F1/26
摘要： A system and system for automatic voltage calibration is presented. A voltage calibration system includes three main units, which are a voltage level trimming unit, a trim detection unit, and a trim control unit. The three units work in conjunction with each other during a trimming operation in order to identify a tap voltage that is closest to a target voltage. In one embodiment, the voltage calibration system may be used to calibrate a voltage regulator. Upon commencement of calibration, the voltage regulator's feedback loop is open, and the target voltage is selected as the input for the feedback port of the amplifier. The voltage regulator serves as a voltage comparator that compares each tap voltage to the target voltage. When the calibration is complete, regulator's feedback loop is closed and the closest tap voltage to the target voltage is used as the regulator's input.
摘要翻译：提出了一种用于自动电压校准的系统和系统。电压校准系统包括三个主要单元，它们是电压调整单元，微调检测单元和微调控制单元。三个单元在微调操作期间相互协调工作，以便识别最接近目标电压的抽头电压。在一个实施例中，电压校准系统可用于校准电压调节器。校准开始后，电压调节器的反馈回路打开，目标电压被选为放大器反馈端口的输入。电压调节器用作将每个抽头电压与目标电压进行比较的电压比较器。当校准完成时，调节器的反馈回路闭合，并将最接近目标电压的分接电压用作调节器的输入。

80. 发明申请

US20060091965A1 Novel circuit for minimizing filter capacitance leakage induced jitter in phase locked loops (PLLs) 有权
标题翻译：用于最大限度地减少锁相环（PLL）中滤波电容泄漏引起的抖动的新型电路
公开(公告)号：US20060091965A1
公开(公告)日：2006-05-04
申请号：US10981155
申请日：2004-11-04
申请人： David Boerstler , Eskinder Hailu , Jieming Qi
发明人： David Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： H03L7/00
CPC分类号： H03L7/0893 , H03L7/093 , H03L7/095
摘要： A method, an apparatus, and a computer program are provided to minimize filter capacitor leakage in a Phased Locked Loop (PLL). In high frequency processors and devices, filter leakage currents can cause substantial problems by causing PLLs to drift out of phase lock. To combat the leakage currents, a dummy filter and other components are employed to provide additional charge or voltage to a low pass filter during lock. The provision of the charge or voltage exponentially decreases the rate of decay of voltage across the low pass filter caused by leakage currents.
摘要翻译：提供了一种方法，装置和计算机程序以最小化相位锁定环（PLL）中的滤波电容器泄漏。在高频处理器和器件中，滤波器漏电流可能会导致相位锁相位漂移出现相当大的问题。为了防止泄漏电流，使用虚拟滤波器和其他组件在锁定期间向低通滤波器提供额外的充电或电压。充电或电压的提供以指数方式降低由漏电流引起的低通滤波器的电压衰减速率。

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