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71. 发明授权

US5834288A KDN-specific deminoneuraminidase from Sphingobacterium multivorum 失效
标题翻译：来自多翅目的Kdn特异性去氨基唾液酸酶
公开(公告)号：US5834288A
公开(公告)日：1998-11-10
申请号：US765491
申请日：1997-04-08
申请人： Yasuo Inoue , Sadako Inoue , Ken Kitajima
发明人： Yasuo Inoue , Sadako Inoue , Ken Kitajima
IPC分类号： C12N1/20 , C12N9/24 , C12P19/14 , C12R1/01 , C12N9/26
CPC分类号： C12Y302/01018 , C12N9/2402
摘要： The bacterium Sphingobacterium multivorum has been cultivated to produce a deaminoneuraminidase which is specific for catalyzing the hydrolysis of the ketosidic linkage formed by deaminoneuraminic acid in complex carbohydrates. The deaminoneuraminidase does not catalyze the hydrolysis of either the ketosidic linkage formed by N-acetylneuraminic acid or the ketosidic linkage formed by n-glycolylneuraminic acid and complex carbohydrates.
摘要翻译： PCT No.PCT / JP95 / 01213 Sec。 371日期1997年4月8日 102（e）日期1997年4月8日PCT Filed 1995年6月19日PCT Pub。公开号WO96 / 00781 日期1996年1月11日已经培养了多细菌Sphingobacterium细菌以产生脱氨基神经氨酸酶，其对于催化由复合碳水化合物中的脱氨基神经氨酸形成的酮糖键的水解是特异性的。脱氨基神经氨酸酶不催化由N-乙酰神经氨酸形成的酮糖键或由N-羟乙酰神经氨酸和复合碳水化合物形成的酮糖键的水解。

72. 发明授权

US5640600A Storage controller and bus control method for use therewith 失效
标题翻译：存储控制器和总线控制方法
公开(公告)号：US5640600A
公开(公告)日：1997-06-17
申请号：US381560
申请日：1995-01-31
申请人： Takao Satoh , Hisaharu Takeuchi , Yasuo Inoue , Akira Yamamoto
发明人： Takao Satoh , Hisaharu Takeuchi , Yasuo Inoue , Akira Yamamoto
IPC分类号： G06F13/16 , G06F3/06 , G06F11/34 , G06F13/12 , G06F13/36 , H01J3/00
CPC分类号： G06F13/124 , G06F11/349 , G06F11/3409 , G06F2201/88 , G06F2201/885
摘要： A storage controller comprising a storage device adapter, a channel adapter, a cache memory, a control memory, and a plurality of buses connecting therebetween. The channel adapter communicates with a processor and processes input/output requests issued by the processor. The storage device adapter controls a storage device and data transfer between the storage device and the cache memory. The channel adapter and the storage device adapter exchanges control information via the control memory. The buses are used to transfer the data and the control information between the cache memory and the control memory, and the channel adapter and the storage device adapter. The controller also comprises bus load estimating means and bus mode selecting means. The bus load estimating means estimates bus load characteristics as an index based on the amount of data transfer during sequential access to the storage device. The bus mode selecting means determines a bus mode of bus utilization based on the index. Each of the channel adapter and the storage device adapter has bus access means for accessing the buses in accordance with the bus mode selected by the bus mode selecting means.
摘要翻译：存储控制器，包括存储设备适配器，信道适配器，高速缓冲存储器，控制存储器以及连接在它们之间的多个总线。信道适配器与处理器通信并处理由处理器发出的输入/输出请求。存储设备适配器控制存储设备和存储设备与高速缓冲存储器之间的数据传输。通道适配器和存储设备适配器通过控制存储器交换控制信息。总线用于将数据和控制信息传输到缓存存储器和控制存储器之间，以及通道适配器和存储设备适配器。控制器还包括总线负载估计装置和总线模式选择装置。总线负载估计装置基于在顺序访问存储设备期间的数据传输量来估计总线负载特性作为索引。总线模式选择装置根据该索引确定总线利用的总线模式。每个通道适配器和存储设备适配器具有总线访问装置，用于根据由总线模式选择装置选择的总线模式访问总线。

73. 发明授权

US5459856A System having independent access paths for permitting independent access from the host and storage device to respective cache memories 失效
标题翻译：具有用于允许从主机和存储设备到相应高速缓冲存储器的独立访问的独立访问路径的系统
公开(公告)号：US5459856A
公开(公告)日：1995-10-17
申请号：US984763
申请日：1992-12-03
申请人： Yasuo Inoue
发明人： Yasuo Inoue
IPC分类号： G06F3/06 , G06F3/00 , G06F12/08 , G06F13/12 , G06F13/14 , G06F13/38 , G11C29/00 , G06F11/20
CPC分类号： G06F3/0601 , G06F12/0866 , G06F3/061 , G06F3/0656 , G06F3/0658 , G06F3/0689 , G11C29/006 , H04L67/1097 , G06F2003/0692
摘要： A plurality of independent cache units and nonvolatile memory units are provided in a disk controller located between a host (central processing unit) and a magnetic disk drive. A plurality of channel units for controlling the data transfer to and from the central processing unit and a plurality of control units for controlling the data transfer to and from the magnetic disk drive are independently connected to the cache units and the nonvolatile memory units through data buses and access lines.
摘要翻译：在位于主机（中央处理单元）和磁盘驱动器之间的盘控制器中提供多个独立高速缓存单元和非易失性存储器单元。用于控制来自中央处理单元的数据传送的多个通道单元和用于控制与磁盘驱动器的数据传送的多个控制单元通过数据总线独立地连接到高速缓存单元和非易失性存储器单元和接入线路。

74. 发明授权

US5340645A Potassium hexatitanate fibers having tunnel structure, process for producing the same, and composite material containing said fibers 失效
标题翻译：具有隧道结构的六钛酸钾纤维，其制造方法和含有所述纤维的复合材料
公开(公告)号：US5340645A
公开(公告)日：1994-08-23
申请号：US24832
申请日：1993-03-02
申请人： Hidefumi Harada , Yasuo Inoue
发明人： Hidefumi Harada , Yasuo Inoue
IPC分类号： C01G23/00 , C08K7/00 , C08K7/08 , C08L101/00 , C22C47/00 , C22C49/00 , C22C49/04 , C22C49/06 , D01F9/08 , B32B5/02 , C04B35/02
CPC分类号： D01F9/08 , C01G23/005 , C01P2004/10 , C01P2004/61 , C01P2006/60 , Y10T428/24994 , Y10T428/249948 , Y10T428/294 , Y10T428/2975 , Y10T428/31507 , Y10T428/31678
摘要： Potassium hexatitanate fibers having a tunnel structure and a free potassium content of 5 ppm or less can be produced by mixing together a titanium containing compound and a potassium containing compound in a ratio represented by the formula K.sub.2 O.nTiO.sub.2 (wherein n=from 2 to 4); firing the mixture at 900.degree. to 1,200.degree. C. to produce mass of potassium titanate fibers; dipping the mass of product in either cold or hot water to disintegrate the mass of potassium titanate fibers into individual single fibers; adding an acid to the slurry to adjust the pH value to 9.3-9.7, thereby changing the composition of the potassium titanate fibers so that the molar ratio of TiO.sub.2 /K.sub.2 O is in the range of from 5.95 to 6.00; heating the fibers at 950.degree. to 1,150.degree. C. for 1 hour or more; and washing the fibers with an acid. The potassium hexatitanate fibers, which have a minimal free potassium content, i.e., 5 ppm or less, can be suitably used as a reinforcing material for polyester thermoplastic resins, polyphenylene sulfide resins, liquid crystal polymers, aluminum alloys, magnesium alloys and so forth, all of which are easily affected by free potassium.
摘要翻译：通过将含钛化合物和含钾化合物以通式K 2 O·nTiO 2（其中n = 2〜4）表示的比例混合在一起，可以制备具有隧道结构和游离钾含量为5ppm以下的六钛酸钾纤维）; 在900〜1200℃下烧成混合物，生成钛酸钾纤维; 将产品的质量浸入冷或热水中以将钛酸钾纤维的质量分解成单个单根纤维; 向浆料中加入酸以将pH值调节至9.3-9.7，从而改变钛酸钾纤维的组成，使得TiO 2 / K 2 O的摩尔比在5.95至6.00的范围内; 在950〜1150℃下加热纤维1小时以上; 并用酸洗涤纤维。具有最小游离钾含量（即5ppm以下）的六钛酸钾纤维可以适合用作聚酯热塑性树脂，聚苯硫醚树脂，液晶聚合物，铝合金，镁合金等的增强材料，所有这些都容易受到游离钾的影响。

75. 发明授权

US5283455A Thin film field effect element having an LDD structure 失效
标题翻译：具有LDD结构的薄膜场效应元件
公开(公告)号：US5283455A
公开(公告)日：1994-02-01
申请号：US911582
申请日：1992-07-10
申请人： Yasuo Inoue , Tadashi Nishimura , Motoi Ashida
发明人： Yasuo Inoue , Tadashi Nishimura , Motoi Ashida
IPC分类号： H01L29/78 , H01L21/336 , H01L29/786 , H01L29/76 , H01L27/01 , H01L29/94 , H01L31/062
CPC分类号： H01L29/6675 , H01L29/66765 , H01L29/78624 , H01L29/78642
摘要： An upper insulating layer is formed on an upper surface of a gate electrode formed on an insulating substrate. A gate insulating layer is formed on sidewalls of the gate electrode and the surfaces of the upper insulating layer. A semiconductor layer is formed on the surfaces of the gate insulating layer. Three source/drain regions are formed in the semiconductor layer. Two independent channel regions are formed in the semiconductor layer along both side surfaces of the gate electrode. Source/drain regions are arranged on both ends of two channel regions. Each source/drain region has an LDD structure formed in a self alignment manner by an oblique ion implantation method and a vertical ion implantation method using sidewall insulating layers formed on the channel regions as masks.
摘要翻译：在绝缘基板上形成的栅电极的上表面上形成上绝缘层。栅极绝缘层形成在栅电极的侧壁和上绝缘层的表面上。在栅极绝缘层的表面上形成半导体层。在半导体层中形成三个源/漏区。沿着栅电极的两个侧表面在半导体层中形成两个独立的沟道区。源极/漏极区域布置在两个沟道区域的两端。每个源极/漏极区域具有通过倾斜离子注入方法以自对准方式形成的LDD结构和使用在沟道区上形成的侧壁绝缘层作为掩模的垂直离子注入方法。

76. 发明授权

US5083225A Digital signal recording and playback apparatus 失效
标题翻译：数字信号记录和播放装置
公开(公告)号：US5083225A
公开(公告)日：1992-01-21
申请号：US310530
申请日：1989-02-15
申请人： Kazuhiko Morisaki , Yasuo Inoue
发明人： Kazuhiko Morisaki , Yasuo Inoue
IPC分类号： G11B5/09 , G11B5/008 , G11B5/53 , G11B15/12 , G11B15/18 , G11B15/467 , G11B27/032
CPC分类号： G11B5/0086 , G11B15/125 , G11B15/1875 , G11B15/4671 , G11B27/032 , G11B5/534 , G11B2220/90 , G11B2220/913
摘要： A digital signal recording and playback apparatus having a rotary heads mounted on a rotary drum capable of recording/reproducing a digital signal onto/from a magnetic tape at a tape speed which is N times as much as the standard speed while conforming to the standard track angle and length. The number of the rotary heads are increased from the standard two heads whereas the drum speed is made one half of N times standard speed and the drum diameter is made slightly larger from the standard so that the relative speed between the running tape and the rotating heads becomes equal to the standard in the double tape speed mode, and becomes twice that in the quadruple tape speed mode. Alternatively, the tape is wound around the drum having two heads, over the angular range of 180 degrees instead of the standard 90 degrees, the drum diameter is made smaller than the standard, and the drum speed is N times the standard so that the relative speed of the heads becomes equal to the standard in the double tape speed mode.
摘要翻译：一种数字信号记录和重放装置，其具有安装在旋转磁鼓上的旋转磁头，其能够以符合标准磁道的标准速度的N倍的磁带速度将数字信号记录到磁带上/从磁带重放数字信号角度和长度。旋转头的数量从标准的两个头增加，而鼓速度是标准速度的N倍的一半，并且鼓的直径从标准形成为稍大，使得行走带和旋转头之间的相对速度变为双带速度模式中的标准，并且变为四倍速带速度模式下的两倍。或者，磁带卷绕在具有两个磁头的磁鼓上，角度范围为180度，而不是标准90度，磁鼓直径小于标准，鼓速度是标准的N倍，使得相对磁头速度等于双磁带速度模式下的标准。

77. 发明授权

US5001539A Multiple layer static random access memory device 失效
标题翻译：多层静态随机存取存储器件
公开(公告)号：US5001539A
公开(公告)日：1991-03-19
申请号：US337702
申请日：1989-04-13
申请人： Yasuo Inoue , Tadashi Nishimura
发明人： Yasuo Inoue , Tadashi Nishimura
IPC分类号： G11C11/412 , H01L21/8244 , H01L27/00 , H01L27/06 , H01L27/11
CPC分类号： H01L27/1104 , H01L27/0688 , H01L27/1108 , Y10S257/903
摘要： A stacked static random access memory SRAM having a plurality of memory cells is disclosed. Individual memory cell has a portion formed in an upper active element layer in the device structure and a portion formed in a lower active element layer in the device structure separated from the upper layer by an intermediate insulating layer. A word line, a bit line and access transistors are formed in the same upper active element layer, eliminating the need for interconnecting them through the insulating layer. The elimination of the inter-layer connections helps to reduce the number of through-holes required to be made in the insulating layer. This in turn reduces the area to be occupied by the memory cell and leads to a simplified manufacturing process of the SRAM.
摘要翻译：公开了一种具有多个存储单元的堆叠静态随机存取存储器SRAM。单个存储单元具有形成在器件结构中的上有源元件层中的部分，以及通过中间绝缘层与器件结构中的下有源元件层中形成的部分形成在上层中的部分。在相同的上部有源元件层中形成字线，位线和存取晶体管，消除了通过绝缘层将它们互连的需要。层间连接的消除有助于减少在绝缘层中制造的通孔的数量。这又减少了由存储器单元占用的面积，并导致了SRAM的简化制造过程。

78. 发明授权

US4987092A Process for manufacturing stacked semiconductor devices 失效
标题翻译：叠层半导体器件的制造方法
公开(公告)号：US4987092A
公开(公告)日：1991-01-22
申请号：US204581
申请日：1988-06-09
申请人： Kiyoteru Kobayashi , Tadashi Nishimura , Hiroshi Morita , Shuji Nakao , Hidekazu Oda , Yasuo Inoue
发明人： Kiyoteru Kobayashi , Tadashi Nishimura , Hiroshi Morita , Shuji Nakao , Hidekazu Oda , Yasuo Inoue
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/822 , H01L21/8244 , H01L27/00 , H01L27/092 , H01L27/11 , H01L29/78 , H01L29/786
CPC分类号： H01L27/11 , H01L21/8221 , H01L27/1104 , H01L27/1108
摘要： An improved method of manufacturing semiconductor devices having a stacked structure is disclosed. A p-channel semiconductor substrate is prepared, and on the major surface of the substrate, n-channel source and drain regions and a gate electrode are formed to provide a n-channel transistor. Sidewalls are formed of P type single-crystal silicon on the opposite size of the gate electrode of n-channel transistor with an insulating layer interposed between the sidewalls and the gate electrode. A single-crystal layer covers the source, drain and gate electrode of the n-channel transistor and the sidewall structures. A P type impurity present in the sidewalls is diffused into the single-crystal layer.
摘要翻译：公开了一种制造具有堆叠结构的半导体器件的改进方法。制备p沟道半导体衬底，并且在衬底的主表面上形成n沟道源极和漏极区域以及栅极电极以提供n沟道晶体管。侧壁由位于n沟道晶体管的栅电极的相对尺寸上的P型单晶硅形成，其中介于侧壁和栅电极之间的绝缘层。单晶层覆盖了n沟道晶体管的源极，漏极和栅极以及侧壁结构。存在于侧壁中的P型杂质扩散到单晶层中。

79. 发明授权

US4874718A Method for forming SOI film 失效
标题翻译： SOI薄膜的形成方法
公开(公告)号：US4874718A
公开(公告)日：1989-10-17
申请号：US225462
申请日：1988-07-28
申请人： Yasuo Inoue
发明人： Yasuo Inoue
IPC分类号： H01L21/20 , H01L21/263 , H01L21/762
CPC分类号： H01L21/2022 , H01L21/76243 , H01L21/76248 , Y10S148/085 , Y10S148/086
摘要： According to the present invention, an SOI film of a monocrystalline silicon film is formed by making solid phase epitaxial growth of an amorphous silicon layer formed on an oxide film. A through hole portion formed in the oxide film is formed in such a shape that an epitaxial growth region growing with the through hole portion as a nucleus covers the entire region of the amorphous silicon layer. After the SOI film is formed, oxygen ions are ioin-implanted into the through hole portion in the oxide film, to be embedded by an oxide film layer by thermal processing.
摘要翻译：根据本发明，通过使形成在氧化物膜上的非晶硅层的固相外延生长，形成单晶硅膜的SOI膜。形成在氧化膜中的通孔部分形成为以通孔部分为核的生长的外延生长区域覆盖非晶硅层的整个区域。在SOI膜形成之后，氧离子注入到氧化膜的通孔部分中，通过热处理被氧化膜层包埋。

80. 发明授权

US4870031A Method of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US4870031A
公开(公告)日：1989-09-26
申请号：US102655
申请日：1987-09-30
申请人： Kazuyuki Sugahara , Tadashi Nishimura , Shigeru Kusunoki , Yasuo Inoue
发明人： Kazuyuki Sugahara , Tadashi Nishimura , Shigeru Kusunoki , Yasuo Inoue
IPC分类号： H01L21/20 , H01L21/263 , H01L21/822 , H01L21/84 , H01L27/00
CPC分类号： H01L21/8221 , H01L21/2026 , Y10S117/904 , Y10S117/905 , Y10S148/09
摘要： In a method of manufacturing a semiconductor device comprising melting an amorphous or polycrystalline first semiconductor layer formed on the surface of a first dielectric layer by irradiating energy rays thereon, and converting the same into single crystals by the subsequent lowering of the temperature and forming a second dielectric layer and a second semiconductor layer on the first semiconductor layer. Energy rays are irradiated under the condition capable of melting the first semiconductor layer through the second semiconductor layer and the second dielectric layer and, after the completion of the conversion into single crystals, the second semiconductor layer and the second dielectric layer are eliminated through etching.
摘要翻译：在制造半导体器件的方法中，包括通过照射第一介电层的表面上的能量射线来熔化形成在第一介电层的表面上的非晶或多晶的第一半导体层，并且随后降低温度并将其转变为单晶电介质层和第一半导体层上的第二半导体层。在能够通过第二半导体层和第二电介质层熔化第一半导体层的条件下照射能量射线，并且在完成转换成单晶之后，通过蚀刻去除第二半导体层和第二电介质层。

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