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71. 发明授权

US5511020A Pseudo-nonvolatile memory incorporating data refresh operation 失效
标题翻译：结合数据刷新操作的伪非易失性存储器
公开(公告)号：US5511020A
公开(公告)日：1996-04-23
申请号：US157358
申请日：1993-11-23
申请人： Chenming Hu , Fu-Chieh Hsu
发明人： Chenming Hu , Fu-Chieh Hsu
IPC分类号： G11C16/10 , G11C16/34 , H01L27/115 , G11C13/00
CPC分类号： G11C16/3431 , G11C16/10 , G11C16/3418 , H01L27/115
摘要： A pseudo nonvolatile memory cell which may be operated in a pseudo-nonvolatile mode is achieved by utilizing a thin direct tunneling dielectric adjacent to the charge retaining region in a traditional nonvolatile memory cell such as an EPROM, EEPROM, flash EPROM, or flash EEPROM cell. The use of the direct tunneling dielectric allows for greatly enhanced write/erase cycles (exceeding 100 gigacycles) and reduced data write/erase time (under 1 microsecond). The direct tunneling dielectric also results in a reduced data retention period. Consequently, refresh circuitry is provided to maintain the non-volatility of the memory cell. A back-up battery is used to power the refresh circuitry when the system power is removed. This mode of operation provides an effectively nonvolatile memory system that is suitable for replacing traditional nonvolatile memory devices.
摘要翻译：可以以伪非易失性模式操作的伪非易失性存储单元通过在诸如EPROM，EEPROM，闪存EPROM或闪存EEPROM单元之类的传统非易失性存储单元中利用与电荷保持区相邻的薄的直接隧道电介质来实现。使用直接隧道电介质允许大大增强的写入/擦除周期（超过100个千兆字节）和减少的数据写入/擦除时间（1微秒以下）。直接隧道电介质也导致数据保留期减少。因此，提供刷新电路以维持存储单元的非易失性。当系统电源被移除时，备用电池用于为刷新电路供电。这种操作模式提供了一种非常适合替代传统的非易失性存储器件的非易失性存储器系统。

72. 发明授权

US5128731A Static random access memory cell using a P/N-MOS transistors 失效
标题翻译：使用P / N-MOS晶体管的静态随机存取存储单元
公开(公告)号：US5128731A
公开(公告)日：1992-07-07
申请号：US537848
申请日：1990-06-13
申请人： Chuen-Der Lien , Fu-Chieh Hsu , Jeong Y. Choi , Jeng-Jiun Yang
发明人： Chuen-Der Lien , Fu-Chieh Hsu , Jeong Y. Choi , Jeng-Jiun Yang
IPC分类号： H01L27/11
CPC分类号： H01L27/1104
摘要： A P/N-MOS transistor having source and drain of opposite semiconductor types is provided. One embodiment of the P/N-MOS transistor has turn-off characteristic similar to a PMOS transistor, and turn-on characteristic similar to a PMOS transistor connected in series with a p-n junction diode. An application of the P/N-MOS transistor is provided in a static random access memory (SRAM) cell. This SRAM cell has density advantage over SRAM cells using polysilicon PMOS transistors as active transistors.
摘要翻译：提供了具有相反半导体类型的源极和漏极的P / N-MOS晶体管。 P / N-MOS晶体管的一个实施例具有类似于PMOS晶体管的截止特性，以及类似于与p-n结二极管串联连接的PMOS晶体管的导通特性。在静态随机存取存储器（SRAM）单元中提供了P / N-MOS晶体管的应用。该SRAM单元相对于使用多晶硅PMOS晶体管作为有源晶体管的SRAM单元具有密度优势。

73. 发明授权

US4987090A Static ram cell with trench pull-down transistors and buried-layer ground plate 失效
标题翻译：具有沟槽下拉晶体管和埋层接地板的静态柱塞电池
公开(公告)号：US4987090A
公开(公告)日：1991-01-22
申请号：US385900
申请日：1989-07-25
申请人： Fu-Chieh Hsu , Chun-Chiu D. Wong , Ciaran P. Hanrahan
发明人： Fu-Chieh Hsu , Chun-Chiu D. Wong , Ciaran P. Hanrahan
IPC分类号： H01L21/74 , H01L21/8244 , H01L23/532 , H01L27/11
CPC分类号： H01L27/11 , H01L21/74 , H01L23/53271 , H01L27/1104 , H01L27/1112 , H01L2924/0002
摘要： Disclosed is a (4T-2R) SRAM cell and method which achieves a much reduced cell area through the combined use of vertical trench pull-down n-channel transistors and a buried-layer ground plate. The reduced cell area allows the fabrication of a higher density SRAM for a given set of lithographic rules. The cell structure also allows the implementation of a (6T) SRAM cell with non-self-aligned poly-silicon p-channel pull-up transistors without appreciably enlarging the cell area.
摘要翻译：公开了通过组合使用垂直沟槽下拉n沟道晶体管和掩埋层接地板来实现大大降低的单元面积的（4T-2R）SRAM单元和方法。减小的单元面积允许为给定的一组光刻规则制造更高密度的SRAM。电池结构还允许实现具有非自对准多硅p沟道上拉晶体管的（6T）SRAM单元，而不会明显地扩大单元面积。

74. 发明授权

US4876215A Method of making a static ram cell with trench pull-down transistors and buried-layer ground plate 失效
标题翻译：制造具有沟槽下拉晶体管和埋层接地板的静态压电池的方法
公开(公告)号：US4876215A
公开(公告)日：1989-10-24
申请号：US236209
申请日：1988-08-23
申请人： Fu-Chieh Hsu
发明人： Fu-Chieh Hsu
IPC分类号： H01L21/74 , H01L21/8244 , H01L23/532 , H01L27/11
CPC分类号： H01L27/11 , H01L21/74 , H01L23/53271 , H01L27/1104 , H01L27/1112 , H01L2924/0002 , Y10S257/903
摘要： Disclosed is a (4T-2R) SRAM cell and method which achieves a much reduced cell area through the combined use of vertical trench pull-down n-channel transistors and a buried-layer ground plate. The reduced cell area allows the fabrication of a higher density SRAM for a given set of lithographic rules. The cell structure also allows the implementation of a (6T) SRAM cell with non-self-aligned polysilicon p-channel pull-up transistors without appreciably enlarging the cell area.
摘要翻译：公开了通过组合使用垂直沟槽下拉n沟道晶体管和掩埋层接地板来实现大大降低的单元面积的（4T-2R）SRAM单元和方法。减小的单元面积允许为给定的一组光刻规则制造更高密度的SRAM。电池结构还允许实现具有非自对准多晶硅p沟道上拉晶体管的（6T）SRAM单元，而不会明显扩大单元面积。

75. 发明授权

US4794561A Static ram cell with trench pull-down transistors and buried-layer ground plate 失效
标题翻译：具有沟槽下拉晶体管和埋层接地板的静态柱塞电池
公开(公告)号：US4794561A
公开(公告)日：1988-12-27
申请号：US69168
申请日：1987-07-02
申请人： Fu-Chieh Hsu
发明人： Fu-Chieh Hsu
IPC分类号： H01L21/74 , H01L21/8244 , H01L23/532 , H01L27/11 , H01L29/78 , G11C11/40 , H01L21/70
CPC分类号： H01L27/11 , H01L21/74 , H01L23/53271 , H01L27/1104 , H01L27/1112 , H01L2924/0002 , Y10S257/903
摘要： Disclosed is a (4T-2R) SRAM cell and method which achieves a much reduced cell area through the combined use of vertical trench pull-down n-channel transistors and a buried-layer ground plate. The reduced cell area allows the fabrication of a higher density SRAM for a given set of lithographic rules. The cell structure also allows the implementation of a (6T) SRAM cell with non-self-aligned polysilicon p-channel pull-up transistors without appreciably enlarging the cell area.

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