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71. 发明授权

US08003428B2 Method of forming an inverted lens in a semiconductor structure 失效
标题翻译：在半导体结构中形成倒置透镜的方法
公开(公告)号：US08003428B2
公开(公告)日：2011-08-23
申请号：US12056736
申请日：2008-03-27
申请人： Terence Barrett , Jeffrey P. Gambino , Robert K. Leidy
发明人： Terence Barrett , Jeffrey P. Gambino , Robert K. Leidy
IPC分类号： H01L21/00
CPC分类号： H01L27/14627 , H01L27/14609 , H01L27/14621 , H01L27/14685
摘要： A flat-top convex-bottom lower lens is formed by first applying a positive tone photoresist over a silicon oxide layer and an optional metallic barrier layer thereupon in a back-end-of-line (BEOL) metallization structure. The positive tone photoresist is exposed under defocused illumination conditions and/or employing a half-tone mask so that a cross-sectional profile of the positive tone photoresist after exposure contains a continuous and smooth concave profile, which is transferred into the underlying silicon oxide layer to form a concave cavity therein. After removing the photoresist, the cavity is filled with a high refractive index material such as silicon nitride, and planarized to form a flat-top convex-bottom lower lens. Various aluminum metal structures, a color filter, and a convex-top flat-bottom upper lens are thereafter formed so that the upper lens and the lower lens constitute a composite lens system.
摘要翻译：通过在后端行（BEOL）金属化结构中首先在氧化硅层上施加正色调光致抗蚀剂和可选的金属阻挡层来形成平顶凸底底部透镜。正色调光致抗蚀剂在散焦照明条件下和/或使用半色调掩模下曝光，使得曝光后的正色调光致抗蚀剂的横截面轮廓包含连续且平滑的凹形轮廓，其被转移到下面的氧化硅层以在其中形成凹腔。在除去光致抗蚀剂之后，用诸如氮化硅的高折射率材料填充空腔，并且平坦化以形成平顶凸底底部下透镜。此后形成各种铝金属结构，滤色器和凸顶平底上透镜，使得上透镜和下透镜构成复合透镜系统。

72. 发明授权

US07958482B2 Stitched circuitry region boundary identification for stitched IC chip layout 有权
标题翻译：缝合IC芯片布局的缝合电路区域边界识别
公开(公告)号：US07958482B2
公开(公告)日：2011-06-07
申请号：US12112329
申请日：2008-04-30
申请人： Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Jeanne-Tania Sucharitaves
发明人： Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Jeanne-Tania Sucharitaves
IPC分类号： G06F17/50
CPC分类号： G03F7/70475
摘要： Stitched circuitry region boundary identification for a stitched IC chip layout is presented along with a related IC chip and design structure. One method includes obtaining a circuit design for an integrated circuit (IC) chip layout that exceeds a size of a photolithography tool field, wherein the IC chip layout includes a stitched circuitry region; and modifying the IC chip layout to include a boundary identification identifying a boundary of the stitched circuitry region at which stitching occurs, wherein the boundary identification takes the form of a negative space in the IC chip layout. One IC chip may include a plurality of stitched circuitry regions; and a boundary identification identifying a boundary between a pair of the stitched circuitry regions, wherein the boundary identification takes the form of a negative space in a layer of the IC chip.
摘要翻译：针对IC芯片布线的缝合电路区域边界识别以及相关的IC芯片和设计结构。一种方法包括获得超过光刻工具领域的尺寸的集成电路（IC）芯片布局的电路设计，其中IC芯片布局包括缝合电路区域; 以及修改IC芯片布局以包括标识发生缝合的缝合电路区域的边界的边界标识，其中边界识别在IC芯片布局中采取负空间的形式。一个IC芯片可以包括多个缝合电路区域; 以及识别一对缝合电路区域之间的边界的边界识别，其中边界识别在IC芯片的层中采取负空间的形式。

73. 发明申请

US20090242948A1 METHOD OF FORMING AN INVERTED LENS IN A SEMICONDUCTOR STRUCTURE 失效
标题翻译：在半导体结构中形成反射镜的方法
公开(公告)号：US20090242948A1
公开(公告)日：2009-10-01
申请号：US12056736
申请日：2008-03-27
申请人： Terence Barrett , Jeffrey P. Gambino , Robert K. Leidy
发明人： Terence Barrett , Jeffrey P. Gambino , Robert K. Leidy
IPC分类号： H01L31/0232 , H01L31/18
CPC分类号： H01L27/14627 , H01L27/14609 , H01L27/14621 , H01L27/14685
摘要： A flat-top convex-bottom lower lens is formed by first applying a positive tone photoresist over a silicon oxide layer and an optional metallic barrier layer thereupon in a back-end-of-line (BEOL) metallization structure. The positive tone photoresist is exposed under defocused illumination conditions and/or employing a half-tone mask so that a cross-sectional profile of the positive tone photoresist after exposure contains a continuous and smooth concave profile, which is transferred into the underlying silicon oxide layer to form a concave cavity therein. After removing the photoresist, the cavity is filled with a high refractive index material such as silicon nitride, and planarized to form a flat-top convex-bottom lower lens. Various aluminum metal structures, a color filter, and a convex-top flat-bottom upper lens are thereafter formed so that the upper lens and the lower lens constitute a composite lens system.
摘要翻译：通过在后端行（BEOL）金属化结构中首先在氧化硅层上施加正色调光致抗蚀剂和可选的金属阻挡层来形成平顶凸底底部透镜。正色调光致抗蚀剂在散焦照明条件下和/或使用半色调掩模下曝光，使得曝光后的正色调光致抗蚀剂的横截面轮廓包含连续且平滑的凹形轮廓，其被转移到下面的氧化硅层以在其中形成凹腔。在除去光致抗蚀剂之后，用诸如氮化硅的高折射率材料填充空腔，并且平坦化以形成平顶凸底底部下透镜。此后形成各种铝金属结构，滤色器和凸顶平底上透镜，使得上透镜和下透镜构成复合透镜系统。

74. 发明申请

US20080209382A1 STITCHED IC CHIP LAYOUT DESIGN STRUCTURE 失效
标题翻译： STITCHED IC芯片布局设计结构
公开(公告)号：US20080209382A1
公开(公告)日：2008-08-28
申请号：US11849461
申请日：2007-09-04
申请人： Timothy G. Dunham , Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Valarmathi C. Shanmugam
发明人： Timothy G. Dunham , Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Valarmathi C. Shanmugam
IPC分类号： G06F17/50
CPC分类号： G03F7/70475 , G03F7/70466 , G03F7/70691
摘要： Stitched integrated circuit (IC) chip layout design structures are disclosed. In one embodiment, a design structure embodied in a machine readable medium used in a design process includes: an integrated circuit (IC) chip exceeding a size of a photolithography tool field, the IC chip layout including: a plurality of stitched regions including at least one redundant stitched region or at least one unique stitched region; and for each stitched region: a boundary identification identifying a boundary of the stitched region at which stitching occurs.
摘要翻译：公开了拼接集成电路（IC）芯片布局设计结构。在一个实施例中，体现在设计过程中使用的机器可读介质中的设计结构包括：超过光刻工具领域尺寸的集成电路（IC）芯片，所述IC芯片布局包括：至少包括多个缝合区域一个冗余缝合区域或至少一个独特的缝合区域; 并且针对每个缝合区域：识别发生缝合的缝合区域的边界的边界标识。

75. 发明申请

US20080116537A1 CMOS IMAGER ARRAY WITH RECESSED DIELECTRIC 有权
标题翻译： CMOS图像阵列带有电介质
公开(公告)号：US20080116537A1
公开(公告)日：2008-05-22
申请号：US11560882
申请日：2006-11-17
申请人： James W. Adkisson , Jeffrey P. Gambino , Zhong-Xiang He , Mark D. Jaffe , Robert K. Leidy , Stephen E. Luce , Richard J. Rassel , Edmund J. Sprogis
发明人： James W. Adkisson , Jeffrey P. Gambino , Zhong-Xiang He , Mark D. Jaffe , Robert K. Leidy , Stephen E. Luce , Richard J. Rassel , Edmund J. Sprogis
IPC分类号： H01L27/146 , H01L21/04
CPC分类号： H01L27/14687 , H01L27/14618 , H01L27/14621 , H01L27/14627 , H01L27/14632 , H01L27/14685 , H01L2224/05001 , H01L2224/05008 , H01L2224/05124 , H01L2224/05548 , H01L2224/05569 , H01L2224/05647 , H01L2224/13 , H01L2924/00014
摘要： A CMOS image sensor array and method of fabrication. The CMOS imager sensor array comprises a substrate; an array of light receiving pixel structures formed above the substrate, the array having formed therein “m” levels of conductive structures, each level formed in a corresponding interlevel dielectric material layer; a dense logic wiring region formed adjacent to the array of light receiving pixel structures having “n” levels of conductive structures, each level formed in a corresponding interlevel dielectric material layer, where n>m. A microlens array having microlenses and color filters formed above the interlevel dielectric material layer, a microlens and respective color filter in alignment with a respective light receiving structure formed at a surface of the substrate. A top surface of the interlevel dielectric material layer beneath the microlens array is recessed from a top surface of the interlevel dielectric material layers of the dense logic wiring region.
摘要翻译： CMOS图像传感器阵列及其制造方法。 CMOS成像器传感器阵列包括衬底; 形成在衬底上方的光接收像素结构的阵列，阵列中形成有“m”级的导电结构，每个级形成在相应的层间介电材料层中; 与具有“n”级的导电结构的光接收像素结构的阵列相邻形成的密集的逻辑布线区域，每个层级形成在相应的层间电介质材料层中，其中n> m。具有形成在层间电介质材料层上方的微透镜和滤色器的微透镜阵列，与形成在衬底表面处的各个光接收结构对准的微透镜和相应的滤色器。微透镜阵列下面的层间介电材料层的顶表面从密集逻辑布线区域的层间介电材料层的顶表面凹陷。

76. 发明申请

US20080111159A1 IMAGE SENSOR INCLUDING SPATIALLY DIFFERENT ACTIVE AND DARK PIXEL INTERCONNECT PATTERNS 有权
标题翻译：图像传感器包括空间不同的主动和深色像素互连图案
公开(公告)号：US20080111159A1
公开(公告)日：2008-05-15
申请号：US11560019
申请日：2006-11-15
申请人： Jeffrey P. Gambino , Mark D. Jaffe , Robert K. Leidy , Richard J. Rassel
发明人： Jeffrey P. Gambino , Mark D. Jaffe , Robert K. Leidy , Richard J. Rassel
IPC分类号： H01L31/101 , H01L29/765 , H01L23/52 , H01L21/339
CPC分类号： H01L27/14636 , H01L27/14603 , H01L27/14621 , H01L27/14623 , H01L27/14627 , H01L27/14632 , H01L27/14645 , H01L27/14687
摘要： An interconnect layout, an image sensor including the interconnect layout and a method for fabricating the image sensor each use a first electrically active physical interconnect layout pattern within an active pixel region and a second electrically active physical interconnect layout pattern spatially different than the first electrically active physical interconnect layout pattern within a dark pixel region. The second electrically active physical interconnect layout pattern includes at least one electrically active interconnect layer interposed between a light shield layer and a photosensor region aligned therebeneath, thus generally providing a higher wiring density. The higher wiring density within the second layout pattern provides that that the image sensor may be fabricated with enhanced manufacturing efficiency and a reduction of metallization levels.
摘要翻译：互连布局，包括互连布局的图像传感器和用于制造图像传感器的方法各自使用有源像素区域内的第一电活性物理互连布局图案和在空间上不同于第一电活动的第二电活动物理互连布局图案物理互连布局图案在暗像素区域内。第二电活动物理互连布局图案包括插入在遮光层和在其下对准的光电传感器区域之间的至少一个电活动互连层，因此通常提供更高的布线密度。在第二布局图案中更高的布线密度提供了图像传感器可以制造成具有增强的制造效率和金属化水平的降低。

77. 发明授权

US07141836B1 Pixel sensor having doped isolation structure sidewall 有权
标题翻译：具有掺杂隔离结构侧壁的像素传感器
公开(公告)号：US07141836B1
公开(公告)日：2006-11-28
申请号：US10908885
申请日：2005-05-31
申请人： James W. Adkisson , Mark D. Jaffe , Robert K. Leidy
发明人： James W. Adkisson , Mark D. Jaffe , Robert K. Leidy
IPC分类号： H01L27/148
CPC分类号： H01L27/14603 , H01L27/1463 , H01L27/14643 , H01L27/14683
摘要： A novel pixel sensor structure formed on a substrate of a first conductivity type includes a photosensitive device of a second conductivity type and a surface pinning layer of the first conductivity type. An isolation structure is formed adjacent to the photosensitive device pinning layer. The isolation structure includes a dopant region comprising material of the first conductivity type selectively formed along a sidewall of the isolation structure that is adapted to electrically couple the surface pinning layer to the underlying substrate. The corresponding method for forming the dopant region selectively formed along the sidewall of the isolation structure comprises an out-diffusion process whereby dopant materials present in a doped material layer formed along selected portions in the isolation structure are driven into the underlying substrate during an anneal. Alternately, or in conjunction, an angled ion implantation of dopant material in the isolation structure sidewall may be performed by first fabricating a photoresist layer and reducing its size by removing a corner, or a corner portion thereof, which may block the angled implant material.
摘要翻译：形成在第一导电类型的衬底上的新型像素传感器结构包括第二导电类型的光敏器件和第一导电类型的表面钉扎层。在光敏器件钉扎层附近形成隔离结构。隔离结构包括掺杂区域，该掺杂剂区域包括沿着隔离结构的侧壁选择性地形成的第一导电类型的材料，其适于将表面钉扎层电耦合到下面的衬底。用于形成沿着隔离结构的侧壁选择性地形成的掺杂剂区域的相应方法包括外扩散工艺，由此在退火期间，存在于沿隔离结构中的选定部分形成的掺杂材料层中的掺杂剂材料被驱动到下面的衬底中。替代地或结合地，隔离结构侧壁中的掺杂剂材料的成角度的离子注入可以通过首先制造光致抗蚀剂层并通过去除可能阻挡成角度的植入材料的角部或其角部来减小其尺寸来执行。

78. 发明授权

US06350548B1 Nested overlay measurement target 有权
标题翻译：嵌套覆盖测量目标
公开(公告)号：US06350548B1
公开(公告)日：2002-02-26
申请号：US09526661
申请日：2000-03-15
申请人： Robert K. Leidy , Debra L. Meunier
发明人： Robert K. Leidy , Debra L. Meunier
IPC分类号： G03F900
CPC分类号： G03F7/70633 , H01L22/34 , Y10S438/975
摘要： A mask overlay measurement target includes nested boxes on three levels or has adjacent boxes sharing a common side, saving substantial area. The nested overlay measurement target also provides savings in measurement time since multiple overlay combinations can be measured at once. The nested target provides more level-to-level overlay information than has been available with standard box-in-box targets. The nested boxes are also used on a single level to provide area savings for stepper field placement metrology.
摘要翻译：掩模覆盖测量目标包括三个级别的嵌套框架或具有共享共同侧面的相邻框架，从而节省大量面积。嵌套覆盖测量目标还可以节省测量时间，因为可以一次测量多个叠加组合。嵌套的目标提供了比标准框中的目标可用的更多的级别到级别的覆盖信息。嵌套盒也用于单个级别，以提供步进场放置度量的面积节省。

79. 发明授权

US08618588B2 Anti-blooming pixel sensor cell with active neutral density filter, methods of manufacture, and design structure 有权
标题翻译：具有活性中性密度滤光片的防晕像素传感器单元，制造方法和设计结构
公开(公告)号：US08618588B2
公开(公告)日：2013-12-31
申请号：US12915888
申请日：2010-10-29
申请人： Kristin M. Ackerson , Jeffrey P. Gambino , Mark D. Jaffe , Robert K. Leidy , Richard J. Rassel , Robert M. Rassel
发明人： Kristin M. Ackerson , Jeffrey P. Gambino , Mark D. Jaffe , Robert K. Leidy , Richard J. Rassel , Robert M. Rassel
IPC分类号： H01L31/062 , H01L31/113
CPC分类号： H04N5/238 , H01L27/14623 , H01L27/14625 , H01L27/14685 , H04N5/3591
摘要： A method of preventing blooming in a pixel array includes affecting an amount of light that impinges on a photoelectric conversion element by adjusting a transmissivity of an electrochromic element based on an output of the photoelectric conversion element.
摘要翻译：防止像素阵列中的起霜的方法包括通过基于光电转换元件的输出调节电致变色元件的透射率来影响照射到光电转换元件上的光量。

80. 发明授权

US08592244B2 Pixel sensor cells and methods of manufacturing 有权
标题翻译：像素传感器单元和制造方法
公开(公告)号：US08592244B2
公开(公告)日：2013-11-26
申请号：US13189961
申请日：2011-07-25
申请人： Jeffrey P. Gambino , Robert K. Leidy , Mark D. Levy
发明人： Jeffrey P. Gambino , Robert K. Leidy , Mark D. Levy
IPC分类号： H01L21/00
CPC分类号： H01L27/14623 , H01L27/14636 , H01L27/14687
摘要： Pixel sensor cells with an opaque mask layer and methods of manufacturing are provided. The method includes forming a transparent layer over at least one active pixel and at least one dark pixel of a pixel sensor cell. The method further includes forming an opaque region in the transparent layer over the at least one dark pixel.
摘要翻译：提供了具有不透明掩模层的像素传感器单元和制造方法。该方法包括在像素传感器单元的至少一个有源像素和至少一个暗像素的上方形成透明层。该方法还包括在至少一个暗像素上的透明层中形成不透明区域。

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