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71. 发明申请

US20060055446A1 Electronic circuits utilizing normally-on junction field-effect transistor 审中-公开
标题翻译：采用正常接合场效应晶体管的电子电路
公开(公告)号：US20060055446A1
公开(公告)日：2006-03-16
申请号：US11220556
申请日：2005-09-08
申请人： Liang-Pin Tai , Jing-Meng Liu , Hung-Der Su
发明人： Liang-Pin Tai , Jing-Meng Liu , Hung-Der Su
IPC分类号： H03K17/687
CPC分类号： H02M3/158 , H02M3/155 , H03K17/063 , H03K17/6871 , H03K17/693 , H03K2017/6875
摘要： Electronic circuits use low-cost depletion-mode JFET to serve as power switch. Since depletion-mode JFET has smaller conductive resistance and is majority carrier device, the energy loss is less when current flows through the depletion-mode JFET, and faster switching speed is obtained, thereby enhancing the efficiency of the electronic circuits.
摘要翻译：电子电路使用低成本耗尽型JFET作为电源开关。由于耗尽型JFET具有较小的导电电阻并且是多数载流子器件，所以当电流流过耗尽型JFET时能量损失较小，并且获得更快的开关速度，从而提高电子电路的效率。

72. 发明申请

US20050275375A1 Battery charger using a depletion mode transistor to serve as a current source 审中-公开
标题翻译：电池充电器使用耗尽型晶体管作为电流源
公开(公告)号：US20050275375A1
公开(公告)日：2005-12-15
申请号：US11150191
申请日：2005-06-13
申请人： Jing-Meng Liu , Chung-Lung Pai , Hung-Der Su
发明人： Jing-Meng Liu , Chung-Lung Pai , Hung-Der Su
IPC分类号： H02J7/00
CPC分类号： H02J7/0052
摘要： In a battery charger using a depletion mode transistor to serve as a current source, the depletion mode transistor is self-biased for generating a charging current to charge a battery, thereby requesting no additional control circuit to control the depletion mode transistor, reducing the circuit size, and lowering the cost.
摘要翻译：在使用耗尽型晶体管作为电流源的电池充电器中，耗尽型晶体管是自偏压的，用于产生充电电流以对电池充电，从而不需要额外的控制电路来控制耗尽型晶体管，从而减少电路尺寸，降低成本。

73. 发明授权

US06828198B2 System-on-chip (SOC) solutions with multiple devices by multiple poly gate trimming process 失效
公开(公告)号：US06828198B2
公开(公告)日：2004-12-07
申请号：US10392120
申请日：2003-03-19
申请人： Hung-Der Su , Shien-Yang Wu , Yung-Shun Chen , Tung-Heng Shie , Yuan-Hung Chiu
发明人： Hung-Der Su , Shien-Yang Wu , Yung-Shun Chen , Tung-Heng Shie , Yuan-Hung Chiu
IPC分类号： H01L21336
CPC分类号： H01L21/823456 , H01L21/28123 , H01L21/32139
摘要： A method of forming gate electrode layer portions having differing widths comprising the following steps. A structure having a gate electrode layer and a hard mask layer thereover and including two or more active areas is provided. The hard mask layer is patterned to form two or more respective hard mask layer portions within the two or more active areas. One or more of the two or more respective hard mask layer portions is/are selectively trimmed to reduce its/their width to a second width leaving at least one the respective hard mask layer portions untrimmed. The gate electrode layer is then patterned.

74. 发明授权

US06582995B2 Method for fabricating a shallow ion implanted microelectronic structure 有权
标题翻译：制造浅离子注入微电子结构的方法
公开(公告)号：US06582995B2
公开(公告)日：2003-06-24
申请号：US09903125
申请日：2001-07-11
申请人： Ting-Hua Hsieh , Hung-Der Su , Carlos H. Diaz
发明人： Ting-Hua Hsieh , Hung-Der Su , Carlos H. Diaz
IPC分类号： H01L21335
CPC分类号： H01L29/6659 , H01L21/823814 , H01L29/665 , H01L29/6656 , H01L29/7833
摘要： Within a method for fabricating a microelectronic fabrication comprising a topographic microelectronic structure formed over a substrate, there is implanted, while employing a first ion implant method and while masking a portion of the substrate adjacent the topographic microelectronic structure but not masking the topographic microelectronic structure, the topographic microelectronic structure to form an ion implanted topographic microelectronic structure without implanting the substrate. There is also implanted, while employing a second ion implant method, the portion of the substrate adjacent the topographic microelectronic substrate to form therein an ion implant structure. The method is particularly useful for fabricating source/drain regions with shallow junctions within field effect transistor (FET) devices.
摘要翻译：在制造包括形成在衬底上的形貌微电子结构的微电子制造的方法中，注入植入，同时采用第一离子注入方法，同时掩盖与形貌微电子结构相邻但不掩盖地形微电子结构的衬底的一部分，地形微电子结构，以形成离子注入的地形微电子结构，而不会植入衬底。在采用第二离子注入方法的同时，植入衬底的部分与形貌微电子衬底相邻以在其中形成离子注入结构。该方法对于在场效应晶体管（FET）器件中制造具有浅结的源极/漏极区域特别有用。

75. 发明授权

US09627524B2 High voltage metal oxide semiconductor device and method for making same 有权
公开(公告)号：US09627524B2
公开(公告)日：2017-04-18
申请号：US12715501
申请日：2010-03-02
申请人： Tsung-Yi Huang , Huan-Ping Chu , Ching-Yao Yang , Hung-Der Su
发明人： Tsung-Yi Huang , Huan-Ping Chu , Ching-Yao Yang , Hung-Der Su
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/78 , H01L29/0847 , H01L29/1045 , H01L29/7833 , H01L29/7835
摘要： The present invention discloses a high voltage metal oxide semiconductor (HVMOS) device and a method for making same. The high voltage metal oxide semiconductor device comprises: a substrate; a gate structure on the substrate; a well in the substrate, the well defining a device region from top view; a first drift region in the well; a source in the well; a drain in the first drift region, the drain being separated from the gate structure by a part of the first drift region; and a P-type dopant region not covering all the device region, wherein the P-type dopant region is formed by implanting a P-type dopant for enhancing the breakdown voltage of the HVMOS device (for N-type HVMOS device) or reducing the ON resistance of the HVMOS device (for P-type HVMOS device).

76. 发明授权

US09590049B2 Semiconductor composite film with heterojunction and manufacturing method thereof 有权
标题翻译：具有异质结的半导体复合膜及其制造方法
公开(公告)号：US09590049B2
公开(公告)日：2017-03-07
申请号：US14966818
申请日：2015-12-11
申请人： Hung-Der Su , Chien-Wei Chiu , Tsung-Yi Huang
发明人： Hung-Der Su , Chien-Wei Chiu , Tsung-Yi Huang
IPC分类号： H01L21/336 , H01L29/205 , H01L29/78 , H01L21/02 , H01L21/306 , H01L29/20 , H01L29/12
CPC分类号： H01L29/205 , H01L21/02378 , H01L21/0242 , H01L21/0254 , H01L21/02664 , H01L21/30612 , H01L29/12 , H01L29/2003 , H01L29/7845 , H01L29/7849
摘要： The present invention discloses a semiconductor composite film with a heterojunction and a manufacturing method thereof. The semiconductor composite film includes: a semiconductor substrate; and a semiconductor epitaxial layer, which is formed on the semiconductor substrate, and it has a first surface and a second surface opposite to each other, wherein the heterojunction is formed between the first surface and the semiconductor substrate, and wherein the semiconductor epitaxial layer further includes at least one recess, which is formed by etching the semiconductor epitaxial layer from the second surface toward the first surface. The recess is for mitigating a strain in the semiconductor composite film.
摘要翻译：本发明公开了一种具有异质结的半导体复合膜及其制造方法。半导体复合膜包括：半导体衬底; 以及半导体外延层，其形成在所述半导体基板上，并且具有彼此相对的第一表面和第二表面，其中所述异质结形成在所述第一表面和所述半导体基板之间，并且其中所述半导体外延层进一步包括通过从第二表面朝向第一表面蚀刻半导体外延层而形成的至少一个凹部。该凹槽用于减轻半导体复合膜中的应变。

77. 发明授权

US09484437B2 Lateral double diffused metal oxide semiconductor device and manufacturing method thereof 有权
标题翻译：横向双扩散金属氧化物半导体器件及其制造方法
公开(公告)号：US09484437B2
公开(公告)日：2016-11-01
申请号：US15018672
申请日：2016-02-08
申请人： Tsung-Yi Huang , Ching-Yao Yang , Wen-Yi Liao , Hung-Der Su , Kuo-Cheng Chang
发明人： Tsung-Yi Huang , Ching-Yao Yang , Wen-Yi Liao , Hung-Der Su , Kuo-Cheng Chang
IPC分类号： H01L29/78 , H01L29/66 , H01L29/06 , H01L21/762 , H01L29/08 , H01L29/10
CPC分类号： H01L29/66681 , H01L21/76202 , H01L21/76224 , H01L21/76229 , H01L29/0649 , H01L29/0852 , H01L29/1095 , H01L29/6681 , H01L29/7816
摘要： The present invention discloses a lateral double diffused metal oxide semiconductor (LDMOS) device and a manufacturing method thereof. The LDMOS device includes: drift region, an isolation oxide region, a first oxide region, a second oxide region, a gate, a body region, a source, and a drain. The isolation oxide region, the first oxide region, and the second oxide region have an isolation thickness, a first thickness, and a second thickness respectively, wherein the second thickness is less than the first thickness. The present invention can reduce a conduction resistance without decreasing a breakdown voltage of the LDMOS device by the first oxidation region and the second oxidation region.
摘要翻译：本发明公开了一种横向双扩散金属氧化物半导体（LDMOS）器件及其制造方法。 LDMOS器件包括：漂移区，隔离氧化区，第一氧化物区，第二氧化物区，栅极，体区，源极和漏极。隔离氧化物区域，第一氧化物区域和第二氧化物区域分别具有隔离厚度，第一厚度和第二厚度，其中第二厚度小于第一厚度。本发明可以降低导通电阻而不降低第一氧化区和第二氧化区的LDMOS器件的击穿电压。

78. 发明申请

US20160099320A1 SEMICONDUCTOR COMPOSITE FILM WITH HETEROJUNCTION AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：具有异质性的半导体复合膜及其制造方法
公开(公告)号：US20160099320A1
公开(公告)日：2016-04-07
申请号：US14966818
申请日：2015-12-11
申请人： Hung-Der Su , Chien-Wei Chiu , Tsung-Yi Huang
发明人： Hung-Der Su , Chien-Wei Chiu , Tsung-Yi Huang
IPC分类号： H01L29/205 , H01L21/02 , H01L21/306 , H01L29/20
CPC分类号： H01L29/205 , H01L21/02378 , H01L21/0242 , H01L21/0254 , H01L21/02664 , H01L21/30612 , H01L29/12 , H01L29/2003 , H01L29/7845 , H01L29/7849
摘要： The present invention discloses a semiconductor composite film with a heterojunction and a manufacturing method thereof. The semiconductor composite film includes: a semiconductor substrate; and a semiconductor epitaxial layer, which is formed on the semiconductor substrate, and it has a first surface and a second surface opposite to each other, wherein the heterojunction is formed between the first surface and the semiconductor substrate, and wherein the semiconductor epitaxial layer further includes at least one recess, which is formed by etching the semiconductor epitaxial layer from the second surface toward the first surface. The recess is for mitigating a strain in the semiconductor composite film.
摘要翻译：本发明公开了一种具有异质结的半导体复合膜及其制造方法。半导体复合膜包括：半导体衬底; 以及半导体外延层，其形成在所述半导体基板上，并且具有彼此相对的第一表面和第二表面，其中所述异质结形成在所述第一表面和所述半导体基板之间，并且其中所述半导体外延层进一步包括通过从第二表面朝向第一表面蚀刻半导体外延层而形成的至少一个凹部。该凹槽用于减轻半导体复合膜中的应变。

79. 发明授权

US09287394B2 Lateral double diffused metal oxide semiconductor device and manufacturing method thereof 有权
公开(公告)号：US09287394B2
公开(公告)日：2016-03-15
申请号：US14510600
申请日：2014-10-09
申请人： Tsung-Yi Huang , Ching-Yao Yang , Wen-Yi Liao , Hung-Der Su , Kuo-Cheng Chang
发明人： Tsung-Yi Huang , Ching-Yao Yang , Wen-Yi Liao , Hung-Der Su , Kuo-Cheng Chang
IPC分类号： H01L29/78 , H01L29/06 , H01L29/66 , H01L21/762
CPC分类号： H01L29/66681 , H01L21/76202 , H01L21/76224 , H01L21/76229 , H01L29/0649 , H01L29/0852 , H01L29/1095 , H01L29/6681 , H01L29/7816
摘要： The present invention discloses a lateral double diffused metal oxide semiconductor (LDMOS) device and a manufacturing method thereof. The LDMOS device includes: drift region, an isolation oxide region, a first oxide region, a second oxide region, a gate, a body region, a source, and a drain. The isolation oxide region, the first oxide region, and the second oxide region have an isolation thickness, a first thickness, and a second thickness respectively, wherein the second thickness is less than the first thickness. The present invention can reduce a conduction resistance without decreasing a breakdown voltage of the LDMOS device by the first oxidation region and the second oxidation region.

80. 发明申请

US20150137232A1 LATERAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：横向双向扩散金属氧化物半导体器件及其制造方法
公开(公告)号：US20150137232A1
公开(公告)日：2015-05-21
申请号：US14510600
申请日：2014-10-09
申请人： Tsung-Yi Huang , Ching-Yao Yang , Wen-Yi Liao , Hung-Der Su , Kuo-Cheng Chang
发明人： Tsung-Yi Huang , Ching-Yao Yang , Wen-Yi Liao , Hung-Der Su , Kuo-Cheng Chang
IPC分类号： H01L29/78 , H01L29/66 , H01L21/762 , H01L29/06
CPC分类号： H01L29/66681 , H01L21/76202 , H01L21/76224 , H01L21/76229 , H01L29/0649 , H01L29/0852 , H01L29/1095 , H01L29/6681 , H01L29/7816
摘要： The present invention discloses a lateral double diffused metal oxide semiconductor (LDMOS) device and a manufacturing method thereof. The LDMOS device includes: drift region, an isolation oxide region, a first oxide region, a second oxide region, a gate, a body region, a source, and a drain. The isolation oxide region, the first oxide region, and the second oxide region have an isolation thickness, a first thickness, and a second thickness respectively, wherein the second thickness is less than the first thickness. The present invention can reduce a conduction resistance without decreasing a breakdown voltage of the LDMOS device by the first oxidation region and the second oxidation region.
摘要翻译：本发明公开了一种横向双扩散金属氧化物半导体（LDMOS）器件及其制造方法。 LDMOS器件包括：漂移区，隔离氧化区，第一氧化物区，第二氧化物区，栅极，体区，源极和漏极。隔离氧化物区域，第一氧化物区域和第二氧化物区域分别具有隔离厚度，第一厚度和第二厚度，其中第二厚度小于第一厚度。本发明可以降低导通电阻而不降低第一氧化区和第二氧化区的LDMOS器件的击穿电压。

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