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71. 发明授权

US08196086B2 Granular channel width for power optimization 有权
标题翻译：颗粒通道宽度进行功率优化
公开(公告)号：US08196086B2
公开(公告)日：2012-06-05
申请号：US12840535
申请日：2010-07-21
申请人： Jeffrey S. Brown , Jonathan W. Byrn , Mark F. Turner
发明人： Jeffrey S. Brown , Jonathan W. Byrn , Mark F. Turner
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/78
摘要： A storage medium recording a cell library having one or more cells that may be readable by a computer and may be used by the computer to design an integrated circuit. The one or more cells may have a physical dimension parameter and a channel width parameter. The physical dimension parameter may be a footprint of the one or more cells. The channel width parameter may have a minimum driver size and a maximum driver size. The channel width parameter may define a range within which a tool varies the channel width between the maximum driver size and the minimum driver size during a design flow of the integrated circuit based upon one or more power criteria without changing the footprint.
摘要翻译：记录具有一个或多个可由计算机读取的单元的单元库的存储介质，并可由计算机用于设计集成电路。一个或多个单元可以具有物理尺寸参数和通道宽度参数。物理尺寸参数可以是一个或多个单元格的占位面积。通道宽度参数可能具有最小驱动程序大小和最大驱动程序大小。通道宽度参数可以定义范围，在该范围内，工具在集成电路的设计流程期间基于一个或多个功率准则改变最大驱动器尺寸和最小驱动器尺寸之间的通道宽度，而不改变占用面积。

72. 发明申请

US20120008450A1 FLEXIBLE MEMORY ARCHITECTURE FOR STATIC POWER REDUCTION AND METHOD OF IMPLEMENTING THE SAME IN AN INTEGRATED CIRCUIT 审中-公开
标题翻译：用于静电功率的灵活存储器结构及其在集成电路中的实现方法
公开(公告)号：US20120008450A1
公开(公告)日：2012-01-12
申请号：US12831439
申请日：2010-07-07
申请人： Mark F. Turner , Jeffrey S. Brown , Paul J. Dorweiler
发明人： Mark F. Turner , Jeffrey S. Brown , Paul J. Dorweiler
IPC分类号： G11C8/00 , G06F17/50
CPC分类号： G11C8/18 , G11C7/1006 , G11C7/1012
摘要： A memory for an integrated circuit, a method of designing a memory and an integrated circuit manufactured by the method. In one embodiment, the memory includes: (1) one of: (1a) at least one data input register block and at least one bit enable input register block and (1b) at least one data and bit enable merging block and at least one merged data register block, (2) one of: (2a) at least one address input register block and at least one binary to one-hot address decode block and (2b) at least one binary to one-hot address decode block and at least one one-hot address register block and (3) a memory array, at least one of the blocks having a timing selected to match at least some timing margins outside of the memory.
摘要翻译：用于集成电路的存储器，设计存储器的方法和通过该方法制造的集成电路。在一个实施例中，存储器包括：（1）以下之一：（1a）至少一个数据输入寄存器块和至少一个位使能输入寄存器块，和（1b）至少一个数据和位使能合并块和至少一个合并数据寄存器块，（2）以下之一：（2a）至少一个地址输入寄存器块和至少一个二进制到一个热地址解码块，以及（2b）至少一个二进制到一个热地址解码块至少一个热地址寄存器块和（3）存储器阵列，所述块中的至少一个具有被选择为匹配存储器外部的至少一些定时裕度的定时。

73. 发明授权

US07966592B2 Dual path static timing analysis 有权
标题翻译：双路静态时序分析
公开(公告)号：US07966592B2
公开(公告)日：2011-06-21
申请号：US12206048
申请日：2008-09-08
申请人： Jeffrey S. Brown , Jonathan W. Byrn , Mark F. Turner
发明人： Jeffrey S. Brown , Jonathan W. Byrn , Mark F. Turner
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A method to analyze timing in a circuit, generally including (A) simulating reception of an input signal and a clock signal at a first flip-flop, wherein (i) the input signal has a latest transition, (ii) the input signal arrives through a first path and (iii) the clock signal has an active edge, (B) calculating a value of a time difference between the latest transition and the active edge, (C) calculating a delay between the active edge and the latest transition appearing in an output signal, wherein (i) the delay is based on a model responding to the value, (ii) the model characterizes a clock-to-output delay as a function of the time difference and (iii) the characterization covering a range of values, (D) calculating an arrival time of the latest transition at a second flip-flop through a second signal path and (E) storing the arrival time in a recording medium.
摘要翻译：一种分析电路中的定时的方法，通常包括（A）模拟第一触发器处的输入信号和时钟信号的接收，其中（i）输入信号具有最新的转换，（ii）输入信号到达通过第一路径和（iii）时钟信号具有有效边缘，（B）计算最新转换和有效边沿之间的时间差值，（C）计算出当前边缘与最近转换出现之间的延迟在输出信号中，其中（i）所述延迟基于响应于该值的模型，（ii）模型将时钟到输出延迟表征为时间差的函数，以及（iii）表征范围（D）通过第二信号路径计算第二触发器的最新转换的到达时间，以及（E）将到达时间存储在记录介质中。

74. 发明授权

US07787325B2 Row decode driver gradient design in a memory device 有权
标题翻译：行解码驱动程序渐变设计在内存设备中
公开(公告)号：US07787325B2
公开(公告)日：2010-08-31
申请号：US12120611
申请日：2008-05-14
申请人： Jeffrey S. Brown , Jonathan W. Byrn , Mark F. Turner
发明人： Jeffrey S. Brown , Jonathan W. Byrn , Mark F. Turner
IPC分类号： G11C8/00
CPC分类号： G11C8/10
摘要： A memory device using a plurality of enhanced row decode drivers for activating wordlines in a memory array is disclosed. Circuit design attributes of the enhanced row decode drivers are varied as a function of proximity to a source of a row address signal applied to each decode driver. The circuit variations are operable to reduce the leakage power of the driver by degrading performance thereof while maintaining required worst case timing. The worst case timing being defined by the timing and performance requirements for the most distant of the row decode driver circuits relative to the source of the applied row address signals.
摘要翻译：公开了一种使用多个用于激活存储器阵列中的字线的增强行解码驱动器的存储器件。增强行解码驱动器的电路设计属性作为与施加到每个解码驱动器的行地址信号的源的接近度的函数而变化。电路变化可操作以通过降低其性能而降低驾驶员的泄漏功率，同时保持所需的最差情况时机。最差的情况定时由相对于应用的行地址信号的源的最远的行解码驱动器电路的定时和性能要求定义。

75. 发明授权

US07707720B2 Method for forming a corrosion-resistant impeller for a magnetic-drive centrifugal pump 有权
标题翻译：用于形成用于磁驱离心泵的耐腐蚀叶轮的方法
公开(公告)号：US07707720B2
公开(公告)日：2010-05-04
申请号：US10918675
申请日：2004-08-13
申请人： Manfred P. Klein , Jeffrey S. Brown , Scott A. McAloon
发明人： Manfred P. Klein , Jeffrey S. Brown , Scott A. McAloon
IPC分类号： B23P15/00
CPC分类号： F04D29/026 , F04D13/026 , F04D13/027 , F05D2260/95 , F05D2300/10 , F05D2300/43 , F05D2300/615 , H02K5/128 , H02K7/14 , H02K2005/1287 , Y10T29/49229 , Y10T29/49236 , Y10T29/49243
摘要： A method for forming an impeller for a pump provides a reliable protective barrier that prevents or eliminates the ingress of pumped fluid that might otherwise attack the magnetic assembly of the impeller. An inner barrier is hermetically connected to an internal impeller section at one or more seams to cover at least part of a first magnetic assembly. Filler is introduced into a spatial volume of the first magnet assembly associated with the internal impeller section. The remainder of an impeller is molded over or in association with the internal impeller section to form the impeller with the inner barrier and an outer barrier overlying the inner barrier for protection of the first magnet assembly from the pumped fluid.
摘要翻译：用于形成用于泵的叶轮的方法提供了可靠的保护屏障，其防止或消除了可能会攻击叶轮的磁性组件的泵送流体的进入。内部阻挡件以一个或多个接缝气密地连接到内部叶轮部分以覆盖第一磁性组件的至少一部分。将填料引入到与内部叶轮部分相关联的第一磁体组件的空间体积中。叶轮的其余部分被模制在内部叶轮部分上或与内部叶轮部分相关联以形成具有内部阻挡件的叶轮和覆盖内部阻挡件的外部阻挡件，用于保护第一磁体组件免受泵送的流体的影响。

76. 发明授权

US07676716B2 Testable tristate bus keeper 有权
标题翻译：可测三通巴士管理员
公开(公告)号：US07676716B2
公开(公告)日：2010-03-09
申请号：US12169216
申请日：2008-07-08
申请人： Jeffrey S. Brown , Mark F. Turner , Marek J. Marasch
发明人： Jeffrey S. Brown , Mark F. Turner , Marek J. Marasch
IPC分类号： G01R31/28 , H03K3/289
CPC分类号： G01R31/318544
摘要： A method of testing a tristate element by applying a given value to the tristate, applying an opposite value to a keeper element connected at an output of the tristate, capturing a first value at a downstream position of the tristate, evaluating a second value at the output of the tristate using the first value, comparing the second value to the opposite value, and producing a failure code for the tristate when the second value is not equal to the opposite value. Then, applying the opposite value to the tristate, applying the given value to the keeper element, capturing the first value, evaluating the second value using the first value, comparing the second value to the given value, and producing a failure code for the tristate when the second value is not equal to the given value. A passing code for the tristate is produced when a failure code has not been produced.
摘要翻译：一种通过向三态施加给定值来测试三态元件的方法，对连接在三态输出端的保持器元件施加相反的值，在三态的下游位置处捕获第一值，评估第三值的第二值使用第一值的三态输出，将第二值与相反值进行比较，并且当第二值不等于相反值时，产生三态的故障代码。然后，将相反的值应用于三态，将给定值应用于保持器元件，捕获第一值，使用第一值来评估第二值，将第二值与给定值进行比较，并产生三态的故障代码当第二个值不等于给定值时。当没有产生故障代码时，产生三态的传递代码。

77. 发明授权

US07525864B2 Memory data inversion architecture for minimizing power consumption 失效
标题翻译：用于最小化功耗的存储器数据反转架构
公开(公告)号：US07525864B2
公开(公告)日：2009-04-28
申请号：US11696870
申请日：2007-04-05
申请人： Jeffrey S. Brown
发明人： Jeffrey S. Brown
IPC分类号： G11C5/14
CPC分类号： G11C7/1006 , G11C7/1012 , G11C7/1051 , G11C7/1069 , G11C2211/5647
摘要： A method for conserving power in a device is disclosed. The method generally includes the steps of (A) storing a plurality of data items in a plurality of bit cells in the device such that a majority of the bit cells holding the data items have a first logic state, wherein reading one of the bit cells having the first logic state consumes less power than reading one of the bit cells having a second logic state; (B) generating a polarity signal by analyzing the data items, the polarity signal indicating that the data items are stored in one of (i) an inverted condition and (ii) a non-inverted condition relative to a normal condition; and (C) driving at least one of the data items onto an external interface of the device in the normal condition during a read operation based on the polarity signal.
摘要翻译：公开了一种节省设备功率的方法。该方法通常包括以下步骤：（A）将多个数据项存储在设备中的多个比特单元中，使得保存数据项的大部分比特单元具有第一逻辑状态，其中，读取比特单元之一具有第一逻辑状态的功率比读取具有第二逻辑状态的位单元之一消耗更少的功率; （B）通过分析数据项产生极性信号，指示数据项存储在相对于正常条件的（i）反转状态和（ii）非反相状态之一的极性信号中; 以及（C）基于所述极性信号，在读取操作期间，将所述数据项中的至少一个数据项驱动到所述装置的外部接口处于正常状态。

78. 发明授权

US06997688B1 Secondary containment for a magnetic-drive centrifugal pump 有权
标题翻译：用于磁驱离心泵的二次容纳
公开(公告)号：US06997688B1
公开(公告)日：2006-02-14
申请号：US10383089
申请日：2003-03-06
申请人： Manfred P. Klein , Brian C. Ward , Jeffrey S. Brown , Scott A. McAloon , Peter E. Phelps
发明人： Manfred P. Klein , Brian C. Ward , Jeffrey S. Brown , Scott A. McAloon , Peter E. Phelps
IPC分类号： F04B17/00
CPC分类号： F04D29/126 , F04D13/026 , F05D2260/6022
摘要： A centrifugal pump includes a housing having a housing cavity, an inlet, and an outlet. A pump shaft is located within the housing cavity. A radial bearing coaxially surrounds the pump shaft. The shaft and the radial bearing are rotatable with respect to one another. An impeller is positioned to receive a fluid from the inlet and to exhaust the fluid to the outlet. The impeller has a first magnet assembly. A rotor has a second magnet assembly spaced apart from the first magnet assembly. A primary container is interposed between the impeller and the rotor. The primary container is arranged to contain a pumped fluid. A drive shaft is associated with the rotor for rotating the rotor. A secondary container contains the pumped fluid if the primary container leaks. The secondary container supports a generally dry-running seal (e.g., non-lubricated seal) associated with the drive shaft. The seal is disposed axially from the primary container and has a stationary portion and a rotating portion.
摘要翻译：离心泵包括具有壳体腔，入口和出口的壳体。泵轴位于壳体腔内。径向轴承同轴地围绕泵轴。轴和径向轴承可相对于彼此旋转。叶轮定位成从入口接收流体并将流体排出到出口。叶轮具有第一磁体组件。转子具有与第一磁体组件间隔开的第二磁体组件。主容器介于叶轮和转子之间。主容器布置成容纳泵送的流体。驱动轴与用于旋转转子的转子相关联。如果主容器泄漏，则辅助容器包含泵送的流体。次级容器支撑与驱动轴相关联的通常干运行的密封件（例如，非润滑密封件）。密封件从主容器轴向设置并具有固定部分和旋转部分。

79. 发明授权

US06980481B1 Address transition detect control circuit for self timed asynchronous memories 失效
标题翻译：用于自定时异步存储器的地址转换检测控制电路
公开(公告)号：US06980481B1
公开(公告)日：2005-12-27
申请号：US10028582
申请日：2001-12-20
申请人： Jeffrey S. Brown
发明人： Jeffrey S. Brown
IPC分类号： G11C7/00 , G11C7/06 , G11C7/12 , G11C7/22 , G11C8/00
CPC分类号： G11C7/12 , G11C7/06 , G11C7/22 , G11C2207/065
摘要： A memory circuit generally comprising a bit cell, a sense amplifier, and a control circuit. The bit cell may be configured to generate a bit signal. The sense amplifier may be configured to generate a reset signal in response to sensing the bit signal. The control circuit may be configured to (i) set a control latch in response to a detection signal and (ii) reset the control latch in response to the reset signal, wherein the control latch is set while both the detection signal and the reset signal are in an asserted state.
摘要翻译：通常包括位单元，读出放大器和控制电路的存储器电路。位单元可以被配置为生成位信号。读出放大器可以被配置为响应于感测位信号而产生复位信号。控制电路可以被配置为：（i）响应于检测信号设置控制锁存器，以及（ii）响应于复位信号复位控制锁存器，其中控制锁存器被设置成同时检测信号和复位信号处于断言状态。

80. 发明授权

US06881672B2 Selective silicide blocking 失效
标题翻译：选择性硅化物封闭
公开(公告)号：US06881672B2
公开(公告)日：2005-04-19
申请号：US10723700
申请日：2003-11-26
申请人： Matthew J. Breitwisch , Jeffrey S. Brown , Terence B. Hook , Randy W. Mann , Christopher S. Putnam , Mohammad I. Younus
发明人： Matthew J. Breitwisch , Jeffrey S. Brown , Terence B. Hook , Randy W. Mann , Christopher S. Putnam , Mohammad I. Younus
IPC分类号： H01L21/8238 , H01L21/44
CPC分类号： H01L21/823871 , H01L21/823842
摘要： A selectively silicided semiconductor structure and a method for fabricating same is disclosed herein. The semiconductor structure has silicide present on the polysilicon line between the N+ diffusion or N+ active area and the P+ diffusion or active area at the N+/P+ junction of the polysilicon line, and silicide is not present on the N+ active area and the P+ active area. The presence of this selective silicidation creates a beneficial low-resistance connection between the N+ region of the polysilicon line and the P+ region of the polysilicon line. The absence of silicidation on the N+ and P+ active areas, specifically on the PFET and NFET structures, prevents current leakage associated with the silicidation of devices.
摘要翻译：本文公开了选择性硅化半导体结构及其制造方法。半导体结构在多晶硅线路上存在硅化物，N +扩散区域或N +有源区域与多晶硅线路的N + / P +结处的P +扩散区域或有源区域之间存在硅化物，而N +有源区域和P +活性区域上不存在硅化物区。这种选择性硅化的存在在多晶硅线的N +区和多晶硅线的P +区之间产生有益的低电阻连接。在N +和P +有源区，特别是PFET和NFET结构上不存在硅化，可防止与器件硅化相关的电流泄漏。

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