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71. 发明授权

US07399665B2 Electrostatic discharge protection device and method of fabricating same 有权
标题翻译：静电放电保护装置及其制造方法
公开(公告)号：US07399665B2
公开(公告)日：2008-07-15
申请号：US11781370
申请日：2007-07-23
申请人： Robert J. Gauthier, Jr. , Junjun Li , Souvick Mitra , Mahmoud A. Mousa , Christopher Stephen Putnam
发明人： Robert J. Gauthier, Jr. , Junjun Li , Souvick Mitra , Mahmoud A. Mousa , Christopher Stephen Putnam
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L29/7436 , H01L21/84 , H01L27/0262 , H01L27/1203
摘要： A silicon control rectifier, a method of making the silicon control rectifier and the use of the silicon control rectifier as an electrostatic discharge protection device of an integrated circuit. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.
摘要翻译：硅控制整流器，制造硅控制整流器的方法和使用硅控制整流器作为集成电路的静电放电保护器件。硅控制整流器包括形成在硅层中的硅体，其与绝缘体上硅衬底的掩埋氧化物层直接物理接触，硅层的顶表面限定水平面; 并且形成在硅体的第一区域中的硅控制整流器的阳极和形成在硅体的相对的第二区域中的硅控制整流器的阴极，其中阳极和阴极之间的电流路径仅为在平行于水平面的单个水平方向上。

72. 发明授权

US07345503B2 Method and apparatus for impedance matching in transmission circuits using tantalum nitride resistor devices 有权
标题翻译：使用氮化钽电阻器件的传输电路中的阻抗匹配的方法和装置
公开(公告)号：US07345503B2
公开(公告)日：2008-03-18
申请号：US11427798
申请日：2006-06-30
申请人： Fen Chen , Kai D. Feng , Robert J. Gauthier, Jr. , Tom C. Lee
发明人： Fen Chen , Kai D. Feng , Robert J. Gauthier, Jr. , Tom C. Lee
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/018571
摘要： A method for trimming impedance matching devices in high-speed circuits includes determining an electrical parameter associated with a first tantalum nitride (TaN) resistor used as an impedance matching device in the circuit under test, and comparing the determined electrical parameter associated with the first TaN resistor to a desired design value of the electrical parameter. The resistance value of the first TaN resistor is altered by application of a trimming voltage thereto, wherein the trimming voltage is based on a voltage-resistance characteristic curve of the first TaN resistor. It is then determined whether the altered resistance value of the first TaN resistor causes the electrical parameter to equal the desired design value thereof, and the altering of the resistance value of the first TaN resistor by application of a trimming voltage is repeated until the electrical parameter equals the desired design value thereof.
摘要翻译：一种用于微调高速电路中的阻抗匹配装置的方法包括：确定与在被测电路中用作阻抗匹配装置的第一氮化钽（TaN）电阻相关联的电参数，并将确定的与第一TaN相关的电参数进行比较电阻到所需的电参数设计值。通过施加微调电压来改变第一TaN电阻器的电阻值，其中微调电压基于第一TaN电阻器的耐电压特性曲线。然后确定第一TaN电阻器的改变的电阻值是否使电参数等于其期望的设计值，并且重复通过施加微调电压来改变第一TaN电阻器的电阻值，直到电参数等于其期望的设计值。

73. 发明授权

US07276768B2 Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures 有权
标题翻译：用于闭锁抑制的半导体结构和形成这种半导体结构的方法
公开(公告)号：US07276768B2
公开(公告)日：2007-10-02
申请号：US11340737
申请日：2006-01-26
申请人： Toshiharu Furukawa , Robert J. Gauthier, Jr. , David Vaclav Horak , Charles William Koburger, III , Jack Allan Mandelman , William Robert Tonti
发明人： Toshiharu Furukawa , Robert J. Gauthier, Jr. , David Vaclav Horak , Charles William Koburger, III , Jack Allan Mandelman , William Robert Tonti
IPC分类号： H01L31/00
CPC分类号： H01L21/76237 , H01L21/26533 , H01L21/76213 , H01L21/76229 , H01L21/76232 , H01L21/823878 , H01L27/0921 , H01L29/1087 , H01L29/78
摘要： Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises a shaped-modified isolation region that is formed in a trench generally between two doped wells of the substrate in which the bulk CMOS devices are fabricated. The shaped-modified isolation region may comprise a widened dielectric-filled portion of the trench, which may optionally include a nearby damage region, or a narrowed dielectric-filled portion of the trench that partitions a damage region between the two doped wells. Latch-up may also be suppressed by providing a lattice-mismatched layer between the trench base and the dielectric filler in the trench.
摘要翻译：用于抑制大量CMOS器件中的闩锁的半导体结构和方法。该半导体结构包括成形修饰的隔离区，其形成在通常在制造本体CMOS器件的衬底的两个掺杂阱之间的沟槽中。成形改进的隔离区域可以包括沟槽的加宽的电介质填充部分，其可以可选地包括分隔两个掺杂阱之间的损伤区域的沟槽的附近损伤区域或狭窄的电介质填充部分。也可以通过在沟槽中的沟槽基底和介电填料之间提供晶格不匹配的层来抑制闩锁。

74. 发明授权

US06541981B2 Automation of transmission line pulse testing of electrostatic discharge devices 失效
标题翻译：静电放电装置传输线脉冲测试自动化
公开(公告)号：US06541981B2
公开(公告)日：2003-04-01
申请号：US09832072
申请日：2001-04-10
申请人： Harvey C. Allard, Jr. , Donald J. Cook , Robert J. Gauthier, Jr. , Edward S. Hoyt , Dain E. Reinhart , John A. Watson
发明人： Harvey C. Allard, Jr. , Donald J. Cook , Robert J. Gauthier, Jr. , Edward S. Hoyt , Dain E. Reinhart , John A. Watson
IPC分类号： G01R2912
CPC分类号： G01R31/14 , G01R31/002 , G01R31/2839 , G01R31/2851
摘要： A method and apparatus for automated testing of a plurality of electrostatic discharge (ESD) devices on a wafer. The wafer has M padsets and N conductive pads on each padset, where m is at least 1, and n is at least 2, and each ESD device is conductively coupled to a unique plurality of pads of a padset of the M padsets. Testing sequences, under program control of a computer system, implement the testing of the ESD devices.
摘要翻译：一种用于在晶片上自动测试多个静电放电（ESD）器件的方法和装置。晶片在每个焊盘上具有M个焊盘和N个导电焊盘，其中m为至少1，n为至少2，并且每个ESD器件与M个焊盘的焊盘的唯一多个焊盘导电耦合。在计算机系统的程序控制下的测试序列实现了ESD器件的测试。

75. 发明授权

US08737028B2 RC-triggered ESD clamp device with feedback for time constant adjustment 有权
标题翻译： RC触发ESD钳位装置，具有时间常数调整反馈
公开(公告)号：US08737028B2
公开(公告)日：2014-05-27
申请号：US13312047
申请日：2011-12-06
申请人： James P. Di Sarro , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra
发明人： James P. Di Sarro , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra
IPC分类号： H02H9/04 , G06F17/50
CPC分类号： H02H9/046
摘要： Methods for responding to an electrostatic discharge (ESD) event on a voltage rail, ESD protection circuits, and design structures for an ESD protection circuit. An RC network of the ESD protection circuit includes a capacitor coupled to a field effect transistor at a node. The node of the RC network is coupled with an input of the inverter. The field-effect transistor is coupled with an output of the inverter. In response to an ESD event, a trigger signal is supplied from the RC network to the input of the inverter, which drives a clamp device to discharge current from the ESD event from the voltage rail. An RC time constant of the RC network is increased in response to the ESD event to sustain the discharge of the current by the clamp device.
摘要翻译：用于响应电压轨上的静电放电（ESD）事件，ESD保护电路以及ESD保护电路的设计结构的方法。 ESD保护电路的RC网络包括耦合到节点处的场效应晶体管的电容器。 RC网络的节点与逆变器的输入端相连。场效应晶体管与反相器的输出端相连。响应于ESD事件，触发信号从RC网络提供给逆变器的输入，该驱动器驱动钳位装置以从ESD电压放电来自电压轨。响应于ESD事件，RC网络的RC时间常数增加以维持钳位装置的电流放电。

76. 发明授权

US08692291B2 Passive devices for FinFET integrated circuit technologies 有权
标题翻译： FinFET集成电路技术的无源器件
公开(公告)号：US08692291B2
公开(公告)日：2014-04-08
申请号：US13431456
申请日：2012-03-27
申请人： William F. Clark, Jr. , Robert J. Gauthier, Jr. , Junjun Li
发明人： William F. Clark, Jr. , Robert J. Gauthier, Jr. , Junjun Li
IPC分类号： H01L29/66
CPC分类号： H01L21/845 , H01L27/0262 , H01L27/1211
摘要： Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A device structure is formed that includes a well of a first conductivity type in a device region and a doped region of a second conductivity in the well. The device region is comprised of a portion of a device layer of a semiconductor-on-insulator substrate. The doped region and a first portion of the well define a junction. A second portion of the well is positioned between the doped region and an exterior sidewall of the device region. Another portion of the device layer may be patterned to form fins for fin-type field-effect transistors.
摘要翻译：无源器件的器件结构，设计结构和制造方法可用作鳍式场效应晶体管集成电路技术中的静电放电保护器件。形成器件结构，其包括器件区域中的第一导电类型的阱和阱中的第二导电性的掺杂区域。器件区域由绝缘体上半导体衬底的器件层的一部分组成。掺杂区域和阱的第一部分限定了结。阱的第二部分位于器件区域的掺杂区域和外部侧壁之间。可以对器件层的另一部分进行构图以形成翅片型场效应晶体管的鳍片。

77. 发明授权

US08637353B2 Through silicon via repair 失效
标题翻译：通过硅片修复
公开(公告)号：US08637353B2
公开(公告)日：2014-01-28
申请号：US13013378
申请日：2011-01-25
申请人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
发明人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
IPC分类号： H01L21/82
CPC分类号： H01L22/30 , H01L21/76886 , H01L21/76898 , H01L22/14 , H01L22/20 , H01L25/0657 , H01L25/50 , H01L2225/06541 , H01L2225/06596 , H01L2924/0002 , Y10T29/5313 , Y10T29/532 , H01L2924/00
摘要： Methods and systems for altering the electrical resistance of a wiring path. The electrical resistance of the wiring path is compared with a target electrical resistance value. If the electrical resistance of the wiring path exceeds the target electrical resistance value, an electrical current is selectively applied to the wiring path to physically alter a portion of the wiring path. The current may be selected to alter the wiring path such that the electrical resistance drops to a value less than or equal to the target electrical resistance value.
摘要翻译：用于改变布线路径的电阻的方法和系统。将布线路径的电阻与目标电阻值进行比较。如果布线路径的电阻超过目标电阻值，则选择性地向布线路径施加电流，以物理地改变布线路径的一部分。可以选择电流来改变布线路径，使得电阻下降到小于或等于目标电阻值的值。

78. 发明授权

US08514535B2 Electrostatic discharge device control and structure 失效
标题翻译：静电放电装置的控制和结构
公开(公告)号：US08514535B2
公开(公告)日：2013-08-20
申请号：US12987276
申请日：2011-01-10
申请人： Robert J. Gauthier, Jr. , Junjun Li , Souvick Mitra
发明人： Robert J. Gauthier, Jr. , Junjun Li , Souvick Mitra
IPC分类号： H02H3/22
CPC分类号： H01L27/0285
摘要： Structures and methods for electrostatic discharge (ESD) device control in an integrated circuit are provided. An ESD protection structure includes an input/output (I/O) pad, and an ESD field effect transistor (FET) including a drain connected to the I/O pad, a source connected to ground, and a gate. A first control FET includes a drain connected to the I/O pad, a source connected to the gate of the ESD FET, and a gate connected to ground. A second control FET includes a drain connected to the gate of the ESD FET and the source of the first control FET, a source connected to ground, and a gate connected to the I/O pad.
摘要翻译：提供集成电路中静电放电（ESD）器件控制的结构和方法。 ESD保护结构包括输入/输出（I / O）焊盘和包括连接到I / O焊盘的漏极，连接到地的源极和栅极的ESD场效应晶体管（FET）。第一控制FET包括连接到I / O焊盘的漏极，连接到ESD FET的栅极的源极和连接到地的栅极。第二控制FET包括连接到ESD FET的栅极和第一控制FET的源极的漏极，连接到地的源极和连接到I / O焊盘的栅极。

79. 发明授权

US08503140B2 Bi-directional back-to-back stacked SCR for high-voltage pin ESD protection, methods of manufacture and design structures 有权
标题翻译：用于高压引脚ESD保护的双向背对背堆叠SCR，制造和设计结构的方法
公开(公告)号：US08503140B2
公开(公告)日：2013-08-06
申请号：US12898013
申请日：2010-10-05
申请人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
发明人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
IPC分类号： H02H9/00
CPC分类号： H01L27/0262 , H01L29/747 , H01L29/87 , H02H9/04
摘要： Bi-directional back-to-back stacked SCRs for high-voltage pin ESD protection, methods of manufacture and design structures are provided. The device includes a symmetrical bi-directional back-to-back stacked silicon controlled rectifier (SCR). An anode of a first of the back-to-back stacked SCR is connected to an input. An anode of a second of the back-to-back stacked SCR is connected to ground. Cathodes of the first and second of the back-to-back stacked SCR are connected together. Each of the symmetrical bi-directional back-to-back SCRs include a pair of diodes directing current towards the cathodes which, upon application of a voltage, become reverse biased effectively and deactivating elements from one of the symmetrical bi-directional back-to-back SCRs while the diodes of another of the symmetrical bi-directional back-to-back SCRs direct current in the same direction as the reverse biased diodes.
摘要翻译：提供用于高压针ESD保护的双向背对背堆叠SCR，制造方法和设计结构。该器件包括对称双向背对背层叠可控硅整流器（SCR）。背对背堆叠的SCR中的第一个的阳极连接到输入。背对背堆叠的SCR的第二个的阳极连接到地面。第一个和第二个背靠背堆叠的SCR的阴极连接在一起。对称双向背靠背SCR中的每一个包括一对二极管，其引导电流朝向阴极，其在施加电压时有效地变得有效地反向偏置，并且从对称的双向后向SCR中的一个去激活元件，另一个对称双向背对背SCR的二极管在与反向偏置二极管相同的方向上直流电流，反向SCR。

80. 发明授权

US08230382B2 Model based simulation of electronic discharge and optimization methodology for design checking 有权
标题翻译：基于模型的电子放电仿真和设计检查优化方法
公开(公告)号：US08230382B2
公开(公告)日：2012-07-24
申请号：US12695494
申请日：2010-01-28
申请人： Robert J. Gauthier, Jr. , Bradford L. Hunter , Amol A. Joshi , Junjun Li , Gregory Joseph Schroer
发明人： Robert J. Gauthier, Jr. , Bradford L. Hunter , Amol A. Joshi , Junjun Li , Gregory Joseph Schroer
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method, apparatus and program product are provided for simulating a circuit. A plurality of elements of the circuit is represented by device models including pass/fail criteria. A circuit simulation program is executed on a hardware implemented processor where the circuit simulation program is configured to obtain simulation results from the device models in response to applied parameters. The circuit simulation program identifies a failure of one or more of the plurality of elements of the circuit based on the pass/fail criteria of the device models. The circuit simulation program is further configured to output the failures during simulation of the one or more of the plurality of elements that are identified in response to the applied parameters.
摘要翻译：提供了一种用于模拟电路的方法，装置和程序产品。电路的多个元件由包括通过/不合格标准的器件模型表示。在硬件实现的处理器上执行电路仿真程序，其中电路仿真程序被配置为响应于所应用的参数从设备模型获得仿真结果。电路仿真程序基于设备模型的通过/不合格标准来识别电路的多个元件中的一个或多个元件的故障。电路仿真程序还被配置为在模拟响应于所应用的参数识别的多个元件中的一个或多个元件期间输出故障。

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