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71. 发明授权

US09128698B2 Systems, apparatuses, and methods for performing rotate and XOR in response to a single instruction 有权
标题翻译：响应于单个指令执行旋转和异或的系统，设备和方法
公开(公告)号：US09128698B2
公开(公告)日：2015-09-08
申请号：US13631242
申请日：2012-09-28
申请人： Vinodh Gopal , Gilbert M. Wolrich , James D. Guilford , Kirk S. Yap
发明人： Vinodh Gopal , Gilbert M. Wolrich , James D. Guilford , Kirk S. Yap
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30167
摘要： Disclosed herein are systems, apparatuses, and methods performing in a computer processor of performing a rotate and XOR in response to a single XOR and rotate instruction, wherein the rotate and XOR instruction includes a first and second source operand, a destination operand, and an immediate value.
摘要翻译：这里公开的是在计算机处理器中执行的响应于单个XOR和旋转指令执行旋转和异或的系统，装置和方法，其中旋转和XOR指令包括第一和第二源操作数，目的地操作数和即时价值。

72. 发明申请

US20140189369A1 Instructions Processors, Methods, and Systems to Process Secure Hash Algorithms 有权
标题翻译：指令处理器，方法和系统来处理安全散列算法
公开(公告)号：US20140189369A1
公开(公告)日：2014-07-03
申请号：US13843141
申请日：2013-03-15
申请人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal , James D. Guilford
发明人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal , James D. Guilford
IPC分类号： G06F21/72
CPC分类号： H04L9/0643 , G06F9/30007 , G06F9/30036 , G06F9/30101 , G06F9/30145 , G06F9/3016 , G06F21/602 , G06F21/64 , G06F21/72
摘要： A method of an aspect includes receiving an instruction. The instruction indicates a first source of a first packed data including state data elements ai, bi, ei, and fi for a current round (i) of a secure hash algorithm 2 (SHA2) hash algorithm. The instruction indicates a second source of a second packed data. The first packed data has a width in bits that is less than a combined width in bits of eight state data elements ai, bi, ci, di, ei, fi, gi, hi of the SHA2 hash algorithm. The method also includes storing a result in a destination indicated by the instruction in response to the instruction. The result includes updated state data elements ai+, bi+, ei+, and fi+ that have been updated from the corresponding state data elements ai, bi, ei, and fi by at least one round of the SHA2 hash algorithm.
摘要翻译：方面的方法包括接收指令。该指令指示包括安全散列算法2（SHA2）散列算法的当前轮（i）的状态数据元素ai，bi，ei和fi的第一打包数据的第一来源。该指令指示第二打包数据的第二来源。第一打包数据具有小于SHA2散列算法的八个状态数据元素ai，bi，ci，di，ei，fi，gi，hi的组合宽度的比特宽度。该方法还包括响应于指令将结果存储在由指令指示的目的地中。结果包括已经通过至少一轮的SHA2散列算法从相应的状态数据元素ai，bi，ei和fi更新的更新的状态数据元素ai +，bi +，ei +和fi +。

73. 发明申请

US20140095844A1 Systems, Apparatuses, and Methods for Performing Rotate and XOR in Response to a Single Instruction 有权
标题翻译：用于对单个指令进行旋转和异或运算的系统，设备和方法
公开(公告)号：US20140095844A1
公开(公告)日：2014-04-03
申请号：US13631242
申请日：2012-09-28
申请人： Vinodh Gopal , Gilbert M. Wolrich , James D. Guilford , Kirk S. Yap
发明人： Vinodh Gopal , Gilbert M. Wolrich , James D. Guilford , Kirk S. Yap
IPC分类号： G06F9/30
CPC分类号： G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30167
摘要： Disclosed herein are systems, apparatuses, and methods performing in a computer processor of performing a rotate and XOR in response to a single XOR and rotate instruction, wherein the rotate and XOR instruction includes a first and second source operand, a destination operand, and an immediate value.
摘要翻译：这里公开的是在计算机处理器中执行的响应于单个XOR和旋转指令执行旋转和异或的系统，装置和方法，其中旋转和XOR指令包括第一和第二源操作数，目的操作数和即时价值。

74. 发明授权

US08953785B2 Instruction set for SKEIN256 SHA3 algorithm on a 128-bit processor 有权
标题翻译： 128位处理器上的SKEIN256 SHA3算法指令集
公开(公告)号：US08953785B2
公开(公告)日：2015-02-10
申请号：US13631143
申请日：2012-09-28
申请人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal
发明人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal
IPC分类号： H04L9/28
CPC分类号： H04L9/0643 , G06F9/30007 , G06F9/30032 , G06F9/30036
摘要： According to one embodiment, a processor includes an instruction decoder to receive a first instruction to perform first SKEIN256 MIX-PERMUTE operations, the first instruction having a first operand associated with a first storage location to store a plurality of odd words, a second operand associated with a second storage location to store a plurality of even words, and a third operand. The processor further includes a first execution unit coupled to the instruction decoder, in response to the first instruction, to perform multiple rounds of the first SKEIN256 MIX-PERMUTE operations based on the odd words and even words using a first rotate value obtained from a third storage location indicated by the third operand, and to store new odd words in the first storage location indicated by the first operand.
摘要翻译：根据一个实施例，处理器包括指令解码器，用于接收执行第一SKEIN256 MIX-PERMUTE操作的第一指令，所述第一指令具有与第一存储位置相关联的第一操作数，以存储多个奇数字，第二操作数相关联具有存储多个偶数字的第二存储位置和第三操作数。处理器还包括响应于第一指令而耦合到指令解码器的第一执行单元，使用从第三指令获得的第一旋转值，基于奇数字和偶数字进行第一SKEIN256 MIX-PERMUTE操作的多轮由第三操作数指示的存储位置，并将新的奇数字存储在由第一操作数指示的第一存储位置中。

75. 发明申请

US20140093068A1 INSTRUCTION SET FOR SKEIN256 SHA3 ALGORITHM ON A 128-BIT PROCESSOR 有权
标题翻译： 128位处理器的SKEIN256 SHA3算法指令集
公开(公告)号：US20140093068A1
公开(公告)日：2014-04-03
申请号：US13631143
申请日：2012-09-28
申请人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal
发明人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal
IPC分类号： H04L9/28
CPC分类号： H04L9/0643 , G06F9/30007 , G06F9/30032 , G06F9/30036
摘要： According to one embodiment, a processor includes an instruction decoder to receive a first instruction to perform first SKEIN256 MIX-PERMUTE operations, the first instruction having a first operand associated with a first storage location to store a plurality of odd words, a second operand associated with a second storage location to store a plurality of even words, and a third operand. The processor further includes a first execution unit coupled to the instruction decoder, in response to the first instruction, to perform multiple rounds of the first SKEIN256 MIX-PERMUTE operations based on the odd words and even words using a first rotate value obtained from a third storage location indicated by the third operand, and to store new odd words in the first storage location indicated by the first operand.
摘要翻译：根据一个实施例，处理器包括指令解码器，用于接收执行第一SKEIN256 MIX-PERMUTE操作的第一指令，所述第一指令具有与第一存储位置相关联的第一操作数，以存储多个奇数字，第二操作数相关联具有存储多个偶数字的第二存储位置和第三操作数。处理器还包括响应于第一指令而耦合到指令解码器的第一执行单元，使用从第三指令获得的第一旋转值，基于奇数字和偶数字进行第一SKEIN256 MIX-PERMUTE操作的多轮由第三操作数指示的存储位置，并将新的奇数字存储在由第一操作数指示的第一存储位置中。

76. 发明申请

US20100161536A1 PATTERN MATCHING 有权
标题翻译：图案匹配
公开(公告)号：US20100161536A1
公开(公告)日：2010-06-24
申请号：US12340360
申请日：2008-12-19
申请人： Christopher F. Clark , Vinodh Gopal , Gilbert M. Wolrich
发明人： Christopher F. Clark , Vinodh Gopal , Gilbert M. Wolrich
IPC分类号： G06N5/02
CPC分类号： H04L63/1416 , G06F21/552
摘要： A method and apparatus to perform pattern matching is provided. The apparatus includes a first storage to store data representing a first set of pattern components, and a second storage to store data representing a second set of pattern components each corresponding to one or more components of the first set of pattern components. A first pattern matcher is configured to detect in an input stream a first component of one or more patterns and to generate a signal indicative of the detection of the first component. A second pattern matcher is configured to receive the signal from the first pattern matcher and to detect if a second component of the one or more patterns of the set of patterns immediately follows the first component in the input stream.
摘要翻译：提供了执行模式匹配的方法和装置。该装置包括第一存储器，用于存储表示第一组模式组件的数据，以及第二存储器，用于存储表示第二组模式组件的数据，每个模式组件对应于第一组模式组件的一个或多个组件。第一模式匹配器被配置为在输入流中检测一个或多个模式的第一分量，并且生成指示第一分量的检测的信号。第二模式匹配器被配置为从第一模式匹配器接收信号并且检测该模式集合中的一个或多个模式的第二分量是否紧跟在输入流中的第一分量之后。

77. 发明授权

US07607068B2 Apparatus and method for generating a Galois-field syndrome 失效
标题翻译：用于产生伽罗瓦氏综合征的装置和方法
公开(公告)号：US07607068B2
公开(公告)日：2009-10-20
申请号：US11469222
申请日：2006-08-31
申请人： Vinodh Gopal , Gilbert M. Wolrich , Daniel Cutter , Wajdi Feghali , Robert P. Ottavi
发明人： Vinodh Gopal , Gilbert M. Wolrich , Daniel Cutter , Wajdi Feghali , Robert P. Ottavi
IPC分类号： G11C29/00
CPC分类号： G06F11/1076 , G06F2211/1054 , G06F2211/1057
摘要： The present disclosure provides an apparatus and method for generating a Galois-field syndrome. One exemplary method may include loading a first data byte from a first storage device to a first register and loading a second data byte from a second storage device to a second register; ANDing the most significant bit (MSB) of the first data byte and a Galois-field polynomial to generate a first intermediate output; XORing each bit of the first intermediate output with the least significant bits (LSBs) of the first data byte to generate a second intermediate output; MUXing the second intermediate output with each bit of the first data byte to generate a third intermediate output; XORing each bit of the third intermediate output with each bit of the second data byte to generate at a fourth intermediate output; and generating a RAID Q syndrome based on, at least in part, the fourth intermediate output. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开提供了一种用于产生伽罗瓦域综合征的装置和方法。一个示例性方法可以包括将第一数据字节从第一存储设备加载到第一寄存器，并将第二数据字节从第二存储设备加载到第二寄存器; 将第一数据字节的最高有效位（MSB）和伽罗瓦域多项式进行比较以产生第一中间输出; 用第一数据字节的最低有效位（LSB）对第一中间输出的每个位进行异或，以产生第二中间输出; 将第二中间输出与第一数据字节的每个位进行多路复用以产生第三中间输出; 将第三中间输出的每个位与第二数据字节的每个位进行异或，以在第四中间输出处产生; 以及至少部分地基于第四中间输出产生RAID Q综合征。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

78. 发明申请

US20080148011A1 Carry/Borrow Handling 审中-公开
标题翻译：携带/借款处理
公开(公告)号：US20080148011A1
公开(公告)日：2008-06-19
申请号：US11610897
申请日：2006-12-14
申请人： Vinodh Gopal , Gilbert M. Wolrich , Gunnar Gaubatz , Daniel Cutter , Wajdi Feghali , Kaan Yuksel , Erdinc Ozturk
发明人： Vinodh Gopal , Gilbert M. Wolrich , Gunnar Gaubatz , Daniel Cutter , Wajdi Feghali , Kaan Yuksel , Erdinc Ozturk
IPC分类号： G06F9/30
CPC分类号： G06F9/3001
摘要： The present disclosure provides a system and method for performing carry/borrow handling. A method according to one embodiment may include generating a first result having a first carry or borrow from a first mathematical operation and storing the first carry or borrow and a first pointer address in a temporary register. The method may further include generating a second result having a second carry or borrow from a second mathematical operation and calling a subroutine configured to perform carry and borrow handling. The method may also include copying the first pointer address from the temporary register into a global variable. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开提供了用于执行进位/借用处理的系统和方法。根据一个实施例的方法可以包括从第一数学运算产生具有第一进位或借位的第一结果，并将第一进位或借位以及第一指针地址存储在临时寄存器中。该方法还可以包括从第二数学运算产生具有第二进位或借位的第二结果，并调用被配置为执行进位和借位处理的子程序。该方法还可以包括将第一指针地址从临时寄存器复制到全局变量中。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

79. 发明申请

US20080144811A1 Method for Simultaneous Modular Exponentiations 有权
标题翻译：同时模块化指标的方法
公开(公告)号：US20080144811A1
公开(公告)日：2008-06-19
申请号：US11610919
申请日：2006-12-14
申请人： Vinodh Gopal , Erdinc Ozturk , Kaan Yuskel , Gunnar Gaubatz , Wajdi Feghali , Gilbert M. Wolrich
发明人： Vinodh Gopal , Erdinc Ozturk , Kaan Yuskel , Gunnar Gaubatz , Wajdi Feghali , Gilbert M. Wolrich
IPC分类号： H04L9/30
CPC分类号： G06F7/723 , H04L9/302
摘要： The present disclosure provides a method for performing modular exponentiation. The method may include generating a first remainder (xp) based on an encrypted message (X) modulo a first prime number (p) and generating a second remainder (xq) based on the encrypted message (X) modulo a second prime number (q). The method may further include generating a third remainder(v1) based on the first remainder (xp) raised to a first private key number (d1) modulo the first prime number (p) and simultaneously generating a fourth remainder (v2) based on the second remainder (xq) raised to a second private key number (d2) modulo the second prime number(q). The method may also include subtracting the fourth remainder (v2) from the third remainder (v1) to yield a result (v1−v2) and multiplying the result (v1−v2) by a constant (c) to produce a second result. The method may additionally include generating a sixth remainder (h) by taking the second result modulo the first prime number (p) and multiplying the sixth remainder (h) by the second prime number (q) to produce a third result. The method may further include adding the third result and the fourth remainder (v2) to yield a final result (Y) and generating, at least in part, a public key based on the final result (Y). Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开提供了一种用于执行模幂运算的方法。该方法可以包括基于第一素数（p）模数的加密消息（X）生成第一余数（xp），并且基于加密消息（X）生成第二余数（xq），第二素数（q））。该方法还可以包括：基于第一余数（xp）产生第三余数（v1），所述第一余数（xp）基于所述第一余数（xp）生成第一素数（p）的第一私钥数（d1）并同时生成第四余数第二余数（xq）升至第二素数（q）的第二私钥号（d2）。该方法还可以包括从第三余数（v1）中减去第四余数（v2）以产生结果（v1-v2）并将结果（v1-v2）乘以常数（c）以产生第二结果。该方法可以另外包括通过将第二结果以第一素数（p）取模并将第六余数（h）乘以第二素数（q）产生第三结果来产生第六余数（h）。该方法还可以包括添加第三结果和第四余数（v2）以产生最终结果（Y），并且至少部分地基于最终结果（Y）生成公钥。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

80. 发明申请

US20120150887A1 PATTERN MATCHING 审中-公开
标题翻译：图案匹配
公开(公告)号：US20120150887A1
公开(公告)日：2012-06-14
申请号：US12963438
申请日：2010-12-08
申请人： Christopher F. Clark , Vinodh Gopal , Gilbert M. Wolrich
发明人： Christopher F. Clark , Vinodh Gopal , Gilbert M. Wolrich
IPC分类号： G06F17/30
CPC分类号： G06F16/90344
摘要： An embodiment may include circuitry to determine, at least in part, whether one or more reference patterns are present in a data stream in a packet flow. The circuitry may include first pattern matching circuitry communicatively coupled to second pattern matching circuitry. The first pattern matching circuitry may determine, based at least in part upon one or more deterministic pattern matching operations, whether at least one portion of the one or more reference patterns is present in the stream. If the first pattern matching circuitry determines that the at least one portion of the one or more reference patterns is present in the stream, the second pattern matching circuitry may determine, based at least in part upon one or more pattern matching threads, whether at least one other portion of the one or more reference patterns is present in the stream. Many modifications are possible without departing from this embodiment.
摘要翻译：一个实施例可以包括至少部分地确定分组流中的数据流中是否存在一个或多个参考模式的电路。电路可以包括通信地耦合到第二模式匹配电路的第一模式匹配电路。第一模式匹配电路可以至少部分地基于一个或多个确定性模式匹配操作来确定流中是否存在一个或多个参考模式的至少一部分。如果第一模式匹配电路确定一个或多个参考模式的至少一部分存在于流中，则第二模式匹配电路可以至少部分地基于一个或多个模式匹配线程来确定是否至少一个或多个参考图案的另一部分存在于流中。在不脱离本实施例的情况下，可以进行许多修改。

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