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71. 发明申请

US20080157225A1 SRAM and logic transistors with variable height multi-gate transistor architecture 审中-公开
标题翻译：具有可变高度多栅极晶体管结构的SRAM和逻辑晶体管
公开(公告)号：US20080157225A1
公开(公告)日：2008-07-03
申请号：US11648521
申请日：2006-12-29
申请人： Suman Datta , Brian S. Doyle , Jack T. Kavalieros , Yih Wang
发明人： Suman Datta , Brian S. Doyle , Jack T. Kavalieros , Yih Wang
IPC分类号： H01L21/336 , H01L29/768
CPC分类号： H01L27/105 , H01L27/11 , H01L27/1104 , H01L27/1116 , H01L29/66795 , H01L29/7851
摘要： Multi-gate transistors having different channel widths formed on non-planar semiconductor bodies have different sidewall heights and method of manufacturing the same. In an embodiment, a multi-gate SRAM transistor is formed on a non-planar semiconductor body having a greater sidewall height than a non-planar semiconductor body utilized for a multi-gate logic transistor to improve performance of SRAM and logic transistors formed on the same substrate. In another embodiment, to reduce cell area, a first SRAM transistor is formed on a non-planar semiconductor body having a greater sidewall height than a non-planar semiconductor body utilized for a second multi-gate SRAM transistor.
摘要翻译：形成在非平面半导体主体上的具有不同沟道宽度的多栅极晶体管具有不同的侧壁高度及其制造方法。在一个实施例中，多栅极SRAM晶体管形成在具有比用于多栅极逻辑晶体管的非平面半导体主体更大的侧壁高度的非平面半导体主体上，以改善在栅极上形成的SRAM和逻辑晶体管的性能相同的底物。在另一个实施例中，为了减小单元面积，第一SRAM晶体管形成在具有比用于第二多栅极SRAM晶体管的非平面半导体主体更大的侧壁高度的非平面半导体本体上。

72. 发明授权

US06972225B2 integrating n-type and P-type metal gate transistors 有权
标题翻译：集成n型和P型金属栅极晶体管
公开(公告)号：US06972225B2
公开(公告)日：2005-12-06
申请号：US10946502
申请日：2004-09-20
申请人： Mark Doczy , Justin K. Brask , Steven J. Keating , Chris E. Barns , Brian S. Doyle , Michael L. McSwiney , Jack T. Kavalieros , John P. Barnak
发明人： Mark Doczy , Justin K. Brask , Steven J. Keating , Chris E. Barns , Brian S. Doyle , Michael L. McSwiney , Jack T. Kavalieros , John P. Barnak
IPC分类号： H01L21/3213 , H01L21/336 , H01L21/8238 , H01L29/49 , H01L29/78
CPC分类号： H01L29/66545 , H01L21/32134 , H01L21/32137 , H01L21/823842 , H01L29/495 , H01L29/4966 , H01L29/7833 , Y10S438/926
摘要： At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.
摘要翻译：至少p型和n型半导体器件沉积在包含金属或金属合金栅极的半导体晶片上。更具体地，在具有n型和p型金属栅极的半导体晶片上形成互补金属氧化物半导体（CMOS）器件。

73. 发明授权

US06858483B2 Integrating n-type and p-type metal gate transistors 有权
标题翻译：集成n型和p型金属栅晶体管
公开(公告)号：US06858483B2
公开(公告)日：2005-02-22
申请号：US10327293
申请日：2002-12-20
申请人： Mark Doczy , Justin K. Brask , Steven J. Keating , Chris E. Barns , Brian S. Doyle , Michael L. McSwiney , Jack T. Kavalieros , John P. Barnak
发明人： Mark Doczy , Justin K. Brask , Steven J. Keating , Chris E. Barns , Brian S. Doyle , Michael L. McSwiney , Jack T. Kavalieros , John P. Barnak
IPC分类号： H01L21/3213 , H01L21/336 , H01L21/8238 , H01L29/49 , H01L29/78
CPC分类号： H01L29/66545 , H01L21/32134 , H01L21/32137 , H01L21/823842 , H01L29/495 , H01L29/4966 , H01L29/7833 , Y10S438/926
摘要： At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.
摘要翻译：至少p型和n型半导体器件沉积在包含金属或金属合金栅极的半导体晶片上。更具体地，在具有n型和p型金属栅极的半导体晶片上形成互补金属氧化物半导体（CMOS）器件。

74. 发明申请

US20100163945A1 Embedded memory cell and method of manufacturing same 有权
标题翻译：嵌入式存储单元及其制造方法
公开(公告)号：US20100163945A1
公开(公告)日：2010-07-01
申请号：US12319101
申请日：2008-12-30
申请人： Jack T. Kavalieros , Niloy Mukherjee , Gilbert Dewey , Dinesh Somasekhar , Brian S. Doyle
发明人： Jack T. Kavalieros , Niloy Mukherjee , Gilbert Dewey , Dinesh Somasekhar , Brian S. Doyle
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L29/66181 , H01L27/10832 , H01L27/10861 , H01L27/10867 , H01L27/1087 , H01L27/10876 , H01L28/90 , H01L29/66666 , H01L29/7827
摘要： An embedded memory cell includes a semiconducting substrate (110), a transistor (120) having a source/drain region (121) at least partially embedded in the semiconducting substrate, and a capacitor (130) at least partially embedded in the semiconducting substrate. The capacitor includes a first electrode (131) and a second electrode (132) that are electrically isolated from each other by a first electrically insulating material (133). The first electrode is electrically connected to the semiconducting substrate and the second electrode is electrically connected to the source/drain region of the transistor.
摘要翻译：嵌入式存储单元包括半导体衬底（110），具有至少部分地嵌入在半导体衬底中的源极/漏极区域（121）的晶体管（120）以及至少部分地嵌入在半导体衬底中的电容器（130）。电容器包括通过第一电绝缘材料（133）彼此电绝缘的第一电极（131）和第二电极（132）。第一电极电连接到半导体衬底，第二电极电连接到晶体管的源极/漏极区域。

75. 发明授权

US07629643B2 Independent n-tips for multi-gate transistors 有权
标题翻译：多栅极晶体管的独立n尖端
公开(公告)号：US07629643B2
公开(公告)日：2009-12-08
申请号：US11948414
申请日：2007-11-30
申请人： Ravi Pillarisetty , Suman Datta , Jack T. Kavalieros , Brian S. Doyle
发明人： Ravi Pillarisetty , Suman Datta , Jack T. Kavalieros , Brian S. Doyle
IPC分类号： H01L27/108
CPC分类号： H01L27/1104 , H01L27/0207 , H01L27/11 , H01L29/785
摘要： Independent n-tips for multi-gate transistors are generally described. In one example, an apparatus includes a semiconductor fin, one or more multi-gate pull down (PD) devices coupled with the semiconductor fin, the one or more PD devices having an n-tip dopant concentration in the semiconductor fin material adjacent to the one or more PD devices, and one or more multi-gate pass gate (PG) devices coupled with the semiconductor fin, the one or more PG devices having an n-tip dopant concentration in the semiconductor fin material adjacent to the one or more PG devices, wherein the n-tip dopant concentration for the PG device is lower than the n-tip dopant concentration for the PD device.
摘要翻译：通常描述多栅极晶体管的独立n尖端。在一个示例中，设备包括半导体鳍片，与半导体鳍片耦合的一个或多个多栅极下拉（PD）器件，所述一个或多个PD器件在与半导体鳍片材料相邻的半导体鳍片材料中具有n尖端掺杂剂浓度一个或多个PD器件，以及与半导体鳍片耦合的一个或多个多栅极通过栅极（PG）器件，所述一个或多个PG器件在与所述一个或多个PG相邻的半导体鳍片材料中具有n尖端掺杂剂浓度器件，其中PG器件的n尖掺杂剂浓度低于PD器件的n尖掺杂剂浓度。

76. 发明授权

US07402856B2 Non-planar microelectronic device having isolation element to mitigate fringe effects and method to fabricate same 有权
标题翻译：具有隔离元件以减轻边缘效应的非平面微电子器件及其制造方法
公开(公告)号：US07402856B2
公开(公告)日：2008-07-22
申请号：US11299102
申请日：2005-12-09
申请人： Justin K. Brask , Jack T. Kavalieros , Brian S. Doyle , Robert S. Chau
发明人： Justin K. Brask , Jack T. Kavalieros , Brian S. Doyle , Robert S. Chau
IPC分类号： H01L29/94
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A non-planar microelectronic device, a method of fabricating the device, and a system including the device. The non-planar microelectronic device comprises: a substrate body including a substrate base and a fin, the fin defining a device portion at a top region thereof; a gate dielectric layer extending at a predetermined height on two laterally opposing sidewalls of the fin, the predetermined height corresponding to a height of the device portion; a device isolation layer on the substrate body and having a thickness up to a lower limit of the device portion; a gate electrode on the device isolation layer and further extending on the gate dielectric layer; an isolation element extending on the two laterally opposing sidewalls of the fin up to a lower limit of the gate dielectric layer, the isolation element being adapted to reduce any fringe capacitance between the gate electrode and regions of the fin extending below the device portion.
摘要翻译：非平面微电子器件，制造器件的方法以及包括该器件的系统。所述非平面微电子器件包括：衬底主体，其包括衬底基座和鳍片，所述鳍片限定其顶部区域处的器件部分; 栅极电介质层，其在所述鳍片的两个横向相对的侧壁上以预定高度延伸，所述预定高度对应于所述器件部分的高度; 在所述衬底主体上的器件隔离层，并且具有至所述器件部分的下限的厚度; 器件隔离层上的栅电极，并进一步在栅介质层上延伸; 隔离元件，其在所述鳍片的两个横向相对的侧壁上延伸到所述栅极电介质层的下限，所述隔离元件适于减小所述栅电极与所述鳍片延伸到所述器件部分下方的区域之间的任何条纹电容。

77. 发明授权

US06953719B2 Integrating n-type and p-type metal gate transistors 有权
公开(公告)号：US06953719B2
公开(公告)日：2005-10-11
申请号：US10851360
申请日：2004-05-20
申请人： Mark Doczy , Justin K. Brask , Steven J. Keating , Chris E. Barns , Brian S. Doyle , Michael L. McSwiney , Jack T. Kavalieros , John P. Barnak
发明人： Mark Doczy , Justin K. Brask , Steven J. Keating , Chris E. Barns , Brian S. Doyle , Michael L. McSwiney , Jack T. Kavalieros , John P. Barnak
IPC分类号： H01L21/3213 , H01L21/336 , H01L21/8238 , H01L29/49 , H01L29/78 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/66545 , H01L21/32134 , H01L21/32137 , H01L21/823842 , H01L29/495 , H01L29/4966 , H01L29/7833 , Y10S438/926
摘要： At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.

78. 发明授权

US07642603B2 Semiconductor device with reduced fringe capacitance 有权
标题翻译：具有降低的边缘电容的半导体器件
公开(公告)号：US07642603B2
公开(公告)日：2010-01-05
申请号：US11823892
申请日：2007-06-29
申请人： Suman Datta , Titash Rakshit , Jack T. Kavalieros , Brian S. Doyle
发明人： Suman Datta , Titash Rakshit , Jack T. Kavalieros , Brian S. Doyle
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/785 , H01L29/41791 , H01L29/66795 , H01L2029/7858
摘要： In one embodiment of the invention, a non-planar transistor includes a gate electrode and multiple fins. A trench contact is coupled to the fins. The contact bottom is formed above the substrate and does not directly contact the substrate. The contact bottom is higher than the gate top.
摘要翻译：在本发明的一个实施例中，非平面晶体管包括栅电极和多个散热片。沟槽接触件连接到鳍片。接触底部形成在衬底之上并且不直接接触衬底。触点底部高于门顶。

79. 发明申请

US20090166743A1 INDEPENDENT GATE ELECTRODES TO INCREASE READ STABILITY IN MULTI-GATE TRANSISTORS 审中-公开
标题翻译：独立门电极增加多栅极晶体管的读稳定性
公开(公告)号：US20090166743A1
公开(公告)日：2009-07-02
申请号：US11964633
申请日：2007-12-26
申请人： Ravi Pillarisetty , Brian S. Doyle , Jack T. Kavalieros , Robert S. Chau
发明人： Ravi Pillarisetty , Brian S. Doyle , Jack T. Kavalieros , Robert S. Chau
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L27/1104 , H01L27/11 , H01L29/785
摘要： Independent gate electrodes for multi-gate transistors are generally described. In one example, an apparatus includes a semiconductor fin, one or more multi-gate pull down (PD) gate stacks coupled with the semiconductor fin, the one or more PD gate stacks including a PD gate electrode, and one or more multi-gate pass gate (PG) gate stacks coupled with the semiconductor fin, the one or more PG gate stacks including a PG gate electrode, the PG gate electrode having a greater threshold voltage than the PD gate electrode.
摘要翻译：通常描述用于多栅极晶体管的独立栅电极。在一个示例中，装置包括半导体鳍片，与半导体鳍片耦合的一个或多个多栅极下拉（PD）栅极叠层，所述一个或多个PD栅极堆叠包括PD栅极电极和一个或多个多栅极所述PG栅极堆叠与所述半导体鳍片耦合，所述一个或多个PG栅极堆叠包括PG栅极电极，所述PG栅电极具有比所述PD栅电极更大的阈值电压。

80. 发明申请

US20080079003A1 Dual crystal orientation circuit devices on the same substrate 有权
标题翻译：双晶体取向电路器件在同一基片上
公开(公告)号：US20080079003A1
公开(公告)日：2008-04-03
申请号：US11529974
申请日：2006-09-29
申请人： Mohamad A. Shaheen , Peter Tolchinsky , Jack T. Kavalieros , Brian S. Doyle , Suman Datta , David Simon
发明人： Mohamad A. Shaheen , Peter Tolchinsky , Jack T. Kavalieros , Brian S. Doyle , Suman Datta , David Simon
IPC分类号： H01L29/04 , H01L21/00
CPC分类号： H01L29/045 , H01L29/66795 , H01L29/7851
摘要： Embodiments of the invention provide a substrate with a device layer having different crystal orientations in different portions or areas. One layer of material having one crystal orientation may be bonded to a substrate having another crystal orientation. Then, a portion of the layer may be amorphized and annealed to be re-crystallized to the crystal orientation of the substrate. N- and P-type devices, such as tri-gate devices, may both be formed on the substrate, with each type of device having the proper crystal orientation along the top and side surfaces of the claimed region for optimum performance. For instance, a substrate may have a portion with a crystal orientation along a top and sidewalls of an NMOS tri-gate transistor and another portion having a crystal orientation along parallel top and sidewall surfaces of a PMOS tri-gate transistor.
摘要翻译：本发明的实施例提供了具有在不同部分或区域中具有不同晶体取向的器件层的衬底。具有一个晶体取向的一层材料可以结合到具有另一晶体取向的衬底。然后，该层的一部分可以非晶化并退火，以再结晶到衬底的晶体取向。可以在衬底上形成N型和P型器件，例如三栅极器件，每种类型的器件沿着所要求保护的区域的顶表面和侧表面具有适当的晶体取向，以获得最佳性能。例如，衬底可以具有沿着NMOS三栅极晶体管的顶部和侧壁具有<100>晶体取向的部分，并且沿着PMOS三栅极的平行顶部和侧壁表面具有<110>晶体取向的另一部分晶体管。

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