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71. 发明授权

US5134449A Nonvolatile memory cell with field-plate switch 失效
标题翻译：具有场板开关的非易失性存储单元
公开(公告)号：US5134449A
公开(公告)日：1992-07-28
申请号：US661590
申请日：1991-02-26
申请人： Manzur Gill , Sebastiano D'Arrigo
发明人： Manzur Gill , Sebastiano D'Arrigo
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521
摘要： An array of nonvolatile memory cells are formed at a face of a semiconductor body, the cells including source regions and including drain regions that are part of a common drain column conductor. Each cell has first and second sub-channel regions between source and drain. The conductivity of the first sub-channel regions of each cell is controlled by a field-plate conductor formed over and insulated from the first sub-channel region. The conductivity of each of the second sub-channel regions is controlled by a floating-gate conductor formed over and insulated from the second sub-channel region. A row line, including control gates, is located above and insulated from the floating gates of the cells for reading, programming and erasing the cells. The field-plate conductor switch provides isolation of the cells during programming.
摘要翻译：在半导体本体的表面上形成非易失性存储单元的阵列，该单元包括源极区，并且包括作为公共漏极列导体的一部分的漏极区。每个单元在源极和漏极之间具有第一和第二子沟道区。每个单元的第一子沟道区的导电性由形成在第一子沟道区上并与第一子沟道区绝缘的场板导体控制。每个第二子沟道区的导电性由形成在第二子沟道区上并与第二子沟道区绝缘的浮栅导体控制。包括控制栅极的行线位于单元的浮动栅极的上方并与之隔绝，用于读取，编程和擦除单元。场板导体开关在编程过程中提供了单元的隔离。

72. 发明授权

US5060195A Hot electron programmable, tunnel electron erasable contactless EEPROM 失效
标题翻译：热电子可编程，隧道电子可擦除非接触式EEPROM
公开(公告)号：US5060195A
公开(公告)日：1991-10-22
申请号：US595521
申请日：1990-10-11
申请人： Manzur Gill , Sung-Wei Lin
发明人： Manzur Gill , Sung-Wei Lin
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/7885
摘要： An electrically-erasable, electrically-programmable, read-only memory cell array is formed in pairs at a face of a semiconductor substrate (11). Each memory cell includes a source region (14a) and a shaped drain region (16), with at corresponding channel region (18a) in between. A Fowler-Nordheim tunnel window subregion (15a) of the source region (14a) is located opposite the channel (18a). A floating gate conductor (FG) includes a channel section (32a) and a tunnel window section (34a). The floating gate conductor is formed in two stages, the first stage forming the channel section (32a) from a first-level polysilicon (P1A). This floating gate channel section (32a/P1A) is used as a self-alignment implant mask for the source (14a) and drain (16) regions, such that the channel junction edges are aligned with the coresponding edges of the channel section. A control gate conductor (CG) is disposed over the floating gate conductor (FG), insulated by an intervening interlevel dielectric (ILD). The memory cell is programmed by hot carrier injection from the channel (18a) to the floating-gate channel section (32a), and erased by Fowler-Nordheim tunneling from the floating-gate tunnel window section (34a) to the tunnel window subregion (15a).
摘要翻译：在半导体衬底（11）的表面成对地形成电可擦除的电可编程的只读存储单元阵列。每个存储单元包括源极区域（14a）和形状的漏极区域（16），其间具有相应的沟道区域（18a）。源区域（14a）的福勒 - 诺德海姆隧道窗口（15a）位于与通道（18a）相对的位置。浮动栅极导体（FG）包括通道部分（32a）和隧道窗口部分（34a）。浮栅导体形成为两级，第一级由第一级多晶硅（P1A）形成沟道段（32a）。该浮动栅极沟道部分（32a / P1A）用作源极（14a）和漏极（16）区域的自对准注入掩模，使得沟道连接边缘与沟道部分的相应边缘对准。控制栅极导体（CG）设置在浮动栅极导体（FG）上，由中间层间电介质（ILD）绝缘。通过从信道（18a）到浮动栅极通道部分（32a）的热载流子注入来对存储器单元进行编程，并且通过Fowler-Nordheim从浮动栅极通道窗口部分（34a）向隧道窗口子区域（ 15a）。

73. 发明授权

US5051795A EEPROM with trench-isolated bitlines 失效
标题翻译：具有沟槽隔离位线的EEPROM
公开(公告)号：US5051795A
公开(公告)日：1991-09-24
申请号：US439766
申请日：1989-11-21
申请人： Manzur Gill , Sebastiano D'Arrigo , David J. McElroy
发明人： Manzur Gill , Sebastiano D'Arrigo , David J. McElroy
IPC分类号： H01L21/762 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11517 , H01L21/76202 , H01L27/115 , H01L29/7883
摘要： An electrically-erasable, electrically-programmable ROM or an EEPROM is constructed using a floating-gate transistor with or without a split gate. The floating-gate transistor may have a self-aligned tunnel window of sublithographic dimension positioned on the opposite side of the source from the channel and drain, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. In this cell, the bitlines and source/drain regions are buried beneath relatively thick silicon oxide and the floating gate extends over the thick silicon oxide. Programming and erasing are accomplished by causing electrons to tunnel through the oxide in the tunnel window. The tunnel window has a thinner dielectric than the remainder of the oxides under the floating gate to allow Fowler-Nordheim tunneling. Trenches and ditches are used for electrical isolation between individual memory cells, allowing an increase in cell density.

74. 发明授权

US5032533A Method of making a nonvolatile memory cell with field-plate switch 失效
标题翻译：制造具有场板开关的非易失性存储单元的方法
公开(公告)号：US5032533A
公开(公告)日：1991-07-16
申请号：US444585
申请日：1989-12-04
申请人： Manzur Gill , Sebastiano D'Arrigo
发明人： Manzur Gill , Sebastiano D'Arrigo
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521 , Y10S438/981
摘要： An array of nonvolatile memory cells are formed at a face of a semiconductor body, the cells including source regions and including drain regions that are part of a common drain column conductor. Each cell has first and second sub-channel regions between source and drain. The conductivity of the first sub-channel regions of each cell is controlled by a field-plate conductor formed over and insulated from the first sub-channel region. The conductivity of each of the second sub-channel regions is controlled by a floating-gate conductor formed over and insulated from the second sub-channel region. A row line, including control gates, is located above and insulated from the floating gates of the cells for reading, programming and erasing the cells. The field-plate conductor switch provided isolation of the cells during programming.
摘要翻译：在半导体本体的表面上形成非易失性存储单元的阵列，该单元包括源极区，并且包括作为公共漏极列导体的一部分的漏极区。每个单元在源极和漏极之间具有第一和第二子沟道区。每个单元的第一子沟道区的导电性由形成在第一子沟道区上并与第一子沟道区绝缘的场板导体控制。每个第二子沟道区的导电性由形成在第二子沟道区上并与第二子沟道区绝缘的浮栅导体控制。包括控制栅极的行线位于单元的浮动栅极的上方并与之隔绝，用于读取，编程和擦除单元。场板导体开关在编程期间提供了单元的隔离。

75. 发明授权

US5023680A Floating-gate memory array with silicided buried bitlines and with single-step-defined floating gates 失效
标题翻译：具有硅化掩埋位线和单步定义浮动栅极的浮栅存储器阵列
公开(公告)号：US5023680A
公开(公告)日：1991-06-11
申请号：US269836
申请日：1988-11-10
申请人： Manzur Gill , Howard L. Tigelaar
发明人： Manzur Gill , Howard L. Tigelaar
IPC分类号： H01L27/115 , H01L29/788
CPC分类号： H01L29/7886 , H01L27/115 , H01L29/7881 , H01L29/7883
摘要： A contact-free floating-gate non-volatile memory cell array and process with silicided NSAG bitlines and with source/drain regions buried beneath relatively thick silicon oxide. The bitlines have a relatively small resistance, eliminating the need for parallel metallic conductors with numerous bitline contacts. The array has relatively small bitline capacitance and may be constructed having relatively small dimensions. Isolation between wordlines and between bitlines is by thick field oxide regions. A thick field oxide strip separates each ground conductor/bitline pair. Wordlines may be formed from silicided polycrystalline or other material with low resistivity. Coupling of programming and erasing voltages to the floating gate is improved by extending the gates over the thick field oxide and perhaps by using an insulator with relatively high dielectric constant between the control gate and the floating gate. The four sides of the floating gates are defined with a single patterning step. The resulting structure is a dense cross-point array of programmable memory cells.
摘要翻译：一个无接触的浮栅非易失性存储单元阵列和具有硅化NSAG位线的工艺，以及埋在相对厚的氧化硅之下的源/漏区。位线具有相对较小的电阻，消除了对具有大量位线触点的并行金属导体的需要。阵列具有相对小的位线电容，并且可以构造成具有相对较小的尺寸。字线之间和位线之间的隔离是厚场氧化物区域。一个厚场氧化物条将每个接地导线/位线对分开。字线可以由具有低电阻率的硅化多晶或其它材料形成。通过将栅极扩展到厚场氧化物上并且可能通过在控制栅极和浮置栅极之间使用具有相对高的介电常数的绝缘体来改善编程和擦除电压到浮栅的耦合。浮动栅极的四个侧面被定义为单个图案化步骤。所得到的结构是可编程存储器单元的密集交叉点阵列。

76. 发明授权

US5010028A Method of making hot electron programmable, tunnel electron erasable contactless EEPROM 失效
标题翻译：制造热电子可编程的方法，隧道电子可擦除非接触式EEPROM
公开(公告)号：US5010028A
公开(公告)日：1991-04-23
申请号：US458936
申请日：1989-12-29
申请人： Manzur Gill , Sung-Wei Lin
发明人： Manzur Gill , Sung-Wei Lin
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/7885
摘要： An electrically-erasable, electrically-programmable, read-only memory cell array is formed in pairs at a face of a semiconductor substrate (11). Each memory cell includes a source region (14a) and a shared drain region (16), with a corresponding channel region (18a) in between. A Fowler-Nordheim tunnel window subregion (15a) of the source region (14a) is located opposite the channel (18a). A floating gate conductor (FG) includes a channel section (32a) and a tunnel window section (34a). The floating gate conductor is formed in two stages, the first stage forming the channel section (32a) from a first-level polysilicon (PlA). This floating gate channel section (32a/PlA) is used as a self-alignment implant mask for the source (14a) and drain (16) regions, such that the channel junction edges are aligned with the corresponding edges of the channel section. A control gate conductor (CG) is disposed over the floating gate conductor (FG), insulated by an intervening interlevel dielectric (ILD). The memory cell is programmed by hot carrier injection from the channel (18a) to the floating-gate channel section (32a), and erased by Fowler-Nordheim tunneling from the floating-gate tunnel window section (34a) to the tunnel window subregion (15a).
摘要翻译：在半导体衬底（11）的表面成对地形成电可擦除的电可编程的只读存储单元阵列。每个存储单元包括源极区（14a）和共用漏极区（16），其间具有相应的沟道区（18a）。源区域（14a）的福勒 - 诺德海姆隧道窗口（15a）位于与通道（18a）相对的位置。浮动栅极导体（FG）包括通道部分（32a）和隧道窗口部分（34a）。浮栅导体形成为两级，第一级由第一级多晶硅（PlA）形成沟道段（32a）。该浮动栅极沟道部分（32a / P1A）用作源极（14a）和漏极（16）区域的自对准注入掩模，使得沟道结边缘与沟道部分的对应边缘对准。控制栅极导体（CG）设置在浮动栅极导体（FG）上，由中间层间电介质（ILD）绝缘。通过从信道（18a）到浮动栅极通道部分（32a）的热载流子注入来对存储器单元进行编程，并且通过Fowler-Nordheim从浮动栅极通道窗口部分（34a）向隧道窗口子区域（ 15a）。

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