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71. 发明授权

US06556477B2 Integrated chip having SRAM, DRAM and flash memory and method for fabricating the same 有权
标题翻译：具有SRAM，DRAM和闪速存储器的集成芯片及其制造方法
公开(公告)号：US06556477B2
公开(公告)日：2003-04-29
申请号：US09861788
申请日：2001-05-21
申请人： Louis L. Hsu , Carl Radens , Li-Kong Wang
发明人： Louis L. Hsu , Carl Radens , Li-Kong Wang
IPC分类号： G11C1134
CPC分类号： H01L27/105 , G11C11/005 , H01L27/1052
摘要： A semiconductor memory system fabricated on one substrate is presented including an SRAM device, a DRAM device and a Flash memory device. In one embodiment the SRAM device is a high-resistive load SRAM device. In another embodiment the DRAM device is a deep trench DRAM device. A method is also presented for fabricating the memory system on one substrate having the SRAM device, the DRAM device and the Flash memory device.
摘要翻译：提出了在一个衬底上制造的半导体存储器系统，其包括SRAM器件，DRAM器件和闪存器件。在一个实施例中，SRAM器件是高电阻负载SRAM器件。在另一个实施例中，DRAM器件是深沟槽DRAM器件。还提出了一种用于在具有SRAM器件，DRAM器件和闪存器件的一个衬底上制造存储器系统的方法。

72. 发明授权

US08614115B2 Photovoltaic solar cell device manufacture 失效
标题翻译：光伏太阳能电池器件制造
公开(公告)号：US08614115B2
公开(公告)日：2013-12-24
申请号：US12916236
申请日：2010-10-29
申请人： Lawrence A. Clevenger , Harold J. Hovel , Rainer Klaus Krause , Kevin S. Petrarca , Gerd Pfeiffer , Kevin M. Prettyman , Carl Radens , Brian C. Sapp
发明人： Lawrence A. Clevenger , Harold J. Hovel , Rainer Klaus Krause , Kevin S. Petrarca , Gerd Pfeiffer , Kevin M. Prettyman , Carl Radens , Brian C. Sapp
IPC分类号： H01L21/00 , H01L31/18
CPC分类号： H01L31/022425 , H01L31/068 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A method for manufacturing a photovoltaic solar cell device includes the following. A p-n junction having a first doping density is formed. Formation of the p-n junction is enhanced by introducing a second doping density to form high doped areas for a dual emitter application. The high doped areas are defined by a masking process integrated with the formation of the p-n junction, resulting in a mask pattern of the high doped areas. A metallization of the high doped areas occurs in accordance with the mask pattern of the high doped areas.
摘要翻译：光伏太阳能电池器件的制造方法包括以下。形成具有第一掺杂密度的p-n结。通过引入第二掺杂密度以形成用于双发射器应用的高掺杂区域来增强p-n结的形成。高掺杂区域由与p-n结的形成集成的掩模工艺限定，产生高掺杂区域的掩模图案。根据高掺杂区域的掩模图案发生高掺杂区域的金属化。

73. 发明申请

US20120313144A1 RECESSED GATE FIELD EFFECT TRANSISTOR 有权
标题翻译：闭门控场效应晶体管
公开(公告)号：US20120313144A1
公开(公告)日：2012-12-13
申请号：US13494965
申请日：2012-06-12
申请人： John H. ZHANG , Lawrence A. Clevenger , Carl Radens , Yiheng Xu
发明人： John H. ZHANG , Lawrence A. Clevenger , Carl Radens , Yiheng Xu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66666 , H01L21/28008 , H01L21/84 , H01L27/1203 , H01L29/165 , H01L29/7781
摘要： A semiconductor device having a gate positioned in a recess between the source region and a drain region that are adjacent either side of the gate electrode. A channel region is below a majority of the source region as well as a majority of the drain region and the entire gate electrode.
摘要翻译：一种半导体器件，其具有位于源极区域和漏极区域之间的与栅极电极的两侧相邻的凹部中的栅极。沟道区域低于源极区域的大部分以及漏极区域和整个栅极电极的大部分。

74. 发明授权

US07960237B2 Structure and method for mosfet with reduced extension resistance 有权
标题翻译：具有降低延伸阻力的mosfet的结构和方法
公开(公告)号：US07960237B2
公开(公告)日：2011-06-14
申请号：US12121922
申请日：2008-05-16
申请人： Dureseti Chidambarrao , Carl Radens
发明人： Dureseti Chidambarrao , Carl Radens
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L29/41733 , H01L29/41775 , H01L29/458 , H01L29/6653 , H01L29/7833 , H01L29/78621 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method in which a low-resistance connection between the MOS channel and silicided source/drain regions is provided that has an independence from the extension ion implant process as well as device overlap capacitance. The method of the present invention broadly includes selectively removing outer spacers of an MOS structure and then selectively plating a metallic or intermetallic material on exposed portions of a semiconductor substrate that were previously protected by the outer spacers. The present invention also provides a semiconductor structure that is formed utilizing the method. The semiconductor structure includes a low-resistance connection between the silicided source/drain regions and the channel regions which includes a selectively plated metallic or intermetallic material.
摘要翻译：本发明提供了一种方法，其中提供了与扩展离子注入工艺无关的MOS沟道和硅化源极/漏极区之间的低电阻连接以及器件重叠电容。本发明的方法广泛地包括选择性地去除MOS结构的外部间隔物，然后在先前由外部间隔物保护的半导体衬底的暴露部分上选择性地镀覆金属或金属间化合物。本发明还提供了利用该方法形成的半导体结构。半导体结构包括硅化源/漏区和沟道区之间的低电阻连接，其包括选择性镀金属或金属间化合物。

75. 发明授权

US07906428B2 Modified via bottom structure for reliability enhancement 有权
标题翻译：通过底部结构改进可靠性增强
公开(公告)号：US07906428B2
公开(公告)日：2011-03-15
申请号：US12121216
申请日：2008-05-15
申请人： Lawrence A. Clevenger , Timothy Joseph Dalton , Louis C. Hsu , Conal Eugene Murray , Carl Radens , Kwong-Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Timothy Joseph Dalton , Louis C. Hsu , Conal Eugene Murray , Carl Radens , Kwong-Hon Wong , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/76805 , H01L21/76843 , H01L21/76844 , H01L21/76847 , H01L21/76865 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The present invention provides an interconnect structure that can be made in the BEOL which exhibits good mechanical contact during normal chip operations and does not fail during various reliability tests as compared with the conventional interconnect structures described above. The inventive interconnect structure has a kinked interface at the bottom of a via that is located within an interlayer dielectric layer. Specifically, the inventive interconnect structure includes a first dielectric layer having at least one metallic interconnect embedded within a surface thereof; a second dielectric layer located atop the first dielectric layer, wherein said second dielectric layer has at least one aperture having an upper line region and a lower via region, wherein the lower via region includes a kinked interface; at least one pair of liners located on at least vertical walls of the at least one aperture; and a conductive material filling the at least one aperture.
摘要翻译：本发明提供一种可以在BEOL中制造的互连结构，其在正常的芯片操作期间表现出良好的机械接触，并且在与上述的常规互连结构相比在各种可靠性测试期间不会失败。本发明的互连结构在通孔的底部具有位于层间介质层内的扭结界面。具体地，本发明的互连结构包括：第一介电层，其具有嵌入在其表面内的至少一个金属互连; 位于所述第一介电层顶部的第二电介质层，其中所述第二电介质层具有至少一个具有上线区域和下通孔区域的孔，其中所述下通孔区域包括扭结界面; 位于所述至少一个孔的至少垂直壁上的至少一对衬垫; 以及填充所述至少一个孔的导电材料。

76. 发明授权

US07648871B2 Field effect transistors (FETS) with inverted source/drain metallic contacts, and method of fabricating same 失效
标题翻译：具有反相源极/漏极金属触点的场效应晶体管（FETS）及其制造方法
公开(公告)号：US07648871B2
公开(公告)日：2010-01-19
申请号：US11163523
申请日：2005-10-21
申请人： Michael P. Belyansky , Dureseti Chidambarrao , Lawrence A. Clevenger , Kaushik A. Kumar , Carl Radens
发明人： Michael P. Belyansky , Dureseti Chidambarrao , Lawrence A. Clevenger , Kaushik A. Kumar , Carl Radens
IPC分类号： H01L21/8238
CPC分类号： H01L21/76804 , H01L29/6659 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to an field effect transistor (FET) comprising an inverted source/drain metallic contact that has a lower portion located in a first, lower dielectric layer and an upper portion located in a second, upper dielectric layer. The lower portion of the inverted source/drain metallic contact has a larger cross-sectional area than the upper portion. Preferably, the lower portion of the inverted source/drain metallic contact has a cross-sectional area ranging from about 0.03 μm2 to about 3.15 μm2, and such an inverted source/drain metallic contact is spaced apart from a gate electrode of the FET by a distance ranging from about 0.001 μm to about 5 μm.
摘要翻译：本发明涉及一种场效应晶体管（FET），其包括反向的源极/漏极金属接触，其具有位于第一下部电介质层中的下部和位于第二上部电介质层中的上部。倒置的源极/漏极金属触点的下部具有比上部更大的横截面面积。优选地，反相源极/漏极金属触点的下部具有约0.03mum2至约3.15mum2的横截面积，并且这种反向的源极/漏极金属触点与FET的栅电极间隔开一个距离范围从约0.001毫米到约5毫米。

77. 发明授权

US07528065B2 Structure and method for MOSFET gate electrode landing pad 有权
标题翻译： MOSFET栅极电极着陆焊盘的结构和方法
公开(公告)号：US07528065B2
公开(公告)日：2009-05-05
申请号：US11333068
申请日：2006-01-17
申请人： Lawrence A. Clevenger , Timothy J. Dalton , Louis C. Hsu , Carl Radens , Kwong-Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Timothy J. Dalton , Louis C. Hsu , Carl Radens , Kwong-Hon Wong , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L27/1203 , H01L21/28114 , H01L21/823456 , H01L21/84 , H01L29/42376 , H01L2924/0002 , H01L2924/00
摘要： A transistor device and method of forming the same comprises a substrate; a first gate electrode over the substrate; a second gate electrode over the substrate; and a landing pad comprising a pair of flanged ends overlapping the second gate electrode, wherein the structure of the second gate electrode is discontinuous with the structure of the landing pad.
摘要翻译：晶体管器件及其形成方法包括：衬底; 衬底上的第一栅电极; 在所述衬底上方的第二栅电极; 以及着陆垫，其包括与所述第二栅电极重叠的一对凸缘端，其中所述第二栅极的结构与所述着陆焊盘的结构不连续。

78. 发明申请

US20090111235A1 Semiconductor Integrated Circuit Devices Having High-Q Wafer Back-Side Capacitors 有权
标题翻译：具有高Q晶片背面电容器的半导体集成电路器件
公开(公告)号：US20090111235A1
公开(公告)日：2009-04-30
申请号：US12348707
申请日：2009-01-05
申请人： Lawrence Clevenger , Timothy Joseph Dalton , Louis Hsu , Carl Radens , Vidhya Ramachandran , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence Clevenger , Timothy Joseph Dalton , Louis Hsu , Carl Radens , Vidhya Ramachandran , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L21/02
CPC分类号： H01L21/84 , H01L21/76898 , H01L23/481 , H01L23/5223 , H01L27/1203 , H01L2924/0002 , Y10S438/957 , H01L2924/00
摘要： Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip capacitors formed on the chip back-side and connected to integrated circuits on the chip front-side using through-wafer interconnects. In one aspect, a semiconductor device includes a semiconductor substrate having a front side, a back side, and a buried insulating layer interposed between the front and back sides of the substrate. An integrated circuit is formed on the front side of the semiconductor substrate, an integrated capacitor is formed on the back side of the semiconductor substrate, and an interconnection structure is formed through the buried insulating layer to connect the integrated capacitor to the integrated circuit.
摘要翻译：提供了用于制造半导体IC（集成电路）芯片的半导体IC（集成电路）芯片，其具有形成在芯片背面的高Q片上电容器，并使用晶片间互连连接到芯片正面的集成电路。在一个方面，半导体器件包括一个半导体衬底，该半导体衬底具有介于衬底的正面和背面之间的正面，背面和掩埋绝缘层。在半导体基板的正面形成有集成电路，在半导体基板的背面形成有集成电容器，通过埋入绝缘层形成互连结构，将集成电容器与集成电路连接起来。

79. 发明申请

US20080308801A1 STRUCTURE FOR STOCHASTIC INTEGRATED CIRCUIT PERSONALIZATION 失效
标题翻译： STOCHASTIC集成电路个性化结构
公开(公告)号：US20080308801A1
公开(公告)日：2008-12-18
申请号：US12193288
申请日：2008-08-18
申请人： Lawrence A. Clevenger , Matthew E. Colburn , Timothy J. Dalton , Michael C. Gaidis , Louis L. C. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Matthew E. Colburn , Timothy J. Dalton , Michael C. Gaidis , Louis L. C. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L23/58
CPC分类号： H01L23/576 , H01L21/31144 , H01L23/544 , H01L28/20 , H01L28/40 , H01L2223/54433 , H01L2223/5444 , H01L2924/0002 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/00
摘要： A method of forming a stochastically based integrated circuit encryption structure includes forming a lower conductive layer over a substrate, forming a short prevention layer over the lower conductive layer, forming an intermediate layer over the short prevention layer, wherein the intermediate layer is characterized by randomly structured nanopore features. An upper conductive layer is formed over the random nanopore structured intermediate layer. The upper conductive layer is patterned into an array of individual cells, wherein a measurable electrical parameter of the individual cells has a random distribution from cell to cell with respect to a reference value of the electrical parameter.
摘要翻译：一种形成随机的集成电路加密结构的方法包括在衬底上形成下导电层，在下导电层上形成防短层，在短路防护层上形成中间层，其中中间层的特征是随机结构纳米孔特征。在无规纳米孔结构化中间层上形成上导电层。上导电层被图案化成单个单元的阵列，其中各个单元的可测量电参数相对于电参数的参考值具有从单元到单元的随机分布。

80. 发明授权

US07447273B2 Redundancy structure and method for high-speed serial link 失效
标题翻译：用于高速串行链路的冗余结构和方法
公开(公告)号：US07447273B2
公开(公告)日：2008-11-04
申请号：US10708240
申请日：2004-02-18
申请人： Louis L. Hsu , Carl Radens , Li-Kong Wang
发明人： Louis L. Hsu , Carl Radens , Li-Kong Wang
IPC分类号： H01L21/82 , H01P1/10
CPC分类号： H04L1/22 , H04L25/029 , H04L25/08
摘要： An integrated circuit is provided having a plurality of data transmitters, including a plurality of default data transmitters for transmitting data from a plurality of data sources and at least one redundancy data transmitter. A plurality of connection elements are provided having a first, low impedance connecting state and having a second, high impedance, disconnecting state. The connection elements are operable to disconnect a failing data transmitter from a corresponding output signal line and to connect the redundancy data transmitter to that output signal line in place of the failing data transmitter. In one preferred form, the connection elements include a fuse and an antifuse. In another form, the connection elements include micro-electromechanical (MEM) switches. The connecting elements preferably present the low impedance connecting state at frequencies which include signal switching frequencies above about 500 MHz.
摘要翻译：提供了具有多个数据发送器的集成电路，包括用于从多个数据源发送数据的多个默认数据发送器和至少一个冗余数据发送器。提供了具有第一低阻抗连接状态并且具有第二高阻抗断开状态的多个连接元件。连接元件可操作以将故障数据发射器与相应的输出信号线断开连接，并将冗余数据发射器连接到该输出信号线来代替故障数据发射器。在一个优选形式中，连接元件包括保险丝和反熔丝。在另一种形式中，连接元件包括微机电（MEM）开关。连接元件优选地在包括高于约500MHz的信号切换频率的频率处呈现低阻抗连接状态。

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