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    • 72. 发明授权
    • Information processing apparatus and information processing method, and non-transitory computer readable medium storing information processing program
    • 信息处理装置和信息处理方法以及存储信息处理程序的非暂时性计算机可读介质
    • US08942310B2
    • 2015-01-27
    • US13881569
    • 2011-11-29
    • Tetsuhiko MiyataniToshifumi Sato
    • Tetsuhiko MiyataniToshifumi Sato
    • H04L27/00H04B7/04H04B7/06
    • H04B7/0408H04B7/0417H04B7/043H04B7/0465H04B7/0617H04B7/0691H04B7/10
    • Transmission channel estimation is performed for NT×NR reception signals and estimated transmission channel values are thereby output. The estimated transmission channel values are divided into N groups of NT×M estimated transmission channel values and a covariance matrix with M rows and N columns is obtained for each of the estimated transmission channel value groups. The N covariance matrixes are averaged over a predetermined range in terms of at least a time or a frequency (first averaging). Eigenvectors are generated based on respective N averaging outputs. Transmission channels between base station antennas and terminal antennas are generated from the eigenvectors and the estimated transmission channel values. Covariance matrixes are obtained for the generated transmission channels. The covariance matrixes are averaged over a different range from the range used in the first averaging (second averaging) and a beam forming weight is obtained by combining the generated eigenvectors.
    • 对NT×NR个接收信号进行发送信道估计,从​​而输出估计的发送信道值。 估计的传输信道值被划分成N组的NT×M个估计的传输信道值,并且对于每个估计的传输信道值组获得具有M行和N列的协方差矩阵。 在至少一个时间或频率(第一平均)方面,N个协方差矩阵在预定范围内被平均化。 基于相应的N个平均输出产生特征向量。 基站天线和终端天线之间的传输信道是从特征向量和估计的传输信道值产生的。 对于所生成的传输信道获得协方差矩阵。 协方差矩阵在与第一平均(第二平均)中使用的范围不同的范围内进行平均,并且通过组合生成的特征向量来获得波束形成权重。
    • 75. 发明授权
    • Digital processing monitoring device
    • 数字处理监控装置
    • US08331521B2
    • 2012-12-11
    • US12957991
    • 2010-12-01
    • Masataka YanagisawaToshifumi Sato
    • Masataka YanagisawaToshifumi Sato
    • G21C17/10
    • G21C17/108G05B23/0213G05B2219/21109G21D3/008Y02E30/40
    • According to an embodiment, a digital process type monitor device includes a plurality of modules and a mother board connected to each of the modules. Each module includes: a base board connected to a connector and having an FPGA for main control and an IPGA for sub board control mounted thereon; and a sub board for a main-machine I/F process, having an FPGA for an I/F process mounted hereon. Each sub board has storage devices for storing man-machine I/F information on the sub board. Each of the FPGA writes transmission data into a predetermined region of a transmission area and has a common transmission protocol to share the transmission data between the respective modules.
    • 根据实施例,数字处理型监视器装置包括多个模块和连接到每个模块的母板。 每个模块包括:连接到连接器的基板,具有用于主控制的FPGA和安装在其上的用于子板控制的IPGA; 以及用于主机I / F处理的子板,其具有安装在其上的I / F处理的FPGA。 每个子板具有用于在子板上存储人机I / F信息的存储装置。 每个FPGA将传输数据写入到传输区域的预定区域中,并且具有共同的传输协议以共享各个模块之间的传输数据。
    • 79. 发明授权
    • Method for verifying safety apparatus and safety apparatus verified by the same
    • 用于验证其验证的安全装置和安全装置的方法
    • US07512917B2
    • 2009-03-31
    • US11360617
    • 2006-02-24
    • Mikio IzumiToshifumi HayashiShigeru OdanakaHirotaka SakaiNaotaka OdaToshifumi SatoToshiaki Ito
    • Mikio IzumiToshifumi HayashiShigeru OdanakaHirotaka SakaiNaotaka OdaToshifumi SatoToshiaki Ito
    • G06F17/50
    • G06F17/5027
    • A verification method is provided for verifying a safety apparatus including a programmable logic device having a plurality of functional elements. The verification method includes the steps of exhaustively verifying the plurality of functional elements on actual hardware, generating a functional element that is the same as one of the functional elements verified on the actual apparatus using a predetermined hardware description language, independently logic-synthesizing each generated functional element into a plurality of first net lists, generating a connection function between the functional elements using the predetermined hardware description language, logic-synthesizing the generated connection function into a second net list corresponding to the connection function, synthesizing the first net lists with the second net list to generate a third net list, writing a logic circuit into the programmable logic device on the basis of the third net list, and verifying the actual programmable logic device.
    • 提供了一种用于验证包括具有多个功能元件的可编程逻辑器件的安全装置的验证方法。 验证方法包括以下步骤:在实际硬件上彻底验证多个功能元件,生成与使用预定的硬件描述语言在实际装置上验证的功能元件中的一个功能元件相同的功能元件,独立地逻辑合成每个产生的功能元件 功能元件组合成多个第一网络列表,使用预定的硬件描述语言在功能元件之间生成连接功能,将生成的连接功能逻辑合成到与连接功能相对应的第二网络列表中,将第一网络列表与 第二网络列表以产生第三网络列表,基于第三网络列表将逻辑电路写入可编程逻辑设备,以及验证实际的可编程逻辑设备。
    • 80. 发明授权
    • Double-sided silent chain
    • 双面无声链
    • US07476170B2
    • 2009-01-13
    • US11151502
    • 2005-06-13
    • Toshitaka OgoToshifumi Sato
    • Toshitaka OgoToshifumi Sato
    • F16G13/02
    • F16G13/04
    • In a double-sided silent chain, the backs of the outermost link plates, which have their teeth protruding in one direction, are higher than the backs of the inner link plates, which have their teeth protruding in the opposite direction. The backs of the outer link plates adjacent the outermost link plates may also be higher than the backs of the inner link plates, and are preferably equal to the heights of the backs of the outermost link plates. The outermost link plates and their adjacent outer link plates are preferably of the outer tooth contact/outer tooth seating type.
    • 在双面无声链条中,具有沿一个方向突出的齿的最外侧连接板的背部比内侧连接板的背面高,其内侧链条的齿沿相反方向突出。 邻近最外侧链板的外链板的背面也可以高于内链板的背面,并且最好等于最外链板的背部的高度。 最外面的链板及其相邻的外链板优选为外齿接触/外齿座位型。