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71. 发明申请

US20100140715A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20100140715A1
公开(公告)日：2010-06-10
申请号：US12630018
申请日：2009-12-03
申请人： Kazutoshi Nakamura , Norio Yasuhara
发明人： Kazutoshi Nakamura , Norio Yasuhara
IPC分类号： H01L27/06
CPC分类号： H01L29/0692 , H01L29/0653 , H01L29/0847 , H01L29/402 , H01L29/404 , H01L29/405 , H01L29/41725 , H01L29/41758 , H01L29/41775 , H01L29/42376 , H01L29/7835 , H02M3/1588 , Y02B70/1466
摘要： A semiconductor device includes: a semiconductor region of first conductivity type provided in a semiconductor layer of first conductivity type; a first semiconductor region of second conductivity type; a second semiconductor region of second conductivity type; a third semiconductor region of second conductivity type having a lower impurity concentration than the second semiconductor region of second conductivity type; a first insulating layer provided in the third semiconductor region of second conductivity type; a control electrode provided on the semiconductor region of first conductivity type via a second insulating layer; a first auxiliary electrode provided on the first insulating layer; a first main electrode electrically connected to the first semiconductor region of second conductivity type; and a second main electrode electrically connected to the second semiconductor region of second conductivity type.
摘要翻译：半导体器件包括：设置在第一导电类型的半导体层中的第一导电类型的半导体区域; 第二导电类型的第一半导体区域; 第二导电类型的第二半导体区域; 具有比第二导电类型的第二半导体区域低的杂质浓度的第二导电类型的第三半导体区域; 设置在第二导电类型的第三半导体区域中的第一绝缘层; 经由第二绝缘层设置在第一导电类型的半导体区上的控制电极; 设置在所述第一绝缘层上的第一辅助电极; 电连接到第二导电类型的第一半导体区域的第一主电极; 以及电连接到第二导电类型的第二半导体区域的第二主电极。

72. 发明授权

US5894164A High voltage semiconductor device 失效
标题翻译：高压半导体器件
公开(公告)号：US5894164A
公开(公告)日：1999-04-13
申请号：US927691
申请日：1997-09-11
申请人： Hideyuki Funaki , Akio Nakagawa , Norio Yasuhara , Yoshinori Terazaki
发明人： Hideyuki Funaki , Akio Nakagawa , Norio Yasuhara , Yoshinori Terazaki
IPC分类号： H01L29/06 , H01L29/739 , H01L29/72
CPC分类号： H01L29/7394 , H01L29/0696
摘要： A lateral IGBT has a n-source layer and a p-contact layer both in contact with a source electrode. The source layer has a trunk adjacent to a channel region under a gate electrode, and a plurality of branches extending from its trunk to the source electrode to be in contact with the source electrode. The contact layer has a trunk in contact with the source electrode, and a plurality of branches extending from its trunk to the source layer trunk The source layer branches and the contact layer branches have shapes complementary with each other and are alternately arranged. The source layer trunk has a width La in an X direction (channel direction), which satisfies a condition, 0.5 .mu.m
摘要翻译：横向IGBT具有与源电极接触的n源层和p接触层。源极层具有与栅电极下方的沟道区域相邻的中继线，以及从其主干延伸到源极电极与源极电极接触的多个分支。接触层具有与源电极接触的干线，以及从其干线延伸到源层干线的多个分支。源极层分支和接触层分支具有彼此互补的形状并交替布置。源层干线在X方向（沟道方向）上具有宽度La，满足0.5μm

73. 发明授权

US5838026A Insulated-gate semiconductor device 失效
标题翻译：绝缘栅半导体器件
公开(公告)号：US5838026A
公开(公告)日：1998-11-17
申请号：US827530
申请日：1997-03-28
申请人： Mitsuhiko Kitagawa , Ichiro Omura , Akio Nakagawa , Norio Yasuhara , Tomoki Inoue
发明人： Mitsuhiko Kitagawa , Ichiro Omura , Akio Nakagawa , Norio Yasuhara , Tomoki Inoue
IPC分类号： H01L29/06 , H01L29/423 , H01L29/739 , H01L29/745 , H01L21/36
CPC分类号： H01L29/7455 , H01L29/7394 , H01L29/7397 , H01L29/7398 , H01L29/0696 , H01L29/4236
摘要： An insulated-gate semiconductor device comprises a P type emitter layer, an N.sup.- high-resistive base layer formed on the P type emitter layer, and a P type base layer contacting the N.sup.- high-resistive base layer. A plurality of trenches are formed having a depth to reach into the N.sup.- high-resistive base layer from the P type base layer. A gate electrode covered with a gate insulation film is buried in each trench. An N type source layer to be connected to a cathode electrode is formed in the surface of the P type base layer in a channel region between some trenches, thereby forming an N channel MOS transistor for turn-on operation. A P channel MOS transistor connected to the P base layer is formed in a channel region between other trenches so as to discharge the holes outside the device upon turn-off operation.
摘要翻译：绝缘栅半导体器件包括P型发射极层，形成在P型发射极层上的N-高电阻基极层和与N型高电阻基极层接触的P型基极层。形成从P型基底层到达N个高电阻基底层的深度的多个沟槽。覆盖有栅极绝缘膜的栅电极被埋在每个沟槽中。在一些沟槽之间的沟道区域中，在P型基极层的表面形成有与阴极连接的N型源极层，从而形成用于导通工作的N沟道MOS晶体管。连接到P基极层的P沟道MOS晶体管形成在其它沟槽之间的沟道区域中，以便在关断操作时将器件的孔排出。

74. 发明授权

US5585651A Insulated-gate semiconductor device having high breakdown voltages 失效
标题翻译：具有高击穿电压的绝缘栅半导体器件
公开(公告)号：US5585651A
公开(公告)日：1996-12-17
申请号：US487508
申请日：1995-06-07
申请人： Mitsuhiko Kitagawa , Ichiro Omura , Akio Nakagawa , Norio Yasuhara , Tomoki Inoue
发明人： Mitsuhiko Kitagawa , Ichiro Omura , Akio Nakagawa , Norio Yasuhara , Tomoki Inoue
IPC分类号： H01L29/06 , H01L29/423 , H01L29/739 , H01L29/745 , H01L29/74 , H01L31/111
CPC分类号： H01L29/7455 , H01L29/7394 , H01L29/7397 , H01L29/7398 , H01L29/0696 , H01L29/4236
摘要： An insulated-gate semiconductor device comprises a p type emitter layer, an N.sup.- high-resistive base layer formed on the P type emitter layer, and a P type base layer contacting the N.sup.- high-resistive base layer. A plurality of trenches are formed having a depth to reach into the N.sup.- high-resistive base layer from the P type base layer. A gate electrode covered with a gate insulation film is buried in each trench. An N type source layer to be connected to a cathode electrode is formed in the surface of the P type base layer in a channel region between some trenches, thereby forming an N channel MOS transistor for turn-on operation. A P channel MOS transistor connected to the P base layer is formed in a channel region between other trenches so as to discharge the holes outside the device upon turn-off operation.
摘要翻译：绝缘栅半导体器件包括p型发射极层，在P型发射极层上形成的N-高电阻基极层和与N型高电阻基极层接触的P型基极层。形成从P型基底层到达N个高电阻基底层的深度的多个沟槽。覆盖有栅极绝缘膜的栅电极被埋在每个沟槽中。在一些沟槽之间的沟道区域中，在P型基极层的表面形成有与阴极连接的N型源极层，从而形成用于导通工作的N沟道MOS晶体管。连接到P基极层的P沟道MOS晶体管形成在其它沟槽之间的沟道区域中，以便在关断操作时将器件的孔排出。

75. 发明授权

US5448083A Insulated-gate semiconductor device 失效
标题翻译：绝缘栅半导体器件
公开(公告)号：US5448083A
公开(公告)日：1995-09-05
申请号：US261384
申请日：1994-06-15
申请人： Mitsuhiko Kitagawa , Ichiro Omura , Akio Nakagawa , Norio Yasuhara , Tomoki Inoue
发明人： Mitsuhiko Kitagawa , Ichiro Omura , Akio Nakagawa , Norio Yasuhara , Tomoki Inoue
IPC分类号： H01L29/06 , H01L29/423 , H01L29/739 , H01L29/745 , H01L21/36 , H01L21/74
CPC分类号： H01L29/7455 , H01L29/7394 , H01L29/7397 , H01L29/7398 , H01L29/0696 , H01L29/4236
摘要： An insulated-gate semiconductor device comprises a P type emitter layer, an N.sup.- high-resistive base layer formed on the P type emitter layer, and a P type base layer contacting the N.sup.- high-resistive base layer. A plurality of trenches are formed having a depth to reach into the N.sup.- high-resistive base layer from the P type base layer. A gate electrode covered with a gate insulation film is buried in each trench. An N type source layer to be connected to a cathode electrode is formed in the surface of the P type base layer in a channel region between some trenches, thereby-forming an N channel MOS transistor for turn-on operation. A P channel MOS transistor connected to the P base layer is formed in a channel region between other trenches so as to discharge the holes outside the device upon turn-off operation.
摘要翻译：绝缘栅半导体器件包括P型发射极层，形成在P型发射极层上的N-高电阻基极层和与N型高电阻基极层接触的P型基极层。形成从P型基底层到达N个高电阻基底层的深度的多个沟槽。覆盖有栅极绝缘膜的栅电极被埋在每个沟槽中。在一些沟槽之间的沟道区域中，在P型基极层的表面上形成与阴极连接的N型源极层，从而形成用于导通工作的N沟道MOS晶体管。连接到P基极层的P沟道MOS晶体管形成在其它沟槽之间的沟道区域中，以便在关断操作时将器件的孔排出。

76. 发明授权

US5378920A High breakdown voltage semiconductor device 失效
标题翻译：高击穿电压半导体器件
公开(公告)号：US5378920A
公开(公告)日：1995-01-03
申请号：US85055
申请日：1993-07-02
申请人： Akio Nakagawa , Norio Yasuhara
发明人： Akio Nakagawa , Norio Yasuhara
IPC分类号： H01L21/336 , H01L21/74 , H01L21/762 , H01L27/06 , H01L27/092 , H01L27/12 , H01L29/06 , H01L29/40 , H01L29/739 , H01L29/74 , H01L29/745 , H01L29/749 , H01L29/78 , H01L29/786 , H01L29/861
CPC分类号： H01L29/7824 , H01L21/74 , H01L21/76264 , H01L21/76297 , H01L27/0623 , H01L27/0922 , H01L27/1203 , H01L29/404 , H01L29/405 , H01L29/407 , H01L29/408 , H01L29/66772 , H01L29/7394 , H01L29/7436 , H01L29/7455 , H01L29/749 , H01L29/7835 , H01L29/78624 , H01L29/8611 , H01L21/76275 , H01L21/76286 , H01L29/402
摘要： A high breakdown voltage semiconductor device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a first semiconductor region formed on the first insulating film, a second semiconductor region of a first conductivity type having an impurity concentration higher than that of the first semiconductor region and selectively formed on a surface portion of the first semiconductor region, a third semiconductor region having an impurity concentration lower than that of the second semiconductor region and formed on the surface portion of the first semiconductor region so as to be adjacent to or near the second semiconductor region and a fourth semiconductor region of a second conductivity type having an impurity concentration higher than that of the first semiconductor region and formed on the surface portion of the first semiconductor region so as to be outside the third semiconductor region. A fifth semiconductor region having an impurity concentration lower than that of the second or fourth semiconductor region is formed on a bottom portion of the first semiconductor region. When a reverse bias is applied between the second and fourth semiconductor regions, a depletion layer extends vertically in the first semiconductor region and laterally in the fifth semiconductor region. The applied voltage is divided in both the directions and a high breakdown voltage can be obtained.
摘要翻译：高耐压电压半导体器件包括半导体衬底，形成在半导体衬底上的第一绝缘膜，形成在第一绝缘膜上的第一半导体区域，具有高于第一绝缘膜的杂质浓度的第一导电类型的第二半导体区域第一半导体区域，并且选择性地形成在第一半导体区域的表面部分上，第三半导体区域具有杂质浓度低于第二半导体区域的杂质浓度，并形成在第一半导体区域的表面部分上，以便邻近或在第二半导体区域附近形成杂质浓度高于第一半导体区域的第二导电类型的第四半导体区域，并且形成在第一半导体区域的表面部分上，以便在第三半导体区域的外部。在第一半导体区域的底部形成有杂质浓度低于第二或第四半导体区域的第五半导体区域。当在第二和第四半导体区域之间施加反向偏压时，耗尽层在第一半导体区域中垂直延伸并且在第五半导体区域中横向延伸。施加的电压在两个方向上被分割，并且可以获得高的击穿电压。

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