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71. 发明授权

US07701064B2 Apparatus for improved power distribution in a three dimensional vertical integrated circuit 有权
标题翻译：用于改进三维垂直集成电路中功率分配的装置
公开(公告)号：US07701064B2
公开(公告)日：2010-04-20
申请号：US11930409
申请日：2007-10-31
申请人： Todd Alan Christensen , John Edward Sheets, II
发明人： Todd Alan Christensen , John Edward Sheets, II
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L23/02 , H01L23/04
CPC分类号： H01L23/5286 , H01L21/6835 , H01L23/481 , H01L25/0657 , H01L2221/6834 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/3025 , H01L2924/00
摘要： A first through via is electrically insulated from surrounding wafer substrate material. A second through via is not electrically insulated from the surrounding wafer substrate material. This configuration is advantageous when the non-insulated via serves as the path for either Vdd or GND. By not insulating the through via, a first supply voltage (Vdd or GND) is allowed to flow through the surrounding wafer substrate material thereby decreasing the resistance of the first supply voltage path.
摘要翻译：第一通孔与周围的晶片基板材料电绝缘。第二通孔不与周围的晶片基板材料电绝缘。当非绝缘通孔用作Vdd或GND的路径时，这种配置是有利的。通过不使通孔绝缘，允许第一电源电压（Vdd或GND）流过周围的晶片基板材料，从而降低第一电源电压路径的电阻。

72. 发明申请

US20100019385A1 Implementing Reduced Hot-Spot Thermal Effects for SOI Circuits 审中-公开
标题翻译：实现SOI电路降低热点热效应
公开(公告)号：US20100019385A1
公开(公告)日：2010-01-28
申请号：US12178029
申请日：2008-07-23
申请人： Gerald Keith Bartley , Todd Alan Christensen , Paul Eric Dahlen , John Edward Sheets, II
发明人： Gerald Keith Bartley , Todd Alan Christensen , Paul Eric Dahlen , John Edward Sheets, II
IPC分类号： H01L21/71 , H01L23/34
CPC分类号： H01L23/3677 , H01L21/76898 , H01L21/84 , H01L23/481 , H01L27/1203 , H01L29/78603 , H01L29/78606 , H01L29/78639 , H01L2924/0002 , H01L2924/00
摘要： Methods and structures are provided for implementing reduced hot spot thermal effects for silicon-on-insulator (SOI) circuits. A silicon-on-insulator (SOI) structure includes a silicon substrate layer, a thin buried oxide (BOX) layer carried by the silicon substrate layer, an active layer carried by the thin BOX layer, and a pad oxide layer carried by the active layer. A thermal conductive path is built to reduce thermal effects of a hotspot area in the active layer and extends from the active layer to the backside of the SOI structure. A trench etched from the topside to the active layer, and is filled with a thermal connection material. A thermal connection from a backside of the SOI structure includes an opening etched into the silicon substrate layer from the backside and filled with a thermal connection material.
摘要翻译：提供了用于实现绝缘体上硅（SOI）电路的减少热点热效应的方法和结构。绝缘体上硅（SOI）结构包括硅衬底层，由硅衬底层承载的薄掩埋氧化物（BOX）层，由薄BOX层承载的有源层和由活性层承载的衬垫氧化物层层。建立导热路径以减少有源层中的热点区域的热效应并且从有源层延伸到SOI结构的背面。从顶部蚀刻到有源层的沟槽，并填充有热连接材料。来自SOI结构的背面的热连接包括从背面蚀刻到硅衬底层中并且填充有热连接材料的开口。

73. 发明申请

US20090174457A1 IMPLEMENTING LOW POWER LEVEL SHIFTER FOR HIGH PERFORMANCE INTEGRATED CIRCUITS 审中-公开
标题翻译：实现高性能集成电路的低功率电平变换器
公开(公告)号：US20090174457A1
公开(公告)日：2009-07-09
申请号：US11970624
申请日：2008-01-08
申请人： Derick Gardner Behrends , Todd Alan Christensen , Travis Reynold Hebig
发明人： Derick Gardner Behrends , Todd Alan Christensen , Travis Reynold Hebig
IPC分类号： H03L5/00
CPC分类号： H03K3/356165 , H03K3/012
摘要： A low power level shifter circuit for high performance integrated circuits includes an input inverter operating in a domain of a first voltage supply and receiving an input signal and a design structure on which the subject circuit resides is provided. An output stage operating in a domain of a higher second voltage supply includes a first output inverter connected to the input inverter and a second output inverter connected in series with the first output inverter. The second output inverter provides a level shifted output signal having a voltage level corresponding to the second voltage supply. A series connected finisher transistor and finisher control transistor are connected between the second voltage supply and an input to the first output inverter. The finisher control transistor is activated responsive to the input signal. A path control transistor controls a path between the first voltage supply and the input inverter. The path control transistor being activated responsive to the level shifted output signal.
摘要翻译：用于高性能集成电路的低功率电平移位器电路包括在第一电压源的区域中操作并接收输入信号的输入反相器和设置有被摄体电路的设计结构。在较高的第二电压源的区域中工作的输出级包括连接到输入反相器的第一输出反相器和与第一输出反相器串联连接的第二输出反相器。第二输出反相器提供具有对应于第二电压源的电压电平的电平移位输出信号。串联连接的整流晶体管和整流器控制晶体管连接在第二电压源和与第一输出反相器的输入端之间。整理器控制晶体管响应于输入信号被激活。路径控制晶体管控制第一电压源和输入反相器之间的路径。路径控制晶体管响应于电平移位的输出信号被激活。

74. 发明授权

US07525367B2 Method for implementing level shifter circuits for integrated circuits 失效
标题翻译：实现集成电路电平转换电路的方法
公开(公告)号：US07525367B2
公开(公告)日：2009-04-28
申请号：US11538967
申请日：2006-10-05
申请人： Derick Gardner Behrends , Todd Alan Christensen , Travis Reynold Hebig
发明人： Derick Gardner Behrends , Todd Alan Christensen , Travis Reynold Hebig
IPC分类号： H04L5/00
CPC分类号： H03K19/094 , H03K19/018521
摘要： A low power level shifter circuit includes an input inverter operating in a domain of a first voltage supply. The input inverter receives an input signal and provides a first inverted signal. An output inverter operating in a domain of a second voltage supply coupled to the input inverter and provides an output signal having a voltage level corresponding to the second voltage supply and a logic value corresponding to the input signal. The second voltage supply is higher than the first voltage supply. A leakage current control circuit includes a finisher transistor connected between the second voltage supply and the input to the output inverter and a path control transistor control a path between the first voltage supply and the input inverter.
摘要翻译：低功率电平移位器电路包括在第一电压源的域中操作的输入反相器。输入反相器接收输入信号并提供第一反相信号。输出反相器，其在与输入反相器耦合的第二电压源的区域中工作，并提供具有与第二电压源相对应的电压电平的输出信号和对应于输入信号的逻辑值。第二电压源高于第一电压源。泄漏电流控制电路包括连接在第二电压源和输出反相器的输入端之间的整流晶体管，并且路径控制晶体管控制第一电压源与输入反相器之间的路径。

75. 发明申请

US20090027946A1 METHOD AND APPARATUS FOR IMPLEMENTING ENHANCED SRAM READ PERFORMANCE SORT RING OSCILLATOR (PSRO) 有权
标题翻译：实现增强SRAM读取性能分析振荡器（PSRO）的方法和设备
公开(公告)号：US20090027946A1
公开(公告)日：2009-01-29
申请号：US11782808
申请日：2007-07-25
申请人： Chad Allen Adams , Todd Alan Christensen , Travis Reynold Hebig , Kirk David Peterson
发明人： Chad Allen Adams , Todd Alan Christensen , Travis Reynold Hebig , Kirk David Peterson
IPC分类号： G11C11/00
CPC分类号： G11C11/413 , G11C11/41 , G11C11/419 , G11C2029/0403
摘要： A method and apparatus including a static random access memory (SRAM) cell implement an enhanced SRAM read performance sort ring oscillator (PSRO). A pair of parallel reverse polarity connected inverters defines a static latch or cross-coupled memory cell. The SRAM cell includes independent left and right wordlines providing a respective gate input to a pair of access transistors used to access to the memory cell. The SRAM cell includes a voltage supply connection to one side of the static latch. For example, a complement side of the static latch is connected to the voltage supply. A plurality of the SRAM cells is assembled together to form a SRAM base block. A plurality of the SRAM base blocks is connected together to form the SRAM read PSRO.
摘要翻译：包括静态随机存取存储器（SRAM）单元的方法和装置实现增强型SRAM读取性能排序环形振荡器（PSRO）。一对并联反极性连接的反相器定义了静态锁存器或交叉耦合存储器单元。 SRAM单元包括独立的左和右字线，为用于访问存储单元的一对存取晶体管提供相应的栅极输入。 SRAM单元包括到静态锁存器的一侧的电压供应连接。例如，静态锁存器的补码侧连接到电源。多个SRAM单元组装在一起以形成SRAM基块。多个SRAM基块被连接在一起以形成SRAM读取PSRO。

76. 发明授权

US07317217B2 Semiconductor scheme for reduced circuit area in a simplified process 失效
标题翻译：减少电路面积的半导体方案
公开(公告)号：US07317217B2
公开(公告)日：2008-01-08
申请号：US10944626
申请日：2004-09-17
申请人： Todd Alan Christensen , Richard Lee Donze , William Paul Hovis , Terrance Wayne Kueper , John Edward Sheets, II
发明人： Todd Alan Christensen , Richard Lee Donze , William Paul Hovis , Terrance Wayne Kueper , John Edward Sheets, II
IPC分类号： H01L29/76
CPC分类号： H01L21/28518 , H01L21/76889 , H01L21/76895 , H01L29/458 , H01L29/785
摘要： An apparatus and method are disclosed for an improved semiconductor interconnect scheme using a simplified process. In an embodiment of the apparatus, a polysilicon shape is formed on a silicon area. The polysilicon shape is created having a bridging vertex. When a spacer is created on the polysilicon shape, the spacer width is formed to be small enough near the bridging vertex to allow a silicide bridge to form that creates an electrical coupling between the silicon area and the bridging vertex. Semiconductor devices and circuits are created using the improved semiconductor interconnect scheme using the simplified process.
摘要翻译：公开了一种使用简化过程的改进的半导体互连方案的装置和方法。在该装置的实施例中，在硅区域上形成多晶硅形状。产生具有桥接顶点的多晶硅形状。当在多晶硅形状上形成间隔物时，在桥接顶点附近形成足够小的间隔物宽度，以形成硅化物桥，从而在硅区域和桥接顶点之间产生电耦合。使用简化的工艺使用改进的半导体互连方案创建半导体器件和电路。

77. 发明授权

US06774734B2 Ring oscillator circuit for EDRAM/DRAM performance monitoring 有权
标题翻译：环形振荡器电路用于EDRAM / DRAM性能监控
公开(公告)号：US06774734B2
公开(公告)日：2004-08-10
申请号：US10306200
申请日：2002-11-27
申请人： Todd Alan Christensen , Terrance Wayne Kueper , John Edward Sheets, II
发明人： Todd Alan Christensen , Terrance Wayne Kueper , John Edward Sheets, II
IPC分类号： H03B100
CPC分类号： G11C29/12015 , G11C7/22 , G11C7/222 , G11C11/401 , G11C29/02 , G11C29/50 , G11C29/50012 , G11C2029/0401 , H03K3/0315
摘要： Circuitry and methods are disclosed for quantitatively characterizing the delay of Embedded Dynamic Random Access Memory (EDRAM) and Dynamic Random Access Memory (DRAM). The performance critical portion of the memory is placed in a ring oscillator designed such that the delay through the portion, from a rising input to the memory to a rising output, can be accurately determined. Recently, such memory elements have begun to be implemented on chips along with high-speed logic circuitry. However, the performance characteristics of the memory elements do not track the performance characteristics of the logic circuitry. The current invention allows the memory performance to be characterized along with, or separately from, characterization of the logic circuitry.
摘要翻译：公开了用于定量表征嵌入式动态随机存取存储器（EDRAM）和动态随机存取存储器（DRAM）的延迟的电路和方法。存储器的性能关键部分放置在环形振荡器中，该环形振荡器被设计成使得可以准确地确定从上升输入到存储器到上升输出的部分的延迟。最近，这种存储元件已经开始在芯片上与高速逻辑电路一起实现。然而，存储器元件的性能特征不跟踪逻辑电路的性能特性。本发明允许存储器性能与逻辑电路的表征一起被描述或者与其分开。

78. 发明授权

US06528853B2 Method and semiconductor structure for implementing dual plane body contacts for silicon-on-insulator (SOI) transistors 失效
标题翻译：用于实现绝缘体上硅（SOI）晶体管的双平面体接触的方法和半导体结构
公开(公告)号：US06528853B2
公开(公告)日：2003-03-04
申请号：US09870754
申请日：2001-05-31
申请人： Todd Alan Christensen , John Edward Sheets, II
发明人： Todd Alan Christensen , John Edward Sheets, II
IPC分类号： H01L2701
CPC分类号： H01L29/78696 , H01L21/76264 , H01L21/76267 , H01L21/76283 , H01L29/0653 , H01L29/7841 , H01L29/78603 , H01L29/78606
摘要： A method and semiconductor structure are provided for implementing dual plane body contacts for silicon-on-insulator (SOI) transistors. A bulk silicon substrate is provided. A deep ion implant layer is implanted to reside below an oxide insulator. An oxygen implant layer is implanted while applying a mask to block the oxygen implant layer in selected regions. The selected regions provide for body contact for the SOI transistors. Holes are formed extending into the deep ion implant layer and the bulk silicon substrate. The holes are filled with an electrically conductive material to create stud contacts to the deep ion implant layer and the bulk silicon substrate.
摘要翻译：提供了一种用于实现绝缘体上硅（SOI）晶体管的双平面体接触的方法和半导体结构。提供体硅衬底。植入深离子注入层以位于氧化物绝缘体的下方。注入氧注入层，同时施加掩模以阻挡选定区域中的氧注入层。所选择的区域为SOI晶体管提供身体接触。形成延伸到深离子注入层和体硅衬底的孔。这些孔填充有导电材料，以产生到深离子注入层和体硅衬底的螺柱触点。

79. 发明授权

US06429099B1 Implementing contacts for bodies of semiconductor-on-insulator transistors 失效
标题翻译：实现绝缘体上半导体晶体管体的触点
公开(公告)号：US06429099B1
公开(公告)日：2002-08-06
申请号：US09478037
申请日：2000-01-05
申请人： Todd Alan Christensen , John Edward Sheets, II
发明人： Todd Alan Christensen , John Edward Sheets, II
IPC分类号： H01L2120
CPC分类号： H01L21/266 , H01L21/26533 , H01L21/743 , H01L21/76243 , H01L21/76267 , H01L21/84 , H01L27/1203 , H01L29/0653 , Y10S438/967
摘要： A method and semiconductor structure are provided for implementing body contacts for semiconductor-on-insulator transistors. A bulk semiconductor substrate is provided. A mask is applied to the bulk semiconductor substrate to block an insulating implant layer in selected regions. The selected regions provide for body contact for transistors. Holes are formed extending into the bulk semiconductor substrate. The holes are filled with an electrically conductive material to create stud contacts to the bulk semiconductor substrate. In the preferred embodiment, the semiconductor-on-insulator is silicon on an oxide insulating layer and the invention provides a body contact for SOI transistors.
摘要翻译：提供了一种用于实现绝缘体上半导体晶体管的体接触的方法和半导体结构。提供了体半导体衬底。将掩模应用于体半导体衬底以阻挡选定区域中的绝缘注入层。所选择的区域为晶体管提供身体接触。形成延伸到体半导体衬底中的孔。这些孔填充有导电材料以产生到体半导体衬底的螺柱触点。在优选实施例中，绝缘体上半导体是氧化物绝缘层上的硅，并且本发明为SOI晶体管提供体接触。

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