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71. 发明授权

US07253116B2 High ion energy and reative species partial pressure plasma ash process 有权
标题翻译：高离子能量和反应物质分压等离子体灰分过程
公开(公告)号：US07253116B2
公开(公告)日：2007-08-07
申请号：US10904608
申请日：2004-11-18
申请人： Nicholas C. M. Fuller , Timothy J. Dalton
发明人： Nicholas C. M. Fuller , Timothy J. Dalton
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/76802 , G03F7/427 , H01L21/31138
摘要： A high ion energy and high pressure O2/CO-based plasma for ashing field photoresist material subsequent to via-level damascene processing. The optimized plasma ashing process is performed at greater than approximately 300 mT pressure and ion energy greater than approximately 500 W conditions with an oxygen partial pressure of greater than approximately 85%. The rapid ash rate of the high pressure/high ion energy process and minimal dissociation conditions (no “source” power is applied) allow minimal interaction between the interlevel dielectric and ash chemistry to achieve minimal overall sidewall modification of less than approximately 5 nm.
摘要翻译：用于经过层级镶嵌处理之后灰化场致光材料的高离子能量和高压O 2 2 / CO基等离子体。优化的等离子体灰化过程在大于约300mT的压力下进行，离子能量大于约500W条件，氧分压大于约85％。高压/高离子能量过程的快速灰分速率和最小解离条件（不施加“源”功率）允许层间电介质和灰分化学之间的最小相互作用，以实现小于约5nm的最小总体侧壁修饰。

72. 发明授权

US07223691B2 Method of forming low resistance and reliable via in inter-level dielectric interconnect 有权
标题翻译：在层间电介质互连中形成低电阻和可靠通孔的方法
公开(公告)号：US07223691B2
公开(公告)日：2007-05-29
申请号：US10965031
申请日：2004-10-14
申请人： Cyril Cabral, Jr. , Lawrence A. Clevenger , Timothy J. Dalton , Patrick W. DeHaven , Chester T. Dziobkowski , Sunfei Fang , Terry A. Spooner , Tsong-Lin L. Tai , Kwong Hon Wong , Chin-Chao Yang
发明人： Cyril Cabral, Jr. , Lawrence A. Clevenger , Timothy J. Dalton , Patrick W. DeHaven , Chester T. Dziobkowski , Sunfei Fang , Terry A. Spooner , Tsong-Lin L. Tai , Kwong Hon Wong , Chin-Chao Yang
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/76849 , H01L21/76867 , H01L21/76888
摘要： A novel interlevel contact via structure having low contact resistance and improved reliability, and method of forming the contact via. The method comprises steps of: etching an opening through an interlevel dielectric layer to expose an underlying metal (Copper) layer surface; and, performing a low energy ion implant of an inert gas (Nitrogen) into the exposed metal underneath; and, depositing a refractory liner into the walls and bottom via structure which will have a lower contact resistance due to the presence of the proceeding inert gas implantation. Preferably, the inert Nitrogen gas reacts with the underlying exposed Copper metal to form a thin layer of CuN.
摘要翻译：具有低接触电阻和改进的可靠性的新颖的层间接触通孔结构以及形成接触通孔的方法。该方法包括以下步骤：通过层间电介质层蚀刻开口以暴露下面的金属（铜）层表面; 并且将惰性气体（氮气）的低能量离子注入进入下面暴露的金属; 并且将耐火衬垫沉积到壁和底部通孔结构中，由于进行的惰性气体注入的存在而将具有较低的接触电阻。优选地，惰性氮气与下面暴露的铜金属反应形成一层薄的CuN。

73. 发明授权

US07001835B2 Crystallographic modification of hard mask properties 失效
标题翻译：硬掩模性能的晶体学修饰
公开(公告)号：US07001835B2
公开(公告)日：2006-02-21
申请号：US10707119
申请日：2003-11-21
申请人： Lawrence A. Clevenger , Andrew P. Cowley , Timothy J. Dalton , Mark Hoinkis , Steffen K. Kaldor , Kaushik A. Kumar , Stephen M. Rossnagel , Andrew H. Simon , Douglas C. La Tulipe, Jr.
发明人： Lawrence A. Clevenger , Andrew P. Cowley , Timothy J. Dalton , Mark Hoinkis , Steffen K. Kaldor , Kaushik A. Kumar , Stephen M. Rossnagel , Andrew H. Simon , Douglas C. La Tulipe, Jr.
IPC分类号： H01L21/4763
CPC分类号： H01L23/544 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01L21/0332 , H01L21/0337 , H01L21/2855 , H01L21/76841 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A hardmask layer in the back end of an integrated circuit is formed from TaN having a composition of less than 50% Ta and a resistivity greater than 400 μOhm-cm, so that it is substantially transparent in the visible and permits visual alignment of upper and lower alignment marks through the hardmask and intervening layer(s) of ILD. A preferred method of formation of the hardmask is by sputter deposition of Ta in an ambient containing N2 and a flow rate such that (N2 flow)/(N2+carrier flow)>0.5.
摘要翻译：集成电路后端的硬掩模层由具有小于50％Ta且电阻率大于400μΩ-cm的组成的TaN形成，使得其在可见光中基本上是透明的并且允许上和通过硬掩模和ILD的中间层降低对准标记。形成硬掩模的优选方法是通过在含有N 2 O 2的环境中溅射沉积Ta并使流速使得（N 2 N 2 O 2）/（N _{2 +载体流）> 0.5。}

74. 发明授权

US06933191B2 Two-mask process for metal-insulator-metal capacitors and single mask process for thin film resistors 失效
标题翻译：金属绝缘体金属电容器的双掩模工艺和薄膜电阻器的单掩模工艺
公开(公告)号：US06933191B2
公开(公告)日：2005-08-23
申请号：US10605260
申请日：2003-09-18
申请人： Glenn A. Biery , Zheng G. Chen , Timothy J. Dalton , Naftali E. Lustig
发明人： Glenn A. Biery , Zheng G. Chen , Timothy J. Dalton , Naftali E. Lustig
IPC分类号： H01L21/02 , H01L21/027 , H01L21/20 , H01L21/8242
CPC分类号： H01L28/20 , H01L21/0274 , H01L28/40
摘要： MIM capacitors and thin film resistors are fabricated with at least one less lithographic step than the prior art methods. The process step reduction is realized by using semi-transparent metallic electrodes, fabricated with a two-mask process, which provides for direct alignment, and eliminates the need for alignment trenches in an additional layer.
摘要翻译： MIM电容器和薄膜电阻器与现有技术的方法相比制造的光刻步骤至少少一个。通过使用通过双掩模工艺制造的半透明金属电极实现工艺步骤减少，其提供直接对准，并且不需要在附加层中对准沟槽。

75. 发明授权

US10319870B2 Photovoltaic module with a controllable infrared protection layer 有权
公开(公告)号：US10319870B2
公开(公告)日：2019-06-11
申请号：US12887156
申请日：2010-09-21
申请人： Lawrence A. Clevenger , Timothy J. Dalton , Maxime Darnon , Rainer Krause , Gerd Pfeiffer , Kevin Prettyman , Carl J. Radens , Brian C. Sapp
发明人： Lawrence A. Clevenger , Timothy J. Dalton , Maxime Darnon , Rainer Krause , Gerd Pfeiffer , Kevin Prettyman , Carl J. Radens , Brian C. Sapp
IPC分类号： H01L31/00 , H01L31/054 , G02B26/00 , H01L31/048 , H01L31/049
摘要： An apparatus, system, and method are disclosed for a photovoltaic module, the photovoltaic module comprising a plurality of photovoltaic cells, a controllable infrared protection layer, and a protection switching means. The controllable infrared protection layer is for reducing the infrared radiation absorbed by the photovoltaic module, where the controllable infrared protection layer has a first state and a second state. When the infrared protection layer is in the first state the transmission of infrared radiation to the photovoltaic cells is higher than when the infrared protection layer is in the second state. The protection switching means is for switching the controllable infrared protection layer between the first state and the second state.

76. 发明授权

US08487401B2 Methods of fabricating passive element without planarizing and related semiconductor device 有权
标题翻译：无平面化制造无源元件及相关半导体器件的方法
公开(公告)号：US08487401B2
公开(公告)日：2013-07-16
申请号：US13359634
申请日：2012-01-27
申请人： Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Anthony K. Stamper , Kunal Vaed
发明人： Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Anthony K. Stamper , Kunal Vaed
IPC分类号： H01L23/522
CPC分类号： H01L21/76819 , H01L23/522 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.
摘要翻译：公开了制造无源元件的方法和包括无源元件的半导体器件，其包括使用虚拟无源元件。虚拟无源元件是被添加到芯片布局以帮助平坦化但在有源电路中不使用的无源元件或线。该方法的一个实施例包括形成无源元件和邻近无源元件的虚拟无源元件; 在无源元件和虚拟无源元件上形成电介质层，其中介电层在无源元件和虚拟无源元件之间基本上是平面的; 并且在电介质层中形成通过电介质层与无源元件的互连以及与虚拟无源元件的至少一部分重叠的虚拟互连部分。该方法消除了平面化的需要。

77. 发明申请

US20120183743A1 TWO-DIMENSIONAL PATTERNING EMPLOYING SELF-ASSEMBLED MATERIAL 失效
公开(公告)号：US20120183743A1
公开(公告)日：2012-07-19
申请号：US13432036
申请日：2012-03-28
申请人： Timothy J. Dalton , Bruce B. Doris , Ho-Cheol Kim , Carl Radens
发明人： Timothy J. Dalton , Bruce B. Doris , Ho-Cheol Kim , Carl Radens
IPC分类号： B32B3/30
CPC分类号： H01L21/0337 , B81C1/00031 , B81C2201/0149 , B82Y10/00 , B82Y30/00 , H01L21/0338 , Y10T428/24612
摘要： A first nanoscale self-aligned self-assembled nested line structure having a sublithographic width and a sublithographic spacing and running along a first direction is formed from first self-assembling block copolymers within a first layer. The first layer is filled with a filler material and a second layer is deposited above the first layer containing the first nanoscale nested line structure. A second nanoscale self-aligned self-assembled nested line structure having a sublithographic width and a sublithographic spacing and running in a second direction is formed from second self-assembling block copolymers within the second layer. The composite pattern of the first nanoscale nested line structure and the second nanoscale nested line structure is transferred into an underlayer beneath the first layer to form an array of structures containing periodicity in two directions.

78. 发明申请

US20120183742A1 PATTERN FORMATION EMPLOYING SELF-ASSEMBLED MATERIAL 有权
公开(公告)号：US20120183742A1
公开(公告)日：2012-07-19
申请号：US13430179
申请日：2012-03-26
申请人： Charles T. Black , Timothy J. Dalton , Bruce B. Doris , Carl J. Radens
发明人： Charles T. Black , Timothy J. Dalton , Bruce B. Doris , Carl J. Radens
IPC分类号： B32B3/10 , B32B3/30
CPC分类号： H01L21/0338 , B81B2203/0369 , B81C1/00031 , B81C2201/0149 , B81C2201/0198 , B82Y30/00 , H01L21/0337 , H01L51/0017 , Y10S977/882 , Y10S977/887 , Y10S977/888 , Y10T428/24479 , Y10T428/2457 , Y10T428/24612 , Y10T428/24736 , Y10T428/24802
摘要： In one embodiment, Hexagonal tiles encompassing a large are divided into three groups, each containing ⅓ of all hexagonal tiles that are disjoined among one another. Openings for the hexagonal tiles in each group are formed in a template layer, and a set of self-assembling block copolymers is applied and patterned within each opening. This process is repeated three times to encompass all three groups, resulting in a self-aligned pattern extending over a wide area. In another embodiment, the large area is divided into rectangular tiles of two non-overlapping and complementary groups. Each rectangular area has a width less than the range of order of self-assembling block copolymers. Self-assembled self-aligned line and space structures are formed in each group in a sequential manner so that a line and space pattern is formed over a large area extending beyond the range of order.

79. 发明申请

US20120183736A1 PATTERN FORMATION EMPLOYING SELF-ASSEMBLED MATERIAL 有权
公开(公告)号：US20120183736A1
公开(公告)日：2012-07-19
申请号：US13430177
申请日：2012-03-26
申请人： Charles T. Black , Timothy J. Dalton , Bruce B. Doris , Carl Radens
发明人： Charles T. Black , Timothy J. Dalton , Bruce B. Doris , Carl Radens
IPC分类号： B32B3/10 , B32B3/30
CPC分类号： H01L21/0338 , B81B2203/0369 , B81C1/00031 , B81C2201/0149 , B81C2201/0198 , B82Y30/00 , H01L21/0337 , H01L51/0017 , Y10S977/882 , Y10S977/887 , Y10S977/888 , Y10T428/24479 , Y10T428/2457 , Y10T428/24612 , Y10T428/24736 , Y10T428/24802
摘要： In one embodiment, Hexagonal tiles encompassing a large are divided into three groups, each containing ⅓ of all hexagonal tiles that are disjoined among one another. Openings for the hexagonal tiles in each group are formed in a template layer, and a set of self-assembling block copolymers is applied and patterned within each opening. This process is repeated three times to encompass all three groups, resulting in a self-aligned pattern extending over a wide area. In another embodiment, the large area is divided into rectangular tiles of two non-overlapping and complementary groups. Each rectangular area has a width less than the range of order of self-assembling block copolymers. Self-assembled self-aligned line and space structures are formed in each group in a sequential manner so that a line and space pattern is formed over a large area extending beyond the range of order.

80. 发明授权

US08198103B2 Addition of ballast hydrocarbon gas to doped polysilicon etch masked by resist 有权
标题翻译：添加压敏烃气体到由抗蚀剂掩蔽的掺杂多晶硅蚀刻
公开(公告)号：US08198103B2
公开(公告)日：2012-06-12
申请号：US12170634
申请日：2008-07-10
申请人： Timothy J. Dalton , Wesley C. Natzle , Paul W. Pastel , Richard S. Wise , Hongwen Yan , Ying Zhang
发明人： Timothy J. Dalton , Wesley C. Natzle , Paul W. Pastel , Richard S. Wise , Hongwen Yan , Ying Zhang
IPC分类号： H01L21/302
CPC分类号： H01L21/32139 , H01L21/32137 , Y10S438/909
摘要： A chemical composition and method for providing uniform and consistent etching of gate stacks on a semiconductor wafer, whereby the composition includes an etchant and an added ballast gas added. The gate stacks are formed using this combined etchant and ballast gas composition. The ballast gas may either be similar to, or the equivalent of, a gaseous byproduct generated within the processing chamber. The ballast gas is added in either an overload amount, or in an amount sufficient to compensate for varying pattern factor changes across the water. This etchant and added ballast gas form a substantially homogeneous etchant across the entire wafer, thereby accommodating for or compensating for these pattern factor differences. When etching the wafer using this homogeneous etchant, a passivation layer is formed on exposed wafer surfaces. The passivation layer protects the lateral sidewalls of the gate stacks during etch to result in straighter gate stacks.
摘要翻译：一种用于在半导体晶片上提供均匀且一致的栅叠层蚀刻的化学组成和方法，由此所述组合物包括添加的蚀刻剂和添加的压载气体。使用这种组合的蚀刻剂和压载气组合物形成栅堆叠。压载气体可以类似于或等同于在处理室内产生的气态副产物。压载气体以过载量或足以补偿横跨水的变化因子变化的量加入。这种蚀刻剂和添加的压载气体在整个晶片上形成基本均匀的蚀刻剂，从而适应或补偿这些图案因子差异。当使用这种均匀的蚀刻剂蚀刻晶片时，在暴露的晶片表面上形成钝化层。钝化层在蚀刻期间保护栅极堆叠的侧壁以产生更直的栅叠层。

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