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71. 发明授权

US5917752A Nonvolatile semiconductor memory device 失效
公开(公告)号：US5917752A
公开(公告)日：1999-06-29
申请号：US457761
申请日：1995-06-01
申请人： Koichi Seki , Takeshi Wada , Tadashi Muto , Kazuyoshi Shoji , Yasurou Kubota , Hitoshi Kume
发明人： Koichi Seki , Takeshi Wada , Tadashi Muto , Kazuyoshi Shoji , Yasurou Kubota , Hitoshi Kume
IPC分类号： G11C16/12 , G11C16/16 , G11C16/30 , G11C16/32 , G11C16/34 , G11C11/34
CPC分类号： G11C16/3445 , G11C16/06 , G11C16/12 , G11C16/16 , G11C16/30 , G11C16/32 , G11C16/344 , G11C2216/20
摘要： Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the present invention, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode. The erasure voltage is supplied to a voltage conversion circuit provided within the nonvolatile memory device. Accordingly, erasure operation can be realized by the Vcc single power source. Further, substantial terminals of the collective erasure operation are individually controlled for every memory element or every collective memory element in response to the individual erasure speed of each memory element.

72. 外观设计

USD407327S Watchcase 失效
公开(公告)号：USD407327S
公开(公告)日：1999-03-30
申请号：US80402
申请日：1997-12-08
申请人： Takeshi Wada , Juhei Ozawa
设计人： Takeshi Wada , Juhei Ozawa

73. 外观设计

USD404654S Watchcase 失效
公开(公告)号：USD404654S
公开(公告)日：1999-01-26
申请号：US080021
申请日：1997-11-26
申请人： Toshiaki Kume , Takeshi Wada , Hitoshi Azegami
设计人： Toshiaki Kume , Takeshi Wada , Hitoshi Azegami

74. 外观设计

USD391498S Watchcase 失效
公开(公告)号：USD391498S
公开(公告)日：1998-03-03
申请号：US64399
申请日：1996-12-30
申请人： Toshiaki Kume , Takeshi Wada
设计人： Toshiaki Kume , Takeshi Wada

75. 发明授权

US5544098A Semiconductor memory device having an automatically activated verify function capability 失效
公开(公告)号：US5544098A
公开(公告)日：1996-08-06
申请号：US455152
申请日：1995-05-31
申请人： Akinori Matsuo , Masashi Watanabe , Masashi Wada , Takeshi Wada , Yasuhiro Nakamura
发明人： Akinori Matsuo , Masashi Watanabe , Masashi Wada , Takeshi Wada , Yasuhiro Nakamura
IPC分类号： G06F12/16 , G11C16/02 , G11C16/06 , G11C16/10 , G11C16/34 , G11C17/00 , G11C29/00 , G11C29/02 , G11C29/04 , G11C29/12 , G11C29/46 , G11C29/48 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C7/00
CPC分类号： G11C16/10 , G11C16/3454 , G11C16/3459 , G11C29/46 , G11C29/48
摘要： A semiconductor memory device having a plurality of nonvolatile memory devices or elements disposed in a matrix arrangement as one or more memory arrays is provided with a write operation and a verify mode which is automatically implemented when the write operation of the memory device ends. In connection with this, an auto-verify function is set in an internal circuit associated with the memory in accordance with a predetermined control signal and wherein a read mode subsequent to the write operation is implemented. During the auto-verify function, the read mode is implemented by effecting a data comparison circuit, such as an exclusive-OR logic circuit, which performs a coincidence/non-coincidence operation comparing the write data and the read data.

76. 发明授权

US5475692A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5475692A
公开(公告)日：1995-12-12
申请号：US407986
申请日：1995-03-22
申请人： Susumu Hatano , Jun Kitano , Kenji Nishimoto , Shin'ichi Ikenaga , Masayasu Kawamura , Yasushi Takahashi , Takeshi Wada , Michihiro Mishima , Fujio Yamamoto
发明人： Susumu Hatano , Jun Kitano , Kenji Nishimoto , Shin'ichi Ikenaga , Masayasu Kawamura , Yasushi Takahashi , Takeshi Wada , Michihiro Mishima , Fujio Yamamoto
IPC分类号： G11C29/10 , G11C29/14 , G11C29/40 , G06F11/00
CPC分类号： G11C29/40 , G11C29/10 , G11C29/14
摘要： Herein disclosed is a semiconductor integrated circuit for testing test data of two kinds of non-inverted and inverted statuses of all bits by itself with a prospective data of one kind to compress and output the test results. The semiconductor integrated circuit includes a decide circuit 25 for deciding a first status, in which the prospective data latched by a pattern register and the read data of a memory cell array are coincident, a second status, in which the read data is coincident with the logically inverted data of the prospective data, and a third statuses other than the first and second statuses through an exclusive OR gate to generate signals of 2 bits capable of discriminating the individual statuses. These statuses are informed to the outside of the semiconductor integrated circuit in accordance with high- and low-levels and a high-impedance.
摘要翻译：这里公开了一种半导体集成电路，用于测试所有位的两种非反相和反相状态的测试数据，其中一种预期数据可以压缩并输出测试结果。半导体集成电路包括：决定电路25，用于决定第一状态，其中由模式寄存器锁存的预期数据和存储单元阵列的读取数据一致;第二状态，读取数据与逻辑反转的预期数据的数据，以及通过异或门以外的第一状态和第二状态的第三状态，以产生能够区分各个状态的2位的信号。这些状态根据高低电平和高阻抗通知到半导体集成电路的外部。

77. 发明授权

US4723193A Low temperature sintered ceramic capacitor with a temperature compensating capability, and method of manufacture 失效
标题翻译：具有温度补偿能力的低温烧结陶瓷电容器及其制造方法
公开(公告)号：US4723193A
公开(公告)日：1988-02-02
申请号：US945335
申请日：1986-12-22
申请人： Hirokazu Chazono , Hiroshi Kishi , Shunji Murai , Masami Fukui , Takeshi Wada
发明人： Hirokazu Chazono , Hiroshi Kishi , Shunji Murai , Masami Fukui , Takeshi Wada
IPC分类号： H01G4/30 , C04B35/47 , C04B35/49 , H01B3/12 , H01G4/12 , C04B35/50
CPC分类号： C04B35/47 , C04B35/49 , H01G4/1245
摘要： A temperature compensating capacitor of monolithic or multilayered configuration comprising a dielectric ceramic body and at least two electrodes buried therein. The ceramic body is composed of a major ingredient expressed by the formula, {(Sr.sub.1-x-y Ca.sub.x M.sub.y)O}.sub.k (Ti.sub.1-z Zr.sub.z)O.sub.2, where M is at least either of magnesium and zinc, and where x, y, k and z are numerals in the ranges of zero to 0.995 inclusive, 0.005 to 0.100 inclusive, 1.00 to 1.04 inclusive, and 0.005 to 0.100 inclusive, respectively. To this major ingredient is added a minor proportion of a mixture of boric oxide, silicon dioxide, and one or more metal oxides selected from among barium oxide, magnesium oxide, zinc oxide, strontium oxide and calcium oxide. For the fabrication of capacitors the mixture of the above major ingredient and additives in finely divided form are formed into moldings of desired shape and size, each with at least two electrodes buried therein. The moldings and electrodes are cosintered in a reductive or neutral atmosphere and then are reheated at a lower temperature in an oxidative atmosphere. The cosintering temperature can be so low that nickel or like base metal can be employed as the electrode material.
摘要翻译：一种单片或多层结构的温度补偿电容器，包括介电陶瓷体和埋在其中的至少两个电极。陶瓷体由以下式表示的主要成分{（Sr1-x-yCaxMy）O} k（Ti1-zZrz）O2组成，其中M是镁和锌中的至少一种，其中x，y，k z分别为0〜0.995，0.005〜0.100，包括1.00〜1.04，0.005〜0.100的数字。添加少量的氧化硼，二氧化硅和一种或多种选自氧化钡，氧化镁，氧化锌，氧化锶和氧化钙的金属氧化物的混合物。为了制造电容器，将上述主要成分和细分散形式的添加剂的混合物形成为所需形状和尺寸的模制品，其中至少埋设有两个电极。模制品和电极在还原或中性气氛中共烧结，然后在较低温度下在氧化气氛中再加热。整个烧结温度可以低到可以使用镍或类似的贱金属作为电极材料。

78. 发明授权

US4709299A Low temperature sintered ceramic capacitor with a temperature compensating capability, and method of manufacture 失效
标题翻译：具有温度补偿能力的低温烧结陶瓷电容器及其制造方法
公开(公告)号：US4709299A
公开(公告)日：1987-11-24
申请号：US934667
申请日：1986-11-25
申请人： Hiroshi Kishi , Minoru Oshio , Shunji Murai , Takeshi Wada , Masami Fukui
发明人： Hiroshi Kishi , Minoru Oshio , Shunji Murai , Takeshi Wada , Masami Fukui
IPC分类号： C04B35/47 , C04B35/49 , H01B3/12 , H01G4/12 , C04B35/46
CPC分类号： C04B35/49 , C04B35/47 , H01G4/1245
摘要： A temperature compensating capacitor of monolithic or multilayered configuration comprising a dielectric ceramic body and at least two electrodes buried therein. The ceramic body is composed of a major ingredient expressed by the formula, (CaO).sub.k.(Zr.sub.1-x Ti.sub.x)O, where k and x are numerals in the ranges of 0.8 to 1.3 inclusive and of zero to 0.3 inclusive, respectively. To this major ingredient is added a minor proportion of a mixture of boric oxide, silicon dioxide, and one or more metal oxides selected from among barium oxide, magnesium oxide, zinc oxide, strontium oxide and calcium oxide. For the fabrication of capacitors the mixture of the above major ingredient and additives in finely divided form are formed into moldings of desired shape and size, each with at least two electrodes buried therein. The moldings and electrodes are cosintered in a reductive or neutral atmosphere and then are reheated at a lower temperature in an oxidative atmosphere. The cosintering temperature can be so low that nickel or like base metal can be employed as the electrode material.
摘要翻译：一种单片或多层结构的温度补偿电容器，包括介电陶瓷体和埋在其中的至少两个电极。陶瓷体由式（CaO）k。（Zr1-xTix）O表示的主要成分组成，其中k和x分别为0.8〜1.3的数值和0〜0.3的数值。添加少量的氧化硼，二氧化硅和一种或多种选自氧化钡，氧化镁，氧化锌，氧化锶和氧化钙的金属氧化物的混合物。为了制造电容器，将上述主要成分和细分散形式的添加剂的混合物形成为所需形状和尺寸的模制品，其中至少埋设有两个电极。模制品和电极在还原或中性气氛中共烧结，然后在较低温度下在氧化气氛中再加热。整个烧结温度可以低到可以使用镍或类似的贱金属作为电极材料。

79. 发明授权

US4700269A Low temperature sintered ceramic capacitor with a temperature compensating capability, and method of manufacture 失效
标题翻译：具有温度补偿能力的低温烧结陶瓷电容器及其制造方法
公开(公告)号：US4700269A
公开(公告)日：1987-10-13
申请号：US934656
申请日：1986-11-25
申请人： Hiroshi Kishi , Minoru Oshio , Shunji Murai , Takeshi Wada , Masami Fukui
发明人： Hiroshi Kishi , Minoru Oshio , Shunji Murai , Takeshi Wada , Masami Fukui
IPC分类号： C04B35/49 , H01B3/12 , H01G4/008 , H01G4/12 , C04B35/46
CPC分类号： H01G4/008 , H01G4/1245
摘要： A temperature compensating capacitor of monolithic, multilayered configuration comprising a dielectric ceramic body and at least two electrodes buried therein. The ceramic body is composed of a major ingredient expressed by the formula, (CaO).sub.k .multidot.(Zr.sub.1-x Ti.sub.x)O.sub.2, where k and x are numerals in the ranges of 0.8 to 1.3 inclusive and of zero to 0.3 inclusive, respectively. To this major ingredient is added a minor proportion of a mixture of lithium oxide, silicon dioxide, and one or more metal oxides selected from among barium oxide, magnesium oxide, zinc oxide, strontium oxide and calcium oxide. For the fabrication of capacitors the mixture of the above major ingredient and additives in finely divided form are formed into moldings of desired shape and size, each with at least two electrodes buried therein. The moldings and electrodes are cosintered in a reductive or neutral atmosphere and then are reheated at a lower temperature in an oxidative atmosphere. The cosintering temperature can be so low that nickel or like base metal can be employed as the electrode material.
摘要翻译：一种单片，多层结构的温度补偿电容器，包括介电陶瓷体和埋在其中的至少两个电极。陶瓷体由式（CaO）k x（Zr 1-x Tix）O 2表示的主要成分组成，其中k和x分别为0.8〜1.3的数值和0〜0.3的数值。在该主要成分中加入少量的氧化锂，二氧化硅和选自氧化钡，氧化镁，氧化锌，氧化锶和氧化钙中的一种或多种金属氧化物的混合物。为了制造电容器，将上述主要成分和细分散形式的添加剂的混合物形成为所需形状和尺寸的模制品，其中至少埋设有两个电极。模制品和电极在还原或中性气氛中共烧结，然后在较低温度下在氧化气氛中再加热。整个烧结温度可以低到可以使用镍或类似的贱金属作为电极材料。

80. 发明授权

US4700264A Low temperature sintered ceramic capacitor with a temperature compensating capability, and method of manufacture 失效
标题翻译：具有温度补偿能力的低温烧结陶瓷电容器及其制造方法
公开(公告)号：US4700264A
公开(公告)日：1987-10-13
申请号：US934671
申请日：1986-11-25
申请人： Hiroshi Kishi , Minoru Oshio , Shunji Murai , Takeshi Wada , Masami Fukui
发明人： Hiroshi Kishi , Minoru Oshio , Shunji Murai , Takeshi Wada , Masami Fukui
IPC分类号： C04B35/486 , C04B35/49 , H01B3/12 , H01G4/008 , H01G4/12 , C04B35/46
CPC分类号： H01G4/008 , C04B35/486 , C04B35/49 , H01G4/1245
摘要： A temperature compensating capacitor of monolithic or multilayered configuration comprising a dielectric ceramic body and at least two electrodes buried therein. The ceramic body is composed of a major ingredient expressed by the formula, (SrO).sub.k .multidot.(Zr.sub.1-x Ti.sub.x)O.sub.2, where k and x are numerals in the ranges of 0.8 to 1.3 inclusive and of zero to 0.25 inclusive, respectively. To this major ingredient is added a minor proportion of a mixture of boric oxide, silicon dioxide, and one or more metal oxides selected from among barium oxide, magnesium oxide, zinc oxide, strontium oxide and calcium oxide. For the fabrication of capacitors the mixture of the above major ingredient and additives in finely divided form are formed into moldings of desired shape and size, each with at least two electrodes buried therein. The moldings and electrodes are cosintered in a reductive or neutral atmosphere and then are reheated at a lower temperature in an oxidative atmosphere. The cosintering temperature can be so low that nickel or like base metal can be employed as the electrode material.
摘要翻译：一种单片或多层结构的温度补偿电容器，包括介电陶瓷体和埋在其中的至少两个电极。陶瓷体由以下式（SrO）kx（Zr1-xTix）O2表示的主要成分组成，其中k和x分别为0.8至1.3的数值和包括0至0.25的数字。添加少量的氧化硼，二氧化硅和一种或多种选自氧化钡，氧化镁，氧化锌，氧化锶和氧化钙的金属氧化物的混合物。为了制造电容器，将上述主要成分和细分散形式的添加剂的混合物形成为所需形状和尺寸的模制品，其中至少埋设有两个电极。模制品和电极在还原或中性气氛中共烧结，然后在较低温度下在氧化气氛中再加热。整个烧结温度可以低到可以使用镍或类似的贱金属作为电极材料。

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