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71. 发明授权

US06728826B2 Semiconductor storage device in which commands are sequentially fed to a plurality of flash memories to continuously write data 失效
标题翻译：半导体存储装置，其中命令被顺序地馈送到多个闪存以连续地写入数据
公开(公告)号：US06728826B2
公开(公告)日：2004-04-27
申请号：US10387478
申请日：2003-03-14
申请人： Kenichi Kaki , Kunihiro Katayama , Takashi Tsunehiro
发明人： Kenichi Kaki , Kunihiro Katayama , Takashi Tsunehiro
IPC分类号： G06F1300
CPC分类号： G06F3/0688 , G06F3/061 , G06F3/0611 , G06F3/0613 , G06F3/0652 , G06F3/0656 , G06F3/0659 , G06F3/0679 , G11C16/102 , G11C16/32
摘要： A semiconductor storage apparatus such as a disk pack in which a controller sends a second write command or instruction while a write operation for a first write command or instruction is being carried out. The storage apparatus includes a plurality of flash memories which operate slower in writing data thereinto than the reading data therefrom, a write buffer memory in which data are temporarily held, a processor which controls the data writing operation and which transfers and analyzes commands and statuses, an address controller which generates physical addresses, a circuit which generates a writing supply voltage Vpp for the flash memories, a memory address bus, and a data bus. The semiconductor disk pack is connected to a standard bus in a personal computer or the like. The processor writes the data of one word into a desired one of the flash memories, and it continuously writes the data of one word into an accessible one of the other flash memories during a latency which extends until the desired flash memory becomes capable of writing the next data of one word thereinto.
摘要翻译：一种半导体存储装置，例如在执行用于第一写入命令或指令的写入操作时控制器发送第二写入命令或指令的盘组件。存储装置包括多个闪存，其写入数据比其读取数据慢，其中临时保存数据的写入缓冲存储器，控制数据写入操作并且传送和分析命令和状态的处理器，生成物理地址的地址控制器，产生闪速存储器的写入电源电压Vpp的电路，存储器地址总线和数据总线。半导体磁盘组件连接到个人计算机等中的标准总线。处理器将一个字的数据写入所需的一个闪速存储器中，并且在延迟期间持续地将一个字的数据写入可访问的另一个闪存中，直到期望的闪速存储器能够写入其中一个字的下一个数据。

72. 发明授权

US06654270B2 Directional coupling memory module 失效
公开(公告)号：US06654270B2
公开(公告)日：2003-11-25
申请号：US10191112
申请日：2002-07-10
申请人： Hideki Osaka , Toyohiko Komatsu , Takashi Tsunehiro , Koichi Kimura , Susumu Hatano , Kazuya Ito , Toshio Sugano
发明人： Hideki Osaka , Toyohiko Komatsu , Takashi Tsunehiro , Koichi Kimura , Susumu Hatano , Kazuya Ito , Toshio Sugano
IPC分类号： G11C502
CPC分类号： G11C5/063 , G11C5/04
摘要： Conventionally, wiring length occupied by a directional coupler decides intervals between modules connected to a bus, and those intervals can not be shortened furthermore. Accordingly, the intervals between modules are wide and high-density mounting is not possible. In the present invention, a directional coupler in a memory bus is formed by a leader line from a controller and a leader line from a memory chip and contained within a memory module. Accordingly, pitch between the modules can be reduced and high-density mounting can be realized.

73. 发明授权

US06421279B1 Flash memory control method and apparatus processing system therewith 有权
标题翻译：闪存控制方法和装置处理系统
公开(公告)号：US06421279B1
公开(公告)日：2002-07-16
申请号：US09927493
申请日：2001-08-13
申请人： Tsunehiro Tobita , Jun Kitahara , Takashi Tsunehiro , Kunihiro Katayama , Ryuichi Hattori , Yukihiro Seki , Hajime Yamagami , Takashi Totsuka , Takeshi Wada , Yosio Takaya , Manabu Saito , Kenichi Kaki , Takao Okubo , Takashi Kikuchi , Masamichi Kishi , Takeshi Suzuki , Shigeru Kadowaki
发明人： Tsunehiro Tobita , Jun Kitahara , Takashi Tsunehiro , Kunihiro Katayama , Ryuichi Hattori , Yukihiro Seki , Hajime Yamagami , Takashi Totsuka , Takeshi Wada , Yosio Takaya , Manabu Saito , Kenichi Kaki , Takao Okubo , Takashi Kikuchi , Masamichi Kishi , Takeshi Suzuki , Shigeru Kadowaki
IPC分类号： G11C800
CPC分类号： G11C29/765 , G06F3/0601 , G06F3/0613 , G06F3/0616 , G06F3/064 , G06F3/0644 , G06F3/0656 , G06F3/0679 , G06F3/068 , G06F11/1433 , G06F11/1441 , G06F12/08 , G06F12/0802 , G06F12/0866 , G06F2003/0694 , G06F2212/2022 , G06F2212/312 , G11C29/789 , G11C29/82
摘要： A semiconductor file system features a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating correspondence between physical and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information. The controller determines a physical sector address. The control section is for controlling input/output of data from/to the external system and for temporarily storing write data into the first nonvolatile memory from the external system in the volatile memory and then transferring the write data from the volatile memory to the first nonvolatile memory.
摘要翻译：半导体文件系统具有电可擦除的第一非易失性存储器，不电可擦除的第二非易失性存储器，易失性存储器，控制器和控制部分，其控制控制器，其中对应于从外部系统指定的逻辑地址的物理地址是访问。第一非易失性存储器存储用于执行操作的外部系统的数据，指示物理和逻辑地址之间的对应关系的第一管理信息以及指示第一非易失性存储器的状态的第二管理信息。第二非易失性存储器先前存储接口信息。控制器确定物理扇区地址。控制部分用于控制来自/外部系统的数据的输入/输出，并用于从易失性存储器中的外部系统暂时将写数据存储到第一非易失性存储器中，然后将写入数据从易失性存储器传送到第一非易失性存储器记忆。

74. 发明授权

US06347051B2 Storage device employing a flash memory 有权
公开(公告)号：US06347051B2
公开(公告)日：2002-02-12
申请号：US09866622
申请日：2001-05-30
申请人： Hajime Yamagami , Kouichi Terada , Yoshihiro Hayashi , Takashi Tsunehiro , Kunihiro Katayama , Kenichi Kaki , Takeshi Furuno
发明人： Hajime Yamagami , Kouichi Terada , Yoshihiro Hayashi , Takashi Tsunehiro , Kunihiro Katayama , Kenichi Kaki , Takeshi Furuno
IPC分类号： G06F1204
CPC分类号： G11C29/765 , G06F3/0601 , G06F3/0616 , G06F3/0619 , G06F3/064 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F2003/0694 , G06F2212/2022 , G11C16/102 , G11C16/349
摘要： A semiconductor disk wherein a flash memory into which data is rewritten in block unit is employed as a storage medium, the semiconductor disk including a data memory in which file data are stored, a substitutive memory which substitutes for blocks of errors in the data memory, an error memory in which error information of the data memory are stored, and a memory controller which reads data out of, writes data into and erases data from the data memory, the substitutive memory and the error memory. Since the write errors of the flash memory can be remedied, the service life of the semiconductor disk can be increased.

75. 发明授权

US6078520A Flash memory control method and information processing system therewith 有权
标题翻译：闪存控制方法和信息处理系统
公开(公告)号：US6078520A
公开(公告)日：2000-06-20
申请号：US357931
申请日：1999-07-21
申请人： Tsunehiro Tobita , Jun Kitahara , Takashi Tsunehiro , Kunihiro Katayama , Ryuichi Hattori , Yukihiro Seki , Hajime Yamagami , Takashi Totsuka , Takeshi Wada , Yosio Takaya , Manabu Saito , Kenichi Kaki , Takao Okubo , Takashi Kikuchi , Masamichi Kishi , Takeshi Suzuki , Shigeru Kadowaki
发明人： Tsunehiro Tobita , Jun Kitahara , Takashi Tsunehiro , Kunihiro Katayama , Ryuichi Hattori , Yukihiro Seki , Hajime Yamagami , Takashi Totsuka , Takeshi Wada , Yosio Takaya , Manabu Saito , Kenichi Kaki , Takao Okubo , Takashi Kikuchi , Masamichi Kishi , Takeshi Suzuki , Shigeru Kadowaki
IPC分类号： G06F11/14 , G06F12/08 , G11C29/00 , G11C17/00
CPC分类号： G11C29/765 , G06F11/1433 , G06F12/08 , G06F12/0802 , G06F12/0866 , G11C29/789 , G11C29/82 , G06F2212/2022 , G06F2212/312
摘要： A control method and system when a flash memory is used as a semiconductor disk or a main memory in an information processing system. A semiconductor file system comprises a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller which controls the memories, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating the correspondence between physical addresses at which the data is stored and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information required for inputting and outputting the data from and to the external system and read-only data of the data. The controller has a control means for determining a physical sector address forming predetermined high-order bits of the physical address when data is output from the first nonvolatile memory or when data is input to the volatile memory, means for storing the determined physical sector address, and means for consecutively generating addresses in a sector determined by the physical sector address.
摘要翻译：当闪存用作信息处理系统中的半导体盘或主存储器时的控制方法和系统。半导体文件系统包括电可擦除的第一非易失性存储器，不电可擦除的第二非易失性存储器，易失性存储器，控制存储器的控制器和控制控制器的控制部分，其中对应于由访问一个外部系统。第一非易失性存储器存储用于执行操作的外部系统的数据，指示存储数据的物理地址与逻辑地址之间的对应关系的第一管理信息，以及指示第一非易失性存储器的状态的第二管理信息。第二非易失性存储器预先存储从外部系统输入和输出数据所需的接口信息以及数据的只读数据。控制器具有控制装置，用于当数据从第一非易失性存储器输出时或当数据被输入到易失性存储器时，确定形成物理地址的预定高位的物理扇区地址，用于存储确定的物理扇区地址的装置，以及用于在由所述物理扇区地址确定的扇区中连续生成地址的装置。

76. 发明授权

US5809515A Semiconductor storage device in which instructions are sequentially fed to a plurality of flash memories to continuously write and erase data 失效
标题翻译：半导体存储装置，其中指令被顺序馈送到多个闪速存储器以连续写入和擦除数据
公开(公告)号：US5809515A
公开(公告)日：1998-09-15
申请号：US669914
申请日：1996-06-25
申请人： Kenichi Kaki , Kunihiro Katayama , Takashi Tsunehiro
发明人： Kenichi Kaki , Kunihiro Katayama , Takashi Tsunehiro
IPC分类号： G06F12/00 , G06F3/06 , G06F3/08 , G06F12/06 , G11C16/02 , G11C16/10 , G11C16/32 , G11C17/00 , G06F13/00 , G06F9/38 , G11C16/06
CPC分类号： G06F3/0601 , G06F3/061 , G06F3/0611 , G06F3/0613 , G06F3/064 , G06F3/0656 , G06F3/0659 , G06F3/0679 , G06F3/0688 , G11C16/102 , G11C16/32 , G06F2003/0694
摘要： A semiconductor storage device such as a disk pack includes a plurality of flash memories, a write buffer memory in which data are temporarily held, a processor which controls data writing and erasing operations and which transfers and analyzes commands and statuses to and from the flash memories, and a circuit which generates a writing supply voltage Vpp, different from a reading supply voltage, for the flash memories. The processor operates to send a first instruction for writing or erasing data of one word into a first one of the flash memories, and it continuously writes the data of one word into an accessible one of the other flash memories before the first one of the flash memories becomes capable of accepting the next write or erase instruction. The processor determines whether each nonvolatile memory has individually become ready to accept a new write or erase instruction. A plurality of instructions for writing or erasing data for consecutive addresses may thus be distributively, e.g., sequentially, fed to the plurality of nonvolatile memories to reduce a time period for writing or erasing data. The semiconductor storage device further includes a static random access memory for storing a conversion table for converting logical sector numbers into physical sector numbers for those areas of the flash memories which have accepted the write and erase instructions. The semiconductor disk pack may be connected, for example, to a standard bus in a personal computer.
摘要翻译：诸如磁盘盒的半导体存储装置包括多个闪速存储器，其中临时保存数据的写入缓冲存储器，控制数据写入和擦除操作的处理器，并且向闪存存储器和从闪存存储器传送和分析命令和状态，以及产生与读取电源电压不同的写入电源电压Vpp用于闪存的电路。处理器操作以发送用于将一个字的数据写入或擦除闪存的第一个的第一指令，并且在闪存的第一个闪存之前，将一个字的数据连续写入其他闪存中的可访问的一个存储器能够接受下一个写或擦除指令。处理器确定每个非易失性存储器是否已经单独准备好接受新的写入或擦除指令。因此，用于连续地址的写入或擦除数据的多个指令可以被分配地，例如顺序地馈送到多个非易失性存储器，以减少用于写入或擦除数据的时间段。半导体存储装置还包括静态随机存取存储器，用于存储用于将逻辑扇区号转换为已接受写和擦除指令的闪存的那些区域的物理扇区号的转换表。例如，半导体盘盒可以连接到个人计算机中的标准总线。

77. 发明授权

US5670969A Information processing apparatus 失效
标题翻译：信息处理装置
公开(公告)号：US5670969A
公开(公告)日：1997-09-23
申请号：US953953
申请日：1992-09-29
申请人： Hajime Yamagami , Takashi Tsunehiro
发明人： Hajime Yamagami , Takashi Tsunehiro
IPC分类号： G06F1/16 , G06F3/147 , G09G5/00
CPC分类号： G06F1/1645 , G06F1/1654 , G06F1/1683 , G06F3/147 , Y10S345/903
摘要： An information processing apparatus comprises a main body of the information processing apparatus and a display device which is replaceably connected to the main body. The main body comprises a CPU, a system bus connected to the CPU and a main body connector connected to the system bus. The display device comprises a panel connector connected to the main body connector, a display, and a controller connected to the panel connector for controlling the display in accordance with information received from the CPU.
摘要翻译：信息处理设备包括信息处理设备的主体和可替换地连接到主体的显示设备。主体包括CPU，连接到CPU的系统总线和连接到系统总线的主体连接器。显示装置包括连接到主体连接器的面板连接器，显示器和连接到面板连接器的控制器，用于根据从CPU接收的信息来控制显示。

78. 发明授权

US5644539A Storage device employing a flash memory 失效
标题翻译：采用闪存的存储设备
公开(公告)号：US5644539A
公开(公告)日：1997-07-01
申请号：US981438
申请日：1992-11-25
申请人： Hajime Yamagami , Kouichi Terada , Yoshihiro Hayashi , Takashi Tsunehiro , Kunihiro Katayama , Kenichi Kaki , Takeshi Furuno
发明人： Hajime Yamagami , Kouichi Terada , Yoshihiro Hayashi , Takashi Tsunehiro , Kunihiro Katayama , Kenichi Kaki , Takeshi Furuno
IPC分类号： G06F3/06 , G11C16/10 , G11C29/00 , G11C13/00
CPC分类号： G11C29/765 , G06F3/0601 , G06F3/0616 , G06F3/0659 , G06F3/0679 , G11C16/102 , G06F2003/0694 , G06F2212/2022 , G06F3/0664
摘要： A semiconductor disk wherein a flash memory into which data is rewritten in block unit is employed as a storage medium, said semiconductor disk comprises a data memory in which file data are stored, a substitutive memory which substitutes for blocks of errors in the data memory, an error memory in which error information of the data memory are stored, and a memory controller which reads data out of, writes data into and erases data from the data memory, the substitutive memory and the error memory. Since the write errors of the flash memory can be remedied, the service life of the semiconductor disk can be increased.
摘要翻译：采用其中以块为单位重写数据的闪存的半导体盘作为存储介质，所述半导体盘包括存储文件数据的数据存储器，代替数据存储器中的错误块的替换存储器，存储有数据存储器的错误信息的错误存储器，以及从数据存储器，替代存储器和错误存储器读取数据并将数据写入数据存储器，替代存储器和错误存储器的数据的存储器控制器。由于可以补救闪速存储器的写入错误，所以可以提高半导体盘的使用寿命。

79. 发明授权

US08031536B2 Storage device employing a flash memory 失效
标题翻译：采用闪存的存储设备
公开(公告)号：US08031536B2
公开(公告)日：2011-10-04
申请号：US12748497
申请日：2010-03-29
申请人： Hajime Yamagami , Kouichi Terada , Yoshihiro Hayashi , Takashi Tsunehiro , Kunihiro Katayama , Kenichi Kaki , Takeshi Furuno
发明人： Hajime Yamagami , Kouichi Terada , Yoshihiro Hayashi , Takashi Tsunehiro , Kunihiro Katayama , Kenichi Kaki , Takeshi Furuno
IPC分类号： G11C7/10
CPC分类号： G11C29/765 , G06F3/0601 , G06F3/0616 , G06F3/0619 , G06F3/064 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F2003/0694 , G06F2212/2022 , G11C16/102 , G11C16/349
摘要： A semiconductor disk wherein a flash memory into which data is rewritten in block unit is employed as a storage medium, the semiconductor disk including a data memory in which file data are stored, a substitutive memory which substitutes for blocks of errors in the data memory, an error memory in which error information of the data memory are stored, and a memory controller which reads data out of, writes data into and erases data from the data memory, the substitutive memory and the error memory. Since the write errors of the flash memory can be remedied, the service life of the semiconductor disk can be increased.
摘要翻译：采用其中以块为单位重写数据的闪存的半导体盘作为存储介质，该半导体盘包括存储有文件数据的数据存储器，代替数据存储器中的错误块的替换存储器，存储有数据存储器的错误信息的错误存储器，以及从数据存储器，替代存储器和错误存储器读取数据并将数据写入数据存储器，替代存储器和错误存储器的数据的存储器控制器。由于可以补救闪速存储器的写入错误，所以可以提高半导体盘的使用寿命。

80. 发明授权

US08001319B2 Semiconductor storage device 失效
标题翻译：半导体存储设备
公开(公告)号：US08001319B2
公开(公告)日：2011-08-16
申请号：US12466907
申请日：2009-05-15
申请人： Kenichi Kaki , Kunihiro Katayama , Takashi Tsunehiro
发明人： Kenichi Kaki , Kunihiro Katayama , Takashi Tsunehiro
IPC分类号： G06F12/08
CPC分类号： G06F3/0688 , G06F3/061 , G06F3/0611 , G06F3/0613 , G06F3/0652 , G06F3/0656 , G06F3/0659 , G06F3/0679 , G11C16/102 , G11C16/32
摘要： A semiconductor storage apparatus is coupled with a system bus to receive a write request accompanied with first and second blocks of data, which are stored in nonvolatile semiconductor memories. A control device sends a first erase command to one of the nonvolatile memories to initiate a first internal erase operation of data within the nonvolatile memories. After the first erase command has been sent, the control device sends a second erase command to another one of the nonvolatile memories, to initiate a second internal erase operation of data within the other nonvolatile memory.
摘要翻译：半导体存储装置与系统总线耦合以接收伴随有第一和第二数据块的写入请求，其存储在非易失性半导体存储器中。控制装置向第一非易失性存储器之一发送第一擦除命令，以启动非易失性存储器内的数据的第一内部擦除操作。在第一擦除命令被发送之后，控制装置向另一个非易失性存储器发送第二擦除命令，以启动另一个非易失性存储器内的数据的第二内部擦除操作。

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