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71. 发明授权

US08847338B2 Method for forming a self-aligned hard mask for contact to a tunnel junction 有权
标题翻译：形成用于与隧道结接触的自对准硬掩模的方法
公开(公告)号：US08847338B2
公开(公告)日：2014-09-30
申请号：US13426845
申请日：2012-03-22
申请人： Solomon Assefa , Sivananda K. Kanakasabapathy
发明人： Solomon Assefa , Sivananda K. Kanakasabapathy
IPC分类号： H01L29/84
CPC分类号： H01L29/82 , H01L27/222 , H01L43/08 , H01L43/12
摘要： A magnetic memory cell having a self-aligned hard mask for contact to a magnetic tunnel junction is provided. For example, a magnetic memory cell includes a magnetic storage element formed on a semiconductor substrate, and a hard mask that is self-aligned with the magnetic storage element. The hard mask includes a hard mask material layer formed on an upper surface of a magnetic stack in the magnetic storage element, an anti-reflective coating (ARC) layer formed on at least a portion of an upper surface of the hard mask material layer, wherein the ARC layer is selected to be removable by a wet etch, and a photoresist layer formed on at least a portion of an upper surface of the ARC layer. The selected portions of the ARC layer and photoresist layer are removed in a same processing step with wet etch techniques without interference to the magnetic stack.
摘要翻译：提供具有用于与磁性隧道结接触的自对准硬掩模的磁存储单元。例如，磁存储单元包括形成在半导体衬底上的磁存储元件和与磁存储元件自对准的硬掩模。硬掩模包括形成在磁性存储元件中的磁性堆叠的上表面上的硬掩模材料层，形成在硬掩模材料层的上表面的至少一部分上的抗反射涂层（ARC）层，其中所述ARC层被选择为通过湿蚀刻可去除，以及形成在所述ARC层的上表面的至少一部分上的光致抗蚀剂层。通过湿蚀刻技术在相同的处理步骤中除去ARC层和光致抗蚀剂层的选定部分，而不会干扰磁性堆叠。

72. 发明申请

US20140064729A1 POLARIZATION DIVERSE DEMULTIPLEXING 有权
标题翻译：极化多重分解
公开(公告)号：US20140064729A1
公开(公告)日：2014-03-06
申请号：US13603811
申请日：2012-09-05
申请人： Solomon Assefa , Douglas M. Gill , William M. Green
发明人： Solomon Assefa , Douglas M. Gill , William M. Green
IPC分类号： H04J14/06
CPC分类号： G02B6/12023 , G02B6/2793 , G02B6/293
摘要： An optical demultiplexing device includes a first portion operative to receive an input optical signal having a first polarization, a second polarization and multiple channels, and split the input optical signal into a first optical signal having the first polarization and a second optical signal having the first polarization, and an optical demultiplexing portion communicatively connected to the polarization splitter portion, the optical demultiplexing portion operative to receive a combination of the first optical signal and the second optical signal, and output each channel of the first optical signal and the second optical signal to a photodetector device corresponding to each channel.
摘要翻译：光解复用装置包括第一部分，其操作以接收具有第一偏振光，第二偏振光和多通道的输入光信号，并将输入光信号分离为具有第一偏振的第一光信号和具有第一偏振的第二光信号偏振光，以及通信地连接到偏振分离器部分的光解复用部分，光解复用部分用于接收第一光信号和第二光信号的组合，并将第一光信号和第二光信号的每个通道输出到对应于每个通道的光电检测器装置。

73. 发明申请

US20140064656A1 POLARIZATION DIVERSE DEMULTIPLEXING 有权
标题翻译：极化多重分解
公开(公告)号：US20140064656A1
公开(公告)日：2014-03-06
申请号：US13611229
申请日：2012-09-12
申请人： Solomon Assefa , Douglas M. Gill , William M. Green
发明人： Solomon Assefa , Douglas M. Gill , William M. Green
IPC分类号： G02B6/00
CPC分类号： G02B6/12023 , G02B6/2793 , G02B6/293
摘要： A method for demultiplexing an optical signal includes receiving a multi polarization optical signal, separating the multi polarization optical signal into a first polarization optical signal and a second polarization optical signal, rotating a polarization of the first polarization optical signal to match a polarization of the second polarization optical signal, routing the first polarization optical signal and the second polarization optical signal to a common demultiplexing device, outputting a channel of the first polarization optical signal and the second polarization optical signal to a common photodetector.
摘要翻译：一种用于解复用光信号的方法包括：接收多偏振光信号，将多偏振光信号分离为第一偏振光信号和第二偏振光信号，旋转第一偏振光信号的偏振以匹配第二偏振光信号的偏振偏振光信号，将第一偏振光信号和第二偏振光信号路由到公共解复用器件，将第一偏振光信号和第二偏振光信号的通道输出到公共光电检测器。

74. 发明授权

US08129811B2 Techniques for three-dimensional circuit integration 有权
标题翻译：三维电路集成技术
公开(公告)号：US08129811B2
公开(公告)日：2012-03-06
申请号：US13088339
申请日：2011-04-16
申请人： Solomon Assefa , Kuan-Neng Chen , Steven J. Koester , Yuri A. Vlasov
发明人： Solomon Assefa , Kuan-Neng Chen , Steven J. Koester , Yuri A. Vlasov
IPC分类号： H01L33/00
CPC分类号： H01L27/0688
摘要： Integrated circuits having complementary metal-oxide semiconductor (CMOS) and photonics circuitry and techniques for three-dimensional integration thereof are provided. In one aspect, a three-dimensional integrated circuit comprises a bottom device layer and a top device layer. The bottom device layer comprises a digital CMOS circuitry layer; and a first bonding oxide layer adjacent to the digital CMOS circuitry layer. The top device layer comprises a substrate; an analog CMOS and photonics circuitry layer formed in a silicon-on-insulator (SOI) layer adjacent to the substrate, the SOI layer having a buried oxide (BOX) with a thickness of greater than or equal to about one micrometer; and a second bonding oxide layer adjacent to a side of the analog CMOS and photonics circuitry layer opposite the substrate. The bottom device layer is bonded to the top device layer by an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer.
摘要翻译：提供了具有互补金属氧化物半导体（CMOS）的集成电路和用于其三维集成的光子电路和技术。一方面，三维集成电路包括底部器件层和顶部器件层。底部器件层包括数字CMOS电路层; 以及与数字CMOS电路层相邻的第一结合氧化物层。顶部器件层包括衬底; 形成在与衬底相邻的绝缘体上硅（SOI）层中的模拟CMOS和光子电路层，所述SOI层具有厚度大于或等于约1微米的掩埋氧化物（BOX）; 以及与模拟CMOS和与衬底相对的光子电路层的一侧相邻的第二结合氧化物层。底部器件层通过第一接合氧化物层和第二接合氧化物层之间的氧化物 - 氧化物键接合到顶部器件层。

75. 发明授权

US08111724B2 Temperature control device for optoelectronic devices 有权
标题翻译：光电器件温度控制装置
公开(公告)号：US08111724B2
公开(公告)日：2012-02-07
申请号：US12498463
申请日：2009-07-07
申请人： Solomon Assefa , William M. Green , Younghee Kim , Joris Van Campenhout , Yurii Vlasov
发明人： Solomon Assefa , William M. Green , Younghee Kim , Joris Van Campenhout , Yurii Vlasov
IPC分类号： H01S5/00
CPC分类号： H01L35/34 , G02B6/12004 , G02B6/1347 , G02B2006/12069 , G02F1/0147 , G02F1/025
摘要： Current may be passed through an n-doped semiconductor region, a recessed metal semiconductor alloy portion, and a p-doped semiconductor region so that the diffusion of majority charge carriers in the doped semiconductor regions transfers heat from or into the semiconductor waveguide through Peltier-Seebeck effect. Further, a temperature control device may be configured to include a metal semiconductor alloy region located in proximity to an optoelectronic device, a first semiconductor region having a p-type doping, and a second semiconductor region having an n-type doping. The temperature of the optoelectronic device may thus be controlled to stabilize the performance of the optoelectronic device.
摘要翻译：电流可以通过n掺杂半导体区域，凹陷金属半导体合金部分和p掺杂半导体区域，使得掺杂半导体区域中的多数电荷载流子的扩散通过Peltier- 塞贝克效应。此外，温度控制装置可以被配置为包括位于光电子器件附近的金属半导体合金区域，具有p型掺杂的第一半导体区域和具有n型掺杂的第二半导体区域。因此可以控制光电子器件的温度以稳定光电器件的性能。

76. 发明申请

US20110049655A1 PILLAR-BASED INTERCONNECTS FOR MAGNETORESISTIVE RANDOM ACCESS MEMORY 有权
标题翻译：用于磁阻随机存取存储器的基于柱状的互连
公开(公告)号：US20110049655A1
公开(公告)日：2011-03-03
申请号：US12549799
申请日：2009-08-28
申请人： Solomon Assefa , Michael C. Gaidis , Eric A. Joseph , Eugene J. O'Sullivan
发明人： Solomon Assefa , Michael C. Gaidis , Eric A. Joseph , Eugene J. O'Sullivan
IPC分类号： H01L43/08 , H01L43/12
CPC分类号： H01L43/12 , H01L27/222 , H01L43/08
摘要： A semiconductor device includes a substrate including an M2 patterned area. A VA pillar structure is formed over the M2 patterned area. The VA pillar structure includes a substractively patterned metal layer. The VA pillar structure is a sub-lithographic contact. An MTJ stack is formed over the oxide layer and the metal layer of the VA pillar. A size of the MTJ stack and a shape anisotropy of the MTJ stack are independent of a size and a shape anisotropy of the sub-lithographic contact.
摘要翻译：半导体器件包括包括M2图案化区域的衬底。在M2图案化区域上形成VA柱结构。 VA柱结构包括一个减少图案化的金属层。 VA柱结构是亚光刻接触。在氧化物层和VA柱的金属层上形成MTJ堆叠。 MTJ叠层的尺寸和MTJ叠层的形状各向异性独立于亚光刻触点的尺寸和形状各向异性。

77. 发明授权

US07825000B2 Method for integration of magnetic random access memories with improved lithographic alignment to magnetic tunnel junctions 有权
标题翻译：磁性随机存取存储器与磁性隧道结的改进的光刻对准的集成方法
公开(公告)号：US07825000B2
公开(公告)日：2010-11-02
申请号：US11850427
申请日：2007-09-05
申请人： Sivananda K. Kanakasabapathy , Solomon Assefa
发明人： Sivananda K. Kanakasabapathy , Solomon Assefa
IPC分类号： H01L21/76 , H01L21/00
CPC分类号： H01L43/12 , H01L23/544 , H01L27/222 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： A magnetic memory device including a Magnetic Tunnel Junction (MTJ) device comprises a substrate and Front End of Line (FEOL) circuitry. A Via level (VA) InterLayer Dielectric (ILD) layer, a bottom conductor layer, and an MTJ device formed over the top surface of the VA ILD layer are formed over a portion of the substrate. An alignment region including alignment marks extends through the bottom conductor layer and extends down into the device below the top surface of the VA ILD layers is juxtaposed with the MJT device.
摘要翻译：包括磁隧道结（MTJ）装置的磁存储器件包括基片和前端线（FEOL）电路。形成在VA ILD层的顶表面上方的通过级（VA）层间绝缘（ILD）层，底部导体层和形成在MTI器件上的MTJ器件。包括对准标记的对准区域延伸穿过底部导体层并向下延伸到VA ILD层的顶表面下方的装置与MJT装置并置。

78. 发明授权

US07803639B2 Method of forming vertical contacts in integrated circuits 有权
标题翻译：在集成电路中形成垂直触点的方法
公开(公告)号：US07803639B2
公开(公告)日：2010-09-28
申请号：US11619623
申请日：2007-01-04
申请人： Solomon Assefa , Michael C. Gaidis , John P. Hummel , Sivananda K. Kanakasabapathy
发明人： Solomon Assefa , Michael C. Gaidis , John P. Hummel , Sivananda K. Kanakasabapathy
IPC分类号： H01L21/00 , H01L21/4763 , H01L21/44
CPC分类号： H01L43/12 , H01L21/76807 , H01L21/76816
摘要： A method of forming vertical contacts in an integrated circuit that couple one or more metal lines in a given metallization level to first and second features occupying different levels in the integrated circuit comprises various processing steps. A first etch stop layer is formed overlying at least of portion of the first feature while a second etch stop layer is formed overlying at least a portion of the second feature. An ILD layer is formed overlying the first and second etch stop layers. A photolithographic mask is formed overlying the ILD layer. The photolithographic mask defines a first opening over the first feature and a second opening over the second feature. A first etch process etches a first hole in the ILD layer through the first opening in the photolithographic mask that lands on the first etch stop layer and etches a second hole in the ILD layer through the second opening that lands on the second etch stop layer. Subsequently, a second etch process further etches the first hole so that it lands on the first feature.
摘要翻译：在集成电路中形成垂直触点的方法，其将给定金属化水平中的一个或多个金属线耦合到在集成电路中占据不同电平的第一和第二特征包括各种处理步骤。形成第一蚀刻停止层，覆盖第一特征的至少一部分，而形成第二蚀刻停止层，覆盖第二特征的至少一部分。形成覆盖在第一和第二蚀刻停止层上的ILD层。在ILD层上形成光刻掩模。光刻掩模限定第一特征上的第一开口和第二特征上的第二开口。第一蚀刻工艺通过位于第一蚀刻停止层上的光刻掩模中的第一开口蚀刻ILD层中的第一孔，并通过第二开口蚀刻ILD层中的第二孔，该第二孔位于第二蚀刻停止层上。随后，第二蚀刻工艺进一步蚀刻第一孔使其落在第一特征上。

79. 发明申请

US20090291388A1 Method for Forming a Self-Aligned Hard Mask for Contact to a Tunnel Junction 失效
标题翻译：形成用于接触隧道结的自对准硬掩模的方法
公开(公告)号：US20090291388A1
公开(公告)日：2009-11-26
申请号：US12126245
申请日：2008-05-23
申请人： Solomon Assefa , Sivananda K. Kanakasabapathy
发明人： Solomon Assefa , Sivananda K. Kanakasabapathy
IPC分类号： G03F7/004 , G03F7/26
CPC分类号： H01L29/82 , H01L27/222 , H01L43/08 , H01L43/12
摘要： A method of forming a hard mask in a semiconductor device which is self-aligned with a MTJ formed in the device is provided. The method includes the steps of: forming a hard mask material layer on an upper surface of a magnetic stack in the MTJ; forming an anti-reflective coating (ARC) layer on at least a portion of an upper surface of the hard mask material layer, the ARC layer being selected to be removable by a wet etch; forming a photoresist layer on at least a portion of an upper surface of the ARC layer; removing at least a portion of the photoresist layer and the ARC layer to thereby expose at least a portion of the hard mask material layer; etching the hard mask material layer to remove the exposed portion of the hard mask material layer; and performing a wet strip to remove remaining portions of the ARC layer and photoresist layer in a same processing step without interference to the magnetic stack.
摘要翻译：提供了在与设备中形成的MTJ自对准的半导体器件中形成硬掩模的方法。该方法包括以下步骤：在MTJ的磁性堆叠的上表面上形成硬掩模材料层; 在所述硬掩模材料层的上表面的至少一部分上形成抗反射涂层（ARC）层，所述ARC层被选择为通过湿法蚀刻可去除; 在所述ARC层的上表面的至少一部分上形成光致抗蚀剂层; 去除所述光致抗蚀剂层和所述ARC层的至少一部分，从而暴露所述硬掩模材料层的至少一部分; 蚀刻硬掩模材料层以去除硬掩模材料层的暴露部分; 并且在相同的处理步骤中执行湿条以去除ARC层和光致抗蚀剂层的剩余部分而不干扰磁性堆叠。

80. 发明授权

US07505308B1 Systems involving spin-transfer magnetic random access memory 有权
标题翻译：涉及自旋转移磁随机存取存储器的系统
公开(公告)号：US07505308B1
公开(公告)日：2009-03-17
申请号：US12118441
申请日：2008-05-09
申请人： Solomon Assefa , William J. Gallagher , Chung H. Lam , Jonathan Z. Sun
发明人： Solomon Assefa , William J. Gallagher , Chung H. Lam , Jonathan Z. Sun
IPC分类号： G11C11/14 , G11C11/15 , G11C11/16
CPC分类号： G11C11/1675 , G11C11/161 , G11C11/1659 , G11C11/1673
摘要： An exemplary magnetic random access memory system comprising, a spin-current generating portion including, a ferromagnetic film layer, and a conductance layer, a first write portion in electrical contact with the ferromagnetic film including, a selection device, and a first read portion in electrical contact with the conductance layer including, a free layer magnet, a read non-magnetic layer, and a reference layer, a second write portion in electrical contact with the ferromagnetic film, and a second read portion in electrical contact with the conductance layer.
摘要翻译：一种示例性磁性随机存取存储器系统，包括：自旋电流产生部分，包括铁磁膜层和电导层，与铁磁膜电接触的第一写入部分，包括选择装置，以及第一读取部分，与电导层电接触，包括自由层磁体，读非磁性层和参考层，与铁磁膜电接触的第二写入部分和与导电层电接触的第二读取部分。

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