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71. 发明申请

US20050265080A1 Semiconductor nonvolatile memory device 有权
标题翻译：半导体非易失存储器件
公开(公告)号：US20050265080A1
公开(公告)日：2005-12-01
申请号：US11137518
申请日：2005-05-26
申请人： Digh Hisamoto , Kan Yasui , Tetsuya Ishimaru , Shinichiro Kimura , Daisuke Okada
发明人： Digh Hisamoto , Kan Yasui , Tetsuya Ishimaru , Shinichiro Kimura , Daisuke Okada
IPC分类号： G11C11/34 , G11C16/04 , G11C16/12 , G11C16/14 , G11C16/26 , G11C16/34
CPC分类号： G11C16/0425 , G11C16/12 , G11C16/14 , G11C16/26 , G11C16/3454 , G11C16/3459
摘要： An operation scheme for operating stably a semiconductor nonvolatile memory device is provided. When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes. Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.
摘要翻译：提供一种稳定运行半导体非易失性存储器件的操作方案。当在分裂栅极结构的半导体非易失性存储器件中进行热空穴注入时，使用不随时间变化的交叉点来验证热孔注入。因此，可以验证擦除状态，而不知道任何时变变化。此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。

72. 发明申请

US20050176202A1 Nonvolatile semiconductor memory and making method thereof 有权
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US20050176202A1
公开(公告)日：2005-08-11
申请号：US11005015
申请日：2004-12-07
申请人： Digh Hisamoto , Kan Yasui
发明人： Digh Hisamoto , Kan Yasui
IPC分类号： H01L21/8247 , H01L21/00 , H01L21/28 , H01L21/336 , H01L21/8242 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11531 , H01L29/66825
摘要： A nonvolatile semiconductor memory device of a split gate structure having a gate of low resistance suitable to the arrangement of a memory cell array is provided. When being formed of a side wall spacer, a memory gate is formed of polycrystal silicon and then replaced with nickel silicide. Thus, its resistance can be lowered with no effect on the silicidation to the selection gate or the diffusion layer.
摘要翻译：提供了具有适合于存储单元阵列的布置的具有低电阻的栅极的分离栅极结构的非易失性半导体存储器件。当由侧壁间隔物形成时，存储栅由多晶硅形成，然后被硅化镍替代。因此，其电阻可以降低，而对选择栅极或扩散层的硅化物没有影响。

73. 发明授权

US08410543B2 Semiconductor storage device and manufacturing method thereof 有权
标题翻译：半导体存储装置及其制造方法
公开(公告)号：US08410543B2
公开(公告)日：2013-04-02
申请号：US11965391
申请日：2007-12-27
申请人： Itaru Yanagi , Toshiyuki Mine , Hirotaka Hamamura , Digh Hisamoto , Yasuhiro Shimamoto
发明人： Itaru Yanagi , Toshiyuki Mine , Hirotaka Hamamura , Digh Hisamoto , Yasuhiro Shimamoto
IPC分类号： H01L27/088
CPC分类号： H01L29/792 , G11C16/0466 , H01L21/28273 , H01L21/28282 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11568 , H01L27/11573 , H01L29/42344 , H01L29/513
摘要： In a non-volatile memory in which writing/erasing is performed by changing a total charge amount by injecting electrons and holes into a silicon nitride film serving as a charge accumulation layer, in order to realize a high efficiency of a hole injection from a gate electrode, the gate electrode of a memory cell comprises a laminated structure made of a plurality of polysilicon films with different impurity concentrations, for example, a two-layered structure comprising a p-type polysilicon film with a low impurity concentration and a p+-type polysilicon film with a high impurity concentration deposited thereon.
摘要翻译：在通过将电子和空穴注入到用作电荷累积层的氮化硅膜中来改变总电荷量进行写/擦除的非易失性存储器中，为了实现从栅极的空穴注入的高效率电极，存储单元的栅电极包括由具有不同杂质浓度的多个多晶硅膜制成的层压结构，例如包括具有低杂质浓度的p型多晶硅膜和p +型的双层结构沉积有高杂质浓度的多晶硅膜。

74. 发明授权

US08319265B2 Semiconductor device with improved common source arrangement for adjacent non-volatile memory cells 有权
标题翻译：具有改进的用于相邻非易失性存储器单元的共同源排列的半导体器件
公开(公告)号：US08319265B2
公开(公告)日：2012-11-27
申请号：US12580289
申请日：2009-10-16
申请人： Tsutomu Okazaki , Daisuke Okada , Kyoya Nitta , Toshihiro Tanaka , Akira Kato , Toshikazu Matsui , Yasushi Ishii , Digh Hisamoto , Kan Yasui
发明人： Tsutomu Okazaki , Daisuke Okada , Kyoya Nitta , Toshihiro Tanaka , Akira Kato , Toshikazu Matsui , Yasushi Ishii , Digh Hisamoto , Kan Yasui
IPC分类号： H01L29/792
CPC分类号： H01L27/1157 , G11C16/0425 , H01L21/28282 , H01L27/0207 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L29/0649 , H01L29/4234 , H01L29/42344 , H01L29/518 , H01L29/66833 , H01L29/792
摘要： A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.
摘要翻译：半导体存储器阵列包括具有第一电荷存储层和第一非易失性存储单元的第一非易失性存储单元，第一非易失性存储单元与第一存储单元相邻，具有第二电荷存储层和第二栅电极。第一电极和第二电极在垂直于第一方向的第二方向上延伸，第一电极具有在第一方向上朝向第二电极延伸的第一接触部分，并且第二电极具有朝向第一电极的第二接触部分第一个方向第一和第二接触位置分别沿第二方向移动，第一电极和第一接触部分与第二电极和第二接触部分电气分离。

75. 发明申请

US20120287959A1 GERMANIUM LIGHT-EMITTING ELEMENT 审中-公开
标题翻译：锗发光元件
公开(公告)号：US20120287959A1
公开(公告)日：2012-11-15
申请号：US13521533
申请日：2011-01-28
申请人： Kazuki Tani , Shinichi Saito , Toshiki Sugawara , Youngkun Lee , Digh Hisamoto , Makoto Miura , Katsuya Oda
发明人： Kazuki Tani , Shinichi Saito , Toshiki Sugawara , Youngkun Lee , Digh Hisamoto , Makoto Miura , Katsuya Oda
IPC分类号： H01S5/22
CPC分类号： H01S5/3223 , H01L33/34 , H01L33/62 , H01L2924/0002 , H01S5/0207 , H01S5/021 , H01S5/0424 , H01S5/0425 , H01S5/1231 , H01S5/4031 , H01L2924/00
摘要： A germanium light-emitting device emitting light at high efficiency is provided by using germanium of small threading dislocation density. A germanium laser diode having a high quality germanium light-emitting layer is attained by using germanium formed over silicon dioxide. A germanium laser diode having a carrier density higher than the carrier density limit that can be injected by existent n-type germanium can be provided using silicon as an n-type electrode.
摘要翻译：通过使用小螺纹位错密度的锗来提供高效率发光的锗发光器件。通过使用在二氧化硅上形成的锗来获得具有高质量锗发光层的锗激光二极管。可以使用硅作为n型电极来提供具有高于可由现有的n型锗注入的载流子密度极限的载流子密度的锗激光二极管。

76. 发明授权

US08084810B2 Fabrication method and structure of semiconductor non-volatile memory device 有权
标题翻译：半导体非易失性存储器件的制造方法和结构
公开(公告)号：US08084810B2
公开(公告)日：2011-12-27
申请号：US12648796
申请日：2009-12-29
申请人： Digh Hisamoto , Shinichiro Kimura , Kan Yasui , Nozomu Matsuzaki
发明人： Digh Hisamoto , Shinichiro Kimura , Kan Yasui , Nozomu Matsuzaki
IPC分类号： H01L21/336
CPC分类号： H01L27/11531 , H01L21/28282 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/11568 , H01L29/42344 , H01L29/792
摘要： A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.
摘要翻译：提供具有良好写入/擦除特性的非易失性半导体存储器件。通过栅极绝缘体在半导体衬底的p型阱上形成选择栅极，并且通过由氧化硅膜，氮化硅膜和氮化硅膜构成的层叠膜在p型阱上形成存储栅极氧化硅膜。存储器栅极通过层叠膜与选择栅极相邻。在p型阱中的选择栅极和存储栅极的两侧的区域中，形成用作源极和漏极的n型杂质扩散层。由选择栅极控制的区域和由位于所述杂质扩散层之间的沟道区域中的存储栅极控制的区域具有彼此不同的杂质的电荷密度。

77. 发明授权

US07915666B2 Nonvolatile semiconductor memory devices with charge injection corner 有权
标题翻译：具有电荷注入角的非易失性半导体存储器件
公开(公告)号：US07915666B2
公开(公告)日：2011-03-29
申请号：US12124143
申请日：2008-05-20
申请人： Kan Yasui , Tetsuya Ishimaru , Digh Hisamoto , Yasuhiro Shimamoto
发明人： Kan Yasui , Tetsuya Ishimaru , Digh Hisamoto , Yasuhiro Shimamoto
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , G11C16/0425 , G11C16/10 , H01L27/11526 , H01L27/11546 , H01L29/42344
摘要： An erase method where a corner portion on which an electric field concentrates locally is provided on the memory gate electrode, and charges in the memory gate electrode are injected into a charge trap film in a gate dielectric with Fowler-Nordheim tunneling operation is used. Since current consumption at the time of erase can be reduced by the Fowler-Nordheim tunneling, a power supply circuit area of a memory module can be reduced. Since write disturb resistance can be improved, a memory array area can be reduced by adopting a simpler memory array configuration. Owing to both the effects, an area of the memory module can be largely reduced, so that manufacturing cost can be reduced. Further, since charge injection centers of write and erase coincide with each other, so that (program and erase) endurance is improved.
摘要翻译：在存储栅电极上设置有局部集中电场的角部的擦除方法，并且使用Fowler-Nordheim隧道操作将存储栅电极中的电荷注入栅极电介质中的电荷陷阱膜。由于通过Fowler-Nordheim隧道可以减少擦除时的电流消耗，因此可以减少存储器模块的电源电路区域。由于可以提高写入干扰电阻，所以可以通过采用更简单的存储器阵列配置来减少存储器阵列区域。由于这两个效果，可以大大减少存储器模块的面积，从而可以降低制造成本。此外，由于写入和擦除的电荷注入中心彼此一致，所以（编程和擦除）耐久性得到改善。

78. 发明申请

US20110039385A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110039385A1
公开(公告)日：2011-02-17
申请号：US12912609
申请日：2010-10-26
申请人： Yasuhiro Shimamoto , Digh Hisamoto , Tetsuya Ishimaru , Shinichiro Kimura
发明人： Yasuhiro Shimamoto , Digh Hisamoto , Tetsuya Ishimaru , Shinichiro Kimura
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , G11C16/0425 , H01L21/28282 , H01L21/31155 , H01L27/105 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L27/11568 , H01L29/42344 , H01L29/66833
摘要： Performance and reliability of a semiconductor device including a non-volatile memory are improved. A memory cell of the non-volatile memory includes, over an upper portion of a semiconductor substrate, a select gate electrode formed via a first dielectric film and a memory gate electrode formed via a second dielectric film formed of an ONO multilayered film having a charge storing function. The first dielectric film functions as a gate dielectric film, and includes a third dielectric film made of silicon oxide or silicon oxynitride and a metal-element-containing layer made of a metal oxide or a metal silicate formed between the select gate electrode and the third dielectric film. A semiconductor region positioned under the memory gate electrode and the second dielectric film has a charge density of impurities lower than that of a semiconductor region positioned under the select gate electrode and the first dielectric film.
摘要翻译：提高了包括非易失性存储器的半导体器件的性能和可靠性。非易失性存储器的存储单元包括在半导体衬底的上部上的经由第一电介质膜形成的选择栅电极和通过由具有电荷的ONO多层膜形成的第二电介质膜形成的存储栅电极存储功能。第一介质膜用作栅极电介质膜，并且包括由氧化硅或氮氧化硅制成的第三电介质膜和由选择栅电极和第三电极之间形成的金属氧化物或金属硅酸盐构成的含金属元素层电介质膜。位于存储栅电极下方的半导体区域和第二电介质膜的电荷密度低于位于选择栅电极和第一电介质膜下方的半导体区域的电荷密度。

79. 发明授权

US07847331B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07847331B2
公开(公告)日：2010-12-07
申请号：US11030900
申请日：2005-01-10
申请人： Tetsuya Ishimaru , Digh Hisamoto , Kan Yasui , Shinichiro Kimura
发明人： Tetsuya Ishimaru , Digh Hisamoto , Kan Yasui , Shinichiro Kimura
IPC分类号： H01L29/792
CPC分类号： G11C16/0466 , H01L21/28282 , H01L29/66833 , H01L29/792
摘要： In a situation where a memory cell includes an ONO film, which comprises a silicon nitride film for charge storage and oxide films positioned above and below the silicon nitride film; a memory gate above the ONO film; a select gate, which is adjacent to a lateral surface of the memory gate via the ONO film; a gate insulator positioned below the select gate; a source region; and a drain region, an erase operation is performed by injecting holes generated by BTBT into the silicon nitride film while applying a positive potential to the source region, applying a negative potential to the memory gate, applying a positive potential to the select gate, and flowing a current from the drain region to the source region, thus improving the characteristics of a nonvolatile semiconductor memory device.
摘要翻译：在存储单元包括ONO膜的情况下，其包括用于电荷存储的氮化硅膜和位于氮化硅膜上方和下方的氧化膜; 在ONO电影上方的记忆门; 选择栅极，其经由ONO膜与存储栅的侧表面相邻; 位于选择门下方的栅极绝缘体; 源区; 和漏极区域，通过将BTBT产生的空穴注入氮化硅膜，同时向源极区域施加正电位，向存储栅极施加负电位，向选择栅极施加正电位，进行擦除操作，以及使电流从漏极区域流向源极区域，从而改善非易失性半导体存储器件的特性。

80. 发明授权

US07709315B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07709315B2
公开(公告)日：2010-05-04
申请号：US11773842
申请日：2007-07-05
申请人： Naoki Tega , Hiroshi Miki , Yasuhiro Shimamoto , Digh Hisamoto , Tetsuya Ishimaru
发明人： Naoki Tega , Hiroshi Miki , Yasuhiro Shimamoto , Digh Hisamoto , Tetsuya Ishimaru
IPC分类号： H01L21/8238
CPC分类号： H01L29/792 , B82Y10/00 , H01L21/28273 , H01L21/28282 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L27/11573 , H01L29/42324 , H01L29/4234 , H01L29/42344 , H01L29/66833
摘要： An interface between a bottom oxide film and a silicon nitride film in a neighborhood of a bottom part of a select gate is located at a position as high as or higher than that of an interface between a silicon substrate (p-type well) and a gate insulating film (d≧0) Further, the gate insulating film and the bottom oxide film are successively and smoothly jointed in the neighborhood of the bottom part of the select gate. By this configuration, localization in a distribution of electrons injected into the silicon nitride film in the writing is mitigated and electrons to be left unerased by hot-hole erasing are reduced. Therefore, not only the increase ratio of the electrons left unerased in the writing can be reduced, but also the problem in which the threshold voltage does not decrease to the predetermined voltage in the deletion can be suppressed.
摘要翻译：在选择栅极的底部附近的底部氧化物膜和氮化硅膜之间的界面位于硅衬底（p型阱）和硅衬底（p型阱）之间的界面的高度或更高的位置栅极绝缘膜（d≥0）此外，栅极绝缘膜和底部氧化物膜在选择栅极的底部附近依次平滑地接合。通过这种配置，减轻了在写入中注入到氮化硅膜中的电子分布中的定位，并且减少了通过热孔擦除而未被消除的电子。因此，不仅可以减少在写入时未加电的电子的增加比例，还可以抑制在删除中阈值电压不降低到预定电压的问题。

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