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71. 发明申请

US20120163076A1 SINGLE CHECK MEMORY DEVICES AND METHODS 有权
标题翻译：单次检查记忆装置和方法
公开(公告)号：US20120163076A1
公开(公告)日：2012-06-28
申请号：US12975494
申请日：2010-12-22
申请人： Vishal Sarin , Aaron Yip , Tomoharu Tanaka
发明人： Vishal Sarin , Aaron Yip , Tomoharu Tanaka
IPC分类号： G11C16/34 , G11C16/04 , G11C16/12
CPC分类号： G11C29/50004 , G11C11/5628 , G11C16/0483 , G11C16/3459 , G11C2029/5004 , G11C2211/5621
摘要： Memory devices and methods of operating memory devices are shown. Configurations described include circuits to perform a single check between programming pulses to determine a threshold voltage with respect to desired benchmark voltages. In one example, the benchmark voltages are used to change a programming speed of selected memory cells.
摘要翻译：显示了存储器件和操作存储器件的方法。所描述的配置包括在编程脉冲之间执行单次检查以确定相对于期望的基准电压的阈值电压的电路。在一个示例中，基准电压用于改变所选存储单元的编程速度。

72. 发明申请

US20120117306A1 SENSE OPERATION FLAGS IN A MEMORY DEVICE 有权
标题翻译：在存储器中识别操作标志
公开(公告)号：US20120117306A1
公开(公告)日：2012-05-10
申请号：US12942152
申请日：2010-11-09
申请人： Shafqat Ahmed , Khaled Hasnat , Pranav Kalavade , Krishna Parat , Aaron Yip , Mark A. Helm , Andrew Bicksler
发明人： Shafqat Ahmed , Khaled Hasnat , Pranav Kalavade , Krishna Parat , Aaron Yip , Mark A. Helm , Andrew Bicksler
IPC分类号： G06F12/02 , G06F12/08 , G06F12/00
CPC分类号： G06F3/0625 , G06F3/061 , G06F3/0653 , G06F3/0665 , G06F3/0688 , G06F3/0689 , G06F12/0804 , G06F12/0846 , G06F13/28 , G06F2212/2022 , G06F2212/224 , G06F2212/461 , G11C16/0483 , G11C16/24 , G11C16/26 , Y02D10/14
摘要： Memory devices, methods for programming sense flags, methods for sensing flags, and memory systems are disclosed. In one such memory device, the odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. The even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page.
摘要翻译：公开了存储器件，用于编程感测标志的方法，用于感测标志的方法和存储器系统。在一个这样的存储器件中，标志存储器单元阵列的奇数位线与短路连接到动态数据高速缓存。标记存储单元阵列的偶数位线与动态数据高速缓存断开连接。当读取主存储单元阵列的偶数页时，同时读取包括标志数据的奇数标志存储单元，以便可以确定主存储单元阵列的奇数页是否已被编程。如果标志数据指示奇数页未被编程，则可以调整阈值电压窗口以确定感测到的偶数存储单元页的状态。

73. 发明授权

US08072816B2 Memory block reallocation in a flash memory device 有权
标题翻译：闪存设备中的内存块重新分配
公开(公告)号：US08072816B2
公开(公告)日：2011-12-06
申请号：US12478877
申请日：2009-06-05
申请人： Jin-Man Han , Aaron Yip
发明人： Jin-Man Han , Aaron Yip
IPC分类号： G11C16/06
CPC分类号： G11C8/08 , G06F12/0246 , G11C16/0483 , G11C16/08 , G11C16/3418 , G11C16/3427 , G11C29/76 , G11C29/82 , Y02D10/13
摘要： A non-volatile memory device has the pages of a certain memory block reallocated to other blocks in order to increase decrease disturb and increase reliability. Each of the reallocation blocks that contain the reallocated pages from the desired memory block are coupled to a wordline driver. These wordline drivers have a subset of the global wordlines as inputs. The desired wordline driver is selected by an appropriate select signal from a block decoder and an indication on an appropriate global wordline. This causes the wordline driver to generate a local wordline to the desired block with the reallocated page to be accessed.
摘要翻译：非易失性存储器件具有将特定存储器块的页面重新分配给其他块，以便增加减少的干扰并增加可靠性。包含来自期望的存储器块的重新分配的页面的每个重新分配块被耦合到字线驱动器。这些字线驱动器具有全局字线的一部分作为输入。期望的字线驱动器通过来自块解码器的适当选择信号和适当的全局字线上的指示来选择。这将导致字线驱动程序在要重新分配的页面访问期望块时生成本地字线。

74. 发明申请

US20110235433A1 VERIFYING AN ERASE THRESHOLD IN A MEMORY DEVICE 有权
标题翻译：验证存储器中的擦除阈值
公开(公告)号：US20110235433A1
公开(公告)日：2011-09-29
申请号：US13153746
申请日：2011-06-06
申请人： Aaron Yip
发明人： Aaron Yip
IPC分类号： G11C16/06
CPC分类号： G11C16/344
摘要： In one or more embodiments, a memory device is disclosed as having an erase verify operation that includes a negative bias on the p-well in which the memory cell or cells being erased are formed. After an erase pulse is applied to the selected cells to be erased, the p-well is biased with the negative voltage and the erase verify operation is performed to determine the erased state of the cell(s).
摘要翻译：在一个或多个实施例中，公开了一种存储器件，其具有擦除验证操作，该擦除验证操作包括在其上形成有擦除存储器单元的p阱上的负偏压。在将擦除脉冲施加到要擦除的所选择的单元之后，p阱被以负电压偏置，并执行擦除验证操作以确定单元的擦除状态。

75. 发明申请

US20100202214A1 VERIFYING AN ERASE THRESHOLD IN A MEMORY DEVICE 有权
标题翻译：验证存储器中的擦除阈值
公开(公告)号：US20100202214A1
公开(公告)日：2010-08-12
申请号：US12762640
申请日：2010-04-19
申请人： Aaron Yip
发明人： Aaron Yip
IPC分类号： G11C16/06
CPC分类号： G11C16/344
摘要： In one or more embodiments, a memory device is disclosed as having an erase verify operation that includes a negative bias on the p-well in which the memory cell or cells being erased are formed. After an erase pulse is applied to the selected cells to be erased, the p-well is biased with the negative voltage and the erase verify operation is performed to determine the erased state of the cell(s).
摘要翻译：在一个或多个实施例中，公开了一种存储器件，其具有擦除验证操作，该擦除验证操作包括在其上形成有擦除存储器单元的p阱上的负偏压。在将擦除脉冲施加到要擦除的所选择的单元之后，p阱被以负电压偏置，并执行擦除验证操作以确定单元的擦除状态。

76. 发明授权

US07688630B2 Programming memory devices 失效
标题翻译：编程存储器件
公开(公告)号：US07688630B2
公开(公告)日：2010-03-30
申请号：US12370810
申请日：2009-02-13
申请人： Dzung H. Nguyen , Benjamin Louie , Hagop A. Nazarian , Aaron Yip , Jin-Man Han
发明人： Dzung H. Nguyen , Benjamin Louie , Hagop A. Nazarian , Aaron Yip , Jin-Man Han
IPC分类号： G11C16/04
CPC分类号： G11C16/10
摘要： A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.
摘要翻译：通过将编程电压施加到包括目标存储器单元的字线，确定目标存储器单元是否被编程来编程存储器件的目标存储器单元，并且如果确定所述编程电压被确定为目标存储单元未编程。在制造存储器件之后，可以选择初始编程电压和阶跃电压。

77. 发明授权

US07546416B2 Method for substantially uninterrupted cache readout 有权
标题翻译：基本上不间断高速缓存读取的方法
公开(公告)号：US07546416B2
公开(公告)日：2009-06-09
申请号：US11474436
申请日：2006-06-26
申请人： Aaron Yip
发明人： Aaron Yip
IPC分类号： G06F13/00 , G11C7/00
CPC分类号： G06F12/0811
摘要： A memory device capable of sequentially outputting multiple pages of cached data while mitigating any interruption typically caused by fetching and transferring operations. The memory device outputs cached data from a first page while data from a second page is fetched into sense amplifier circuitry. When the outputting of the first page reaches a predetermined transfer point, a portion of the fetched data from the second page is transferred into the cache at the same time the remainder of the cached first page is being output. The remainder of the second page is transferred into the cache after all of the data from the first page is output while the outputting of the first portion of the second page begins with little or no interruption.
摘要翻译：一种能够顺利地输出多页缓存数据同时减轻通常由取样和传送操作引起的任何中断的存储器件。存储器件从第一页输出缓存的数据，而来自第二页的数据被提取到读出放大器电路中。当第一页的输出到达预定的传送点时，来自第二页的获取的数据的一部分在被缓存的第一页的其余部分被输出的同时被传送到高速缓存。在第二页的第一部分的输出以很少或没有中断的情况下开始输出来自第一页的所有数据之后，第二页的其余部分被传送到高速缓存。

78. 发明申请

US20080151638A1 SELECTIVE THRESHOLD VOLTAGE VERIFICATION AND COMPACTION 有权
标题翻译：选择性阈值电压验证和压缩
公开(公告)号：US20080151638A1
公开(公告)日：2008-06-26
申请号：US12042021
申请日：2008-03-04
申请人： Aaron Yip
发明人： Aaron Yip
IPC分类号： G11C16/34 , G11C16/10
CPC分类号： G11C16/0483 , G11C16/3404 , G11C16/344 , G11C16/3445
摘要： Non-volatile memory devices for providing selective compaction verification and/or selective compaction to facilitate a tightening of the distribution of threshold voltages in memory devices utilizing a NAND architecture. By providing for compaction verification and/or compaction on less than all word lines of a NAND string, increased tightening of the distribution may be achieved over prior methods performed concurrently on all word lines of a NAND string.
摘要翻译：用于提供选择性压实验证和/或选择性压缩的非易失性存储器件，以利于利用NAND架构在存储器件中紧固阈值电压分布。通过在NAND串的不到所有字线上提供压缩验证和/或压缩，可以通过在NAND串的所有字线上同时执行的现有方法来实现分配的增加的紧缩。

79. 发明授权

US07336536B2 Handling defective memory blocks of NAND memory devices 有权
标题翻译：处理NAND存储器件的缺陷存储块
公开(公告)号：US07336536B2
公开(公告)日：2008-02-26
申请号：US10876878
申请日：2004-06-25
申请人： Benjamin Louie , Aaron Yip
发明人： Benjamin Louie , Aaron Yip
IPC分类号： G11C16/06
CPC分类号： G11C29/832 , G11C16/04 , G11C16/0483 , G11C29/26 , G11C29/789 , G11C29/82 , G11C2029/4402
摘要： Apparatus and methods are provided. A NAND memory device has a memory array comprising a plurality of memory blocks and a volatile latch coupled to each of the memory blocks for selectively preventing testing of the respective memory block coupled thereto when that memory block is a known defective block. A non-volatile latch may also be coupled to each of the memory blocks for permanently preventing access, during normal operation of the memory device, to the respective memory block coupled thereto when that memory block is a known defective block.
摘要翻译：提供了装置和方法。 NAND存储器件具有包括多个存储器块的存储器阵列和耦合到每个存储器块的易失性锁存器，用于当该存储器块是已知缺陷块时选择性地防止与其耦合的存储器块的测试。非易失性锁存器还可以耦合到每个存储器块，以在存储器装置的正常操作期间永久地防止当该存储器块是已知缺陷块时与其耦合的相应存储器块的存取。

80. 发明授权

US07274607B2 Bitline exclusion in verification operation 有权
标题翻译：验证操作中的位线排除
公开(公告)号：US07274607B2
公开(公告)日：2007-09-25
申请号：US11153188
申请日：2005-06-15
申请人： Hendrik Hartono , Aaron Yip , Benjamin Louie
发明人： Hendrik Hartono , Aaron Yip , Benjamin Louie
IPC分类号： G11C7/12
CPC分类号： G11C16/3454 , G11C29/83 , G11C29/832
摘要： Methods and apparatuses for disabling a bad bitline for verification operations, and for determining whether a programming operation have failed, include setting a bitline disable latch for a bad bitline, and inhibiting operation of a program latch if the bitlines is excluded or if a programming operation fails.
摘要翻译：用于禁止用于验证操作的错误位线以及用于确定编程操作是否失败的方法和装置包括为坏位线设置位线禁止锁存器，以及如果排除了位线，则禁止程序锁存器的操作，或者如果编程操作失败了

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