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71. 发明授权

US08773919B2 Semiconductor device and data processing system 有权
标题翻译：半导体器件和数据处理系统
公开(公告)号：US08773919B2
公开(公告)日：2014-07-08
申请号：US13300139
申请日：2011-11-18
申请人： Seiji Miura , Satoru Hanzawa
发明人： Seiji Miura , Satoru Hanzawa
IPC分类号： G11C7/00 , G11C13/00 , G11C8/08 , G11C8/18
CPC分类号： G11C13/0007 , G11C8/08 , G11C8/18 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C13/0097 , G11C2013/0088 , G11C2211/5623
摘要： In a phase change memory, when M bit (8 bits=1 byte) data is written, erase operation and program operation are performed in units of n bit (M>n) data. Further, when M bit data is written, program operation is performed in units of the n bit (M>n) data. Further, when M bit data is read from the memory cell, read operation is performed in units of the n bit (M>n) data. For example, when the data is written into to the phase change memory, the data is not overwritten but program is performed after once erasing the target memory cell. The data size for erasure and the data size for program are made equal. Erase and program operation are performed only for the demanded data size.
摘要翻译：在相变存储器中，当写入M位（8位= 1字节）数据时，以n位（M> n）数据为单位执行擦除操作和编程操作。此外，当写入M位数据时，以n位（M> n）数据为单位执行编程操作。此外，当从存储单元读取M位数据时，以n位（M> n）数据为单位执行读操作。例如，当数据被写入相变存储器时，数据不被重写，而是在擦除目标存储单元之后执行程序。擦除的数据大小和程序的数据大小相等。擦除和编程操作仅针对所需的数据大小执行。

72. 发明授权

US08711650B2 Semiconductor device including multi-chip 失效
标题翻译：半导体器件包括多芯片
公开(公告)号：US08711650B2
公开(公告)日：2014-04-29
申请号：US13533003
申请日：2012-06-26
申请人： Kazushige Ayukawa , Seiji Miura , Yoshikazu Saitou
发明人： Kazushige Ayukawa , Seiji Miura , Yoshikazu Saitou
IPC分类号： G11C8/00
CPC分类号： G11C11/005 , G11C5/04 , G11C5/06 , G11C5/063 , G11C5/143 , G11C8/12 , G11C11/406 , G11C11/40607 , G11C11/40618 , G11C11/4076 , H01L2224/06145 , H01L2224/06156 , H01L2224/32145 , H01L2224/48091 , H01L2224/48137 , H01L2224/48139 , H01L2224/48227 , H01L2924/01039 , H01L2924/01055 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/19041 , H01L2924/3025 , H01L2924/00014 , H01L2924/00
摘要： In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.
摘要翻译：为了实现具有大的存储容量和减少的数据保持电流的存储器，非易失性存储器，SRAM，DRAM和控制电路被模块化成一个封装。控制电路对SRAM和DRAM进行地址分配，并将要长时间保留的数据存储在SRAM中。在DRAM中，多个存储体被分成两组，映射到相同的地址空间，并且交替地刷新集合。它们的多个芯片被堆叠和布置，并且通过使用BGA和芯片到芯片的接合进行布线。

73. 发明授权

US08711637B2 Semiconductor device and data processing system 有权
公开(公告)号：US08711637B2
公开(公告)日：2014-04-29
申请号：US13300139
申请日：2011-11-18
申请人： Seiji Miura , Satoru Hanzawa
发明人： Seiji Miura , Satoru Hanzawa
IPC分类号： G11C7/00
摘要： In a phase change memory, when M bit (8 bits=1 byte) data is written, erase operation and program operation are performed in units of n bit (M>n) data. Further, when M bit data is written, program operation is performed in units of the n bit (M>n) data. Further, when M bit data is read from the memory cell, read operation is performed in units of the n bit (M>n) data. For example, when the data is written into to the phase change memory, the data is not overwritten but program is performed after once erasing the target memory cell. The data size for erasure and the data size for program are made equal. Erase and program operation are performed only for the demanded data size.

74. 发明授权

US08271740B2 Multiport memory and information processing system 有权
标题翻译：多端口内存和信息处理系统
公开(公告)号：US08271740B2
公开(公告)日：2012-09-18
申请号：US12411974
申请日：2009-03-26
申请人： Seiji Miura , Yoshinori Matsui , Kazuhiko Abe , Shoji Kaneko
发明人： Seiji Miura , Yoshinori Matsui , Kazuhiko Abe , Shoji Kaneko
IPC分类号： G06F12/00
CPC分类号： G11C7/1075 , G06F13/1663
摘要： In an information processing system, a plurality of information processing devices CHIP0 and CHIP1 are connected to multiport memory MPMEM0 that has a plurality of ports, and memory areas in multiport memory MPMEM0 can be altered to memory areas occupied by particular ports and memory areas shared by a plurality of ports. At such times, immediately after the occurrence of a request from a port, the status of this request may be supplied from other ports.
摘要翻译：在信息处理系统中，多个信息处理装置CHIP0和CHIP1连接到具有多个端口的多端口存储器MPMEM0，并且多端口存储器MPMEM0中的存储区域可以被改变为由特定端口和存储区域所占用的存储区域多个端口。在这样的时刻，在从端口发出请求之后，可以从其他端口提供该请求的状态。

75. 发明申请

US20120004306A1 EXTERNAL PREPARATION CONTAINING ANALGESIC/ANTI-INFLAMMATORY AGENT 审中-公开
标题翻译：含有毒性/抗炎药的外用制剂
公开(公告)号：US20120004306A1
公开(公告)日：2012-01-05
申请号：US13256057
申请日：2010-03-11
申请人： Seiji Miura , Tsutomu Awamura , Yuhiro Yamazaki , Hironari Fujii
发明人： Seiji Miura , Tsutomu Awamura , Yuhiro Yamazaki , Hironari Fujii
IPC分类号： A61K31/196 , A61P29/00 , A61P25/04
CPC分类号： A61K31/196 , A61K9/7053 , A61K31/05 , A61K45/06 , A61K2300/00
摘要： An external preparation containing the following components (A), (B), and (C): (A) a non-steroidal analgesic/anti-inflammatory agent, (B) a polyhydric alcohol, and (C) a polyoxyalkylene alkyl ether and/or a polyoxyalkylene alkenyl ether. The external preparation of the present invention has improved the drug efficacy of a non-steroidal analgesic/anti-inflammatory agent, and can be effective at a low concentration. The external preparation of the present invention also has excellent appearance.
摘要翻译：含有以下组分（A），（B）和（C）的外用制剂：（A）非甾体镇痛/抗炎剂，（B）多元醇和（C）聚氧化烯烷基醚和 /或聚氧化烯链烯基醚。本发明的外用制剂改善了非甾体止痛/消炎药的药效，可以低浓度有效。本发明的外用制剂也具有优异的外观。

76. 发明授权

US07991954B2 Memory module, memory system, and information device 有权
标题翻译：内存模块，内存系统和信息设备
公开(公告)号：US07991954B2
公开(公告)日：2011-08-02
申请号：US12579223
申请日：2009-10-14
申请人： Seiji Miura , Kazushige Ayukawa
发明人： Seiji Miura , Kazushige Ayukawa
IPC分类号： G06F12/00
CPC分类号： G11C11/005 , G06F12/0638 , G06F2212/2022 , G11C7/20 , G11C11/4072 , H01L2224/48091 , H01L2224/48137 , H01L2924/00014
摘要： A memory system including ROM and RAM in which reading and writing are enabled. A memory system includes a non-volatile memory (FLASH), DRAM, a control circuit, and an information processing device. Data in FLASH is transferred to SRAM or DRAM in advance. Data transfer between the non-volatile memory and the DRAM can be performed in the background. The memory system including these plural chips is configured as a memory system module in which each chip is mutually laminated and each chip is wired via a ball grid array (BGA) and bonding wire between the chips. Data in FLASH can be read at the similar speed to that of DRAM by securing a region in which the data in FLASH can be copied in DRAM and transferring the data to DRAM in advance immediately after power is turned on or by a load instruction.
摘要翻译：包括ROM和RAM的存储器系统，其中启用读和写。存储器系统包括非易失性存储器（FLASH），DRAM，控制电路和信息处理设备。预先将FLASH中的数据传送到SRAM或DRAM。在非易失性存储器和DRAM之间的数据传输可以在后台执行。包括这些多个芯片的存储器系统被配置为存储器系统模块，其中每个芯片相互层叠，并且每个芯片经由球栅阵列（BGA）和芯片之间的接合线布线。 FLASH中的数据可以通过保护FLASH中的数据可以在DRAM中复制的区域以及在接通电源或通过加载指令之后将数据传送到DRAM中，以与DRAM类似的速度读取速度。

77. 发明申请

US20090268502A1 Semiconductor device with non-volatile memory and random access memory 有权
公开(公告)号：US20090268502A1
公开(公告)日：2009-10-29
申请号：US12454645
申请日：2009-05-21
申请人： Seiji Miura , Kazushige Ayukawa
发明人： Seiji Miura , Kazushige Ayukawa
IPC分类号： G11C5/06
CPC分类号： G06F12/0246 , G11C5/02 , G11C5/025 , G11C5/04 , G11C11/005 , G11C11/406 , G11C11/40603 , G11C11/40607 , G11C11/412 , G11C16/10 , G11C16/26 , G11C16/32 , G11C29/70
摘要： A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data.

78. 发明授权

US07554830B2 Semiconductor device with non-volatile memory and random access memory 有权
公开(公告)号：US07554830B2
公开(公告)日：2009-06-30
申请号：US11797882
申请日：2007-05-08
申请人： Seiji Miura , Kazushige Ayukawa
发明人： Seiji Miura , Kazushige Ayukawa
IPC分类号： G11C5/06
CPC分类号： G06F12/0246 , G11C5/02 , G11C5/025 , G11C5/04 , G11C11/005 , G11C11/406 , G11C11/40603 , G11C11/40607 , G11C11/412 , G11C16/10 , G11C16/26 , G11C16/32 , G11C29/70
摘要： A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data.

79. 发明授权

US07215096B2 Battery pack with charge control function 有权
标题翻译：带充电控制功能的电池组
公开(公告)号：US07215096B2
公开(公告)日：2007-05-08
申请号：US10789490
申请日：2004-02-26
申请人： Seiji Miura , Yukihiro Terada , Akira Ikeuchi
发明人： Seiji Miura , Yukihiro Terada , Akira Ikeuchi
IPC分类号： H01M10/46
CPC分类号： H02J7/0031 , H02J2007/0037 , H02J2007/004
摘要： A battery pack with a charge control function includes a charge protection circuit and a charge control circuit. The charge control circuit turns a discharge control switch on or off to control a discharge current which flows from a secondary battery to a load and also turns a charge control switch on or off to control a charge current which flows from a charger to the secondary battery. When an abnormal voltage is input, the charge control circuit turns the charge control switch on or off to stop the charging of the secondary battery through the charger.
摘要翻译：具有充电控制功能的电池组包括充电保护电路和充电控制电路。充电控制电路使放电控制开关接通或关断，以控制从二次电池流向负载的放电电流，并且还接通或关闭充电控制开关，以控制从充电器流向二次电池的充电电流。当输入异常电压时，充电控制电路打开或关闭充电控制开关，以通过充电器停止对二次电池的充电。

80. 发明申请

US20060271755A1 Memory module, cache system and address conversion method 失效
标题翻译：内存模块，缓存系统和地址转换方法
公开(公告)号：US20060271755A1
公开(公告)日：2006-11-30
申请号：US11435712
申请日：2006-05-18
申请人： Seiji Miura
发明人： Seiji Miura
IPC分类号： G06F13/28 , G06F12/00 , G08C25/00
CPC分类号： G06F12/0246 , G06F11/1068 , G06F12/0862 , G06F12/0888 , G06F12/0893 , G06F2212/2022 , G11C5/02 , G11C7/1006 , G11C2207/2245 , H01L2224/16225 , H01L2224/32145 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48227 , H01L2224/49175 , H01L2224/73253 , H01L2224/73265 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： A memory system including a non-volatile memory, a cache memory, a control circuit, and a data processing device is configured. The high speed can be achieved by transferring data in the non-volatile memory to the cache memory to retain the same therein. When the data in the non-volatile memory is transferred to the cache memory, error correction is performed so as to improve the reliability. Since the cache memory and the non-volatile memory can be accessed from the data processing device independently, improvement in usability can be achieved. The memory system including the plurality of chips is configured as a memory system module where respective chips are arranged in a stacked manner and wired by a ball grid array (BGA) and wire bonding between chips.
摘要翻译：配置包括非易失性存储器，高速缓冲存储器，控制电路和数据处理装置的存储器系统。可以通过将非易失性存储器中的数据传送到高速缓冲存储器来保持高速度来实现高速度。当非易失性存储器中的数据被传送到高速缓冲存储器时，执行错误校正以提高可靠性。由于可以独立于数据处理装置访问高速缓冲存储器和非易失性存储器，所以可以实现可用性的提高。包括多个芯片的存储器系统被配置为存储器系统模块，其中各个芯片以堆叠的方式布置并且由球栅阵列（BGA）布线并且在芯片之间引线接合。

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