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71. 发明申请

US20120265929A1 INTEGRATED CIRCUITS TO CONTROL ACCESS TO MULTIPLE LAYERS OF MEMORY IN A SOLID STATE DRIVE 审中-公开
标题翻译：集成电路控制在固态驱动器中访问多个存储器层
公开(公告)号：US20120265929A1
公开(公告)日：2012-10-18
申请号：US13530598
申请日：2012-06-22
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G06F12/02
CPC分类号： G11C7/24 , G11C5/02 , G11C16/22
摘要： Circuits to control access to memory; for example, third dimension memory are disclosed. An integrated circuit (IC) may be configured to control access to memory cells. For example, the IC may include a memory having memory cells that are vertically disposed in multiple layers of memory. The IC may include a memory access circuit configured to control access to a first subset of the memory cells in response to access control data in a second subset of the memory cells. Each memory cell may include a non-volatile two-terminal memory element that stores data as a plurality of conductivity profiles that can be non-destructively sensed by applying a read voltage across the two terminals of the memory element. New data can be written by applying a write voltage across the two terminals of the memory element. The two-terminal memory elements can be arranged in a two-terminal cross-point array configuration.
摘要翻译：控制存储器访问的电路; 例如，公开了第三维存储器。集成电路（IC）可以被配置为控制对存储器单元的访问。例如，IC可以包括具有垂直设置在多层存储器中的存储单元的存储器。 IC可以包括存储器访问电路，其被配置为响应于存储器单元的第二子集中的访问控制数据来控制对存储器单元的第一子集的访问。每个存储器单元可以包括非易失性两端存储元件，其通过在存储元件的两个端子上施加读取电压而将数据存储为可以非破坏性地感测的多个导电率分布。可以通过在存储元件的两个端子上施加写入电压来写入新的数据。两端存储器元件可以布置成两端交叉点阵列配置。

72. 发明授权

US08289803B2 System including vertically stacked embedded non-flash re-writable non-volatile memory 有权
标题翻译：系统包括垂直堆叠的非闪存可重写非易失性存储器
公开(公告)号：US08289803B2
公开(公告)日：2012-10-16
申请号：US13303012
申请日：2011-11-22
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G11C8/00
CPC分类号： G11C5/04 , G06F12/0638 , G06F2212/7208 , G11C5/02 , G11C11/005 , Y02D10/13
摘要： A multiple-type memory is disclosed. The multiple-type memory includes memory blocks in communication with control logic blocks. The memory blocks and the control logic blocks are configured to emulate a plurality of memory types. The memory blocks can be configured into a plurality of memory planes that are vertically stacked upon one another. The vertically stacked memory planes may be used to increase data storage density and/or the number of memory types that can be emulated by the multiple-type memory. Each memory plane can emulate one or more memory types. The control logic blocks can be formed in a substrate (e.g., a silicon substrate including CMOS circuitry) and the memory blocks or the plurality of memory planes can be positioned over the substrate and in communication with the control logic blocks. The multiple-type memory may be non-volatile so that stored data is retained in the absence of power.
摘要翻译：公开了一种多式存储器。多类型存储器包括与控制逻辑块通信的存储器块。存储器块和控制逻辑块被配置为模拟多个存储器类型。存储器块可以被配置成彼此垂直堆叠的多个存储器平面。可以使用垂直堆叠的存储器平面来增加数据存储密度和/或可由多型存储器仿真的存储器类型的数量。每个存储器平面可以模拟一个或多个存储器类型。控制逻辑块可以形成在衬底（例如，包括CMOS电路的硅衬底）中，并且存储器块或多个存储器平面可以位于衬底上并与控制逻辑块通信。多类型存储器可以是非易失性的，使得存储的数据在没有电力的情况下被保留。

73. 发明授权

US08271855B2 Memory scrubbing in third dimension memory 有权
标题翻译：第三维存储器中的内存擦除
公开(公告)号：US08271855B2
公开(公告)日：2012-09-18
申请号：US12653896
申请日：2009-12-18
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G11C29/00
CPC分类号： G11C13/0064 , G11C11/56 , G11C13/004 , G11C13/0069 , G11C29/00 , G11C2013/0054 , G11C2211/5634 , G11C2211/5645 , G11C2213/71
摘要： A method for memory scrubbing is provided. In this method, a first resistance of a reference memory element is read. A second resistance of a memory element also is read. A difference between the first resistance and the second resistance is sensed and a programming error associated with the second resistance is detected based on the difference. Each memory element is non-volatile and re-writeable, and can be positioned in a two-terminal memory cell that is one of a plurality of memory cells positioned in a two-terminal cross-point memory array. Active circuitry for performing the memory scrubbing can be fabricated FEOL in a logic layer and one or more layers of the two-terminal cross-point memory arrays can be fabricated BEOL over the logic layer. Each memory cell can optionally include non-ohmic device (NOD) electrically in series with the memory element and the two terminals of the memory cell.
摘要翻译：提供了一种用于记忆擦洗的方法。在该方法中，读取参考存储元件的第一电阻。还读取存储元件的第二电阻。感测到第一电阻和第二电阻之间的差异，并且基于该差异检测与第二电阻相关联的编程误差。每个存储器元件是非易失性的和可重写的，并且可以被定位在位于两端交叉点存储器阵列中的多个存储单元之一的两端存储单元中。可以在逻辑层中制造用于执行存储器擦除的有源电路，并且可以在逻辑层上制造两端的交叉点存储器阵列的一层或多层BEOL。每个存储器单元可以可选地包括与存储器单元和存储单元的两个端子串联的非欧姆器件（NOD）。

74. 发明授权

US08208297B2 Integrated circuits to control access to multiple layers of memory in a solid state drive 失效
标题翻译：用于控制在固态驱动器中访问多层存储器的集成电路
公开(公告)号：US08208297B2
公开(公告)日：2012-06-26
申请号：US13134701
申请日：2011-06-14
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G11C11/34
CPC分类号： G11C7/24 , G11C5/02 , G11C16/22
摘要： Circuits to control access to memory; for example, third dimension memory are disclosed. An integrated circuit (IC) may be configured to control access to memory cells. For example, the IC may include a memory having memory cells that are vertically disposed in multiple layers of memory. The IC may include a memory access circuit configured to control access to a first subset of the memory cells in response to access control data in a second subset of the memory cells. Each memory cell may include a non-volatile two-terminal memory element that stores data as a plurality of conductivity profiles that can be non-destructively sensed by applying a read voltage across the two terminals of the memory element. New data can be written by applying a write voltage across the two terminals of the memory element. The two-terminal memory elements can be arranged in a two-terminal cross-point array configuration.
摘要翻译：控制存储器访问的电路; 例如，公开了第三维存储器。集成电路（IC）可以被配置为控制对存储器单元的访问。例如，IC可以包括具有垂直设置在多层存储器中的存储单元的存储器。 IC可以包括存储器访问电路，其被配置为响应于存储器单元的第二子集中的访问控制数据来控制对存储器单元的第一子集的访问。每个存储器单元可以包括非易失性两端存储元件，其通过在存储元件的两个端子上施加读取电压而将数据存储为可以非破坏性地感测的多个导电率分布。可以通过在存储元件的两个端子上施加写入电压来写入新的数据。两端存储器元件可以布置成两端交叉点阵列配置。

75. 发明授权

US08141021B2 Combined memories in integrated circuits 有权
标题翻译：集成电路中的组合存储器
公开(公告)号：US08141021B2
公开(公告)日：2012-03-20
申请号：US13224173
申请日：2011-09-01
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G06F17/50
CPC分类号： H01L45/08 , G06F17/5045 , G11C11/5685 , G11C13/0007 , G11C13/0009 , G11C13/004 , G11C13/0069 , G11C2013/0045 , G11C2013/005 , G11C2013/009 , G11C2213/11 , G11C2213/31 , G11C2213/32 , G11C2213/53 , G11C2213/54 , G11C2213/56 , G11C2213/71 , G11C2213/79 , H01L27/2436 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/1246 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1625
摘要： Combined memories in integrated circuits are described, including determining a first requirement for logic blocks, determining a second requirement for memory blocks including a vertical configuration for the memory blocks, and compiling a design for the integrated circuit using the first requirement and the second requirement. The memory blocks may include non-volatile two-terminal cross-point memory arrays. The non-volatile two-terminal cross-point memory arrays can be formed on top of a logic plane. The logic plane can be fabricated in a substrate. The non-volatile two-terminal cross-point memory arrays may be vertically stacked upon one another to form a plurality of memory planes. The memory planes can be portioned into sub-planes. One or more different memory types such as Flash, SRAM, DRAM, and ROM can be emulated by the plurality of memory planes and/or sub-planes. The non-volatile two-terminal cross-point memory arrays can include a plurality of two-terminal memory elements.
摘要翻译：描述了集成电路中的组合存储器，包括确定对逻辑块的第一要求，确定包括用于存储器块的垂直配置的存储器块的第二要求，以及使用第一要求和第二要求编译集成电路的设计。存储器块可以包括非易失性两端交叉点存储器阵列。非易失性双端子交叉点存储器阵列可以形成在逻辑平面的顶部。逻辑平面可以在衬底中制造。非易失性双端子交叉点存储器阵列可以彼此垂直地堆叠以形成多个存储器平面。存储器平面可以分成子平面。可以通过多个存储器平面和/或子平面来仿真一个或多个不同的存储器类型，例如闪存，SRAM，DRAM和ROM。非易失性两端交叉点存储器阵列可以包括多个两端存储元件。

76. 发明授权

US08000138B2 Scaleable memory systems using third dimension memory 失效
标题翻译：使用第三维存储器的可扩展内存系统
公开(公告)号：US08000138B2
公开(公告)日：2011-08-16
申请号：US12454739
申请日：2009-05-22
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G11C11/34 , G06F12/02
CPC分类号： G11C16/04 , G11C2207/104
摘要： A non-volatile scalable memory circuit is described, including a bus formed on a substrate that includes active circuitry, metallization layers, and a plurality of high density third dimension memory arrays formed over the substrate. Each memory circuit can include an embedded controller for controlling data access to the memory arrays and optionally a control node that allows data access to be controlled by an external memory controller or by the embedded controller. The memory circuits can be chained together to increase memory capacity. The memory arrays can be two-terminal cross-point arrays that may be stacked upon one another.
摘要翻译：描述了非易失性可伸缩存储器电路，包括形成在衬底上的总线，其包括有源电路，金属化层以及形成在衬底上的多个高密度第三维存储器阵列。每个存储器电路可以包括用于控制对存储器阵列的数据访问的嵌入式控制器和可选地允许由外部存储器控制器或嵌入式控制器控制数据访问的控制节点。存储器电路可以链接在一起以增加存储器容量。存储器阵列可以是彼此堆叠的两端交叉点阵列。

77. 发明授权

US07999571B2 State machines using non-volatile re-writeable two-terminal resistivity-sensitive memories 失效
公开(公告)号：US07999571B2
公开(公告)日：2011-08-16
申请号：US12927546
申请日：2010-11-15
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： H03K19/173
CPC分类号： G05B19/045 , G05B2219/23289 , G11C13/00
摘要： State machines using resistivity-sensitive memory elements are disclosed. The state machine includes a next state logic comprising a non-volatile memory including a resistivity-sensitive memory element and receiving an input, a state storage device connected to the next state logic including a connection to provide a state of the state machine to the next state logic, and an output connect to the state register to output the state of the state machine. The resistivity-sensitive memory elements may be two-terminal resistivity-sensitive memory elements. The two-terminal resistivity-sensitive memory elements may store data as a plurality of conductivity profiles that can be non-destructively read by applying a read voltage across the terminals of the memory elements, and new data can be written by applying a write voltage across the terminals. The two-terminal resistivity-sensitive memory elements retain stored data in the absence of power and may be configured into a two-terminal cross-point memory array.

78. 发明授权

US07996600B2 Memory emulation in an electronic organizer 有权
标题翻译：内存模拟在电子组织者
公开(公告)号：US07996600B2
公开(公告)日：2011-08-09
申请号：US11897909
申请日：2007-08-30
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G06F12/00
CPC分类号： H04N1/2166 , G11C13/00 , G11C13/0007 , G11C2213/31 , G11C2213/71 , G11C2213/77
摘要： An electronic organizer using a memory array that is directly addressed and non-volatile is disclosed. The memory array can be used to replace and emulate multiple memory types such as DRAM, SRAM, non-volatile RAM, FLASH memory, and a non-volatile memory card, for example. The memory array may be randomly accessed. Data stored in the memory array is retained in the absence of electrical power. One or more memory arrays may be used in the electronic organizer. At least one of the memory arrays may be in the form of a removable memory card.
摘要翻译：公开了一种使用直接寻址和非易失性的存储器阵列的电子组织器。存储器阵列可以用于替换和仿真多种存储器类型，例如DRAM，SRAM，非易失性RAM，FLASH存储器和非易失性存储卡。可以随机访问存储器阵列。存储在存储器阵列中的数据在没有电力的情况下被保留。电子管理器中可以使用一个或多个存储器阵列。存储器阵列中的至少一个可以是可移动存储卡的形式。

79. 发明授权

US07961510B2 Integrated circuits to control access to multiple layers of memory in a solid state drive 失效
公开(公告)号：US07961510B2
公开(公告)日：2011-06-14
申请号：US12315361
申请日：2008-12-02
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G11C11/34
CPC分类号： G11C7/24 , G11C5/02 , G11C16/22
摘要： Circuits to control access to memory; for example, third dimension memory are disclosed. An integrated circuit (IC) may be configured to control access to memory cells. For example, the IC may include a memory having memory cells that are vertically disposed in multiple layers of memory. The IC may include a memory access circuit configured to control access to a first subset of the memory cells in response to access control data in a second subset of the memory cells. Each memory cell may include a non-volatile two-terminal memory element that stores data as a plurality of conductivity profiles that can be non-destructively sensed by applying a read voltage across the two terminals of the memory element. New data can be written by applying a write voltage across the two terminals of the memory element. The two-terminal memory elements can be arranged in a two-terminal cross-point array configuration.

80. 发明申请

US20110134715A1 Method for accessing vertically stacked embedded non-flash re-writable non-volatile memory 有权
公开(公告)号：US20110134715A1
公开(公告)日：2011-06-09
申请号：US12931972
申请日：2011-02-15
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G11C8/10 , G11C8/00
CPC分类号： G11C5/04 , G06F12/0638 , G06F2212/7208 , G11C5/02 , G11C11/005 , Y02D10/13
摘要： A multiple-type memory is disclosed. The multiple-type memory includes memory blocks in communication with control logic blocks. The memory blocks and the control logic blocks are configured to emulate a plurality of memory types. The memory blocks can be configured into a plurality of memory planes that are vertically stacked upon one another. The vertically stacked memory planes may be used to increase data storage density and/or the number of memory types that can be emulated by the multiple-type memory. Each memory plane can emulate one or more memory types. The control logic blocks can be formed in a substrate (e.g., a silicon substrate including CMOS circuitry) and the memory blocks or the plurality of memory planes can be positioned over the substrate and in communication with the control logic blocks. The multiple-type memory may be non-volatile so that stored data is retained in the absence of power.

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