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71. 发明授权

US6094719A Reducing data dependent conflicts by converting single precision instructions into microinstructions using renamed phantom registers in a processor having double precision registers 失效
标题翻译：在具有双精度寄存器的处理器中使用重命名幻像寄存器将单精度指令转换为微指令来减少数据相关的冲突
公开(公告)号：US6094719A
公开(公告)日：2000-07-25
申请号：US881958
申请日：1997-06-25
申请人： Ramesh Panwar
发明人： Ramesh Panwar
IPC分类号： G06F9/30 , G06F9/302 , G06F9/318 , G06F9/38
CPC分类号： G06F9/30014 , G06F9/30112 , G06F9/3013 , G06F9/3017 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3857
摘要： In an out-of-order processor having single-precision floating-point registers aliased into double-precision floating-point registers, a single-precision floating-point arithmetic operation having four possible register dependencies is converted into two microinstructions which are processed normally within the processor. The first microinstruction is coded to perform the arithmetic operation specified by the single-precision instruction using the first and second source registers specified and storing the result in a phantom register. The second microinstruction is coded for merging the contents of the phantom register and the destination register specified. Each microinstruction has at most two possible register dependencies, thereby reducing the total number of register dependencies which the processor is required to track.
摘要翻译：在具有混合到双精度浮点寄存器中的单精度浮点寄存器的无序处理器中，具有四个可能的寄存器依赖性的单精度浮点算术运算被转换成两个微指令，它们在处理器。第一个微指令被编码为使用指定的第一个和第二个源寄存器执行由单精度指令指定的算术运算，并将结果存储在幻像寄存器中。第二个微指令被编码用于合并幻象寄存器的内容和指定的目标寄存器。每个微指令至多有两个可能的寄存器依赖关系，从而减少了处理器需要跟踪的寄存器依赖关系的总数。

72. 发明授权

US6058466A System for allocation of execution resources amongst multiple executing processes 失效
标题翻译：用于在多个执行过程之间分配执行资源的系统
公开(公告)号：US6058466A
公开(公告)日：2000-05-02
申请号：US881732
申请日：1997-06-24
申请人： Ramesh Panwar , Joseph I. Chamdani
发明人： Ramesh Panwar , Joseph I. Chamdani
IPC分类号： G06F9/38 , G06F9/00
CPC分类号： G06F9/3806 , G06F9/3802 , G06F9/3844 , G06F9/3851 , G06F9/3863
摘要： A system of executing coded instructions in a dynamically configurable multiprocessor having shared execution resources including steps of placing a first processor in an active state upon booting of the multiprocessor. In response to a processor create command, a second processor is placed in an active state. When either the first or second processor encounter a cache miss that has to be serviced by off-chip cache the processor requiring service is placed in nap state in which instruction fetching for that processor is disabled. When either the first or second processor encounter a cache miss that has to be serviced by main memory, the processor requiring services is placed in a sleep state by flushing all instructions from the processor in the sleep state and disabling instruction fetching for the processor in the sleep state.
摘要翻译：在具有共享执行资源的动态可配置多处理器中执行编码指令的系统，包括在引导多处理器时将第一处理器置于活动状态的步骤。响应于处理器创建命令，第二处理器被置于活动状态。当第一或第二处理器遇到必须由片外高速缓存服务的高速缓存未命中时，处理器需要服务处于休眠状态，在该状态下禁止该处理器的指令取出。当第一或第二处理器遇到必须由主存储器服务的高速缓存未命中时，需要服务的处理器通过在睡眠状态下从处理器中冲洗所有指令而置于休眠状态，并且禁用在处理器中的指令获取睡眠状态

73. 发明授权

US6035374A Method of executing coded instructions in a multiprocessor having shared execution resources including active, nap, and sleep states in accordance with cache miss latency 失效
标题翻译：根据高速缓存未命中延迟，在具有包括活动，睡眠和睡眠状态的共享执行资源的多处理器中执行编码指令的方法
公开(公告)号：US6035374A
公开(公告)日：2000-03-07
申请号：US881239
申请日：1997-06-25
申请人： Ramesh Panwar , Joseph I. Chamdani
发明人： Ramesh Panwar , Joseph I. Chamdani
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3885 , G06F9/3806 , G06F9/382 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3861
摘要： A method of executing coded instructions in a dynamically configurable multiprocessor having shared execution resources including steps of placing a first processor in an active state upon booting of the multiprocessor. In response to a processor create command, a second processor is placed in an active state. When either the first or second processor encounter a cache miss that has to be serviced by off-chip cache the processor requiring service is placed in nap state in which instruction fetching for that processor is disabled. When either the first or second processor encounter a cache miss that has to be serviced by main memory, the processor requiring services I placed in a sleep state by flushing all instructions from the processor in the sleep state and disabling instruction fetching for the processor in the sleep state.
摘要翻译：一种在具有共享执行资源的动态可配置多处理器中执行编码指令的方法，包括在所述多处理器引导时将第一处理器置于活动状态的步骤。响应于处理器创建命令，第二处理器被置于活动状态。当第一或第二处理器遇到必须由片外高速缓存服务的高速缓存未命中时，处理器需要服务处于休眠状态，在该状态下禁止该处理器的指令取出。当第一或第二处理器遇到必须由主存储器服务的高速缓存未命中时，处理器要求服务I处于睡眠状态，通过在处于休眠状态的状态下冲洗所有指令并禁止在处理器中取出指令睡眠状态

74. 发明授权

US5898853A Apparatus for enforcing true dependencies in an out-of-order processor 失效
标题翻译：用于在乱序处理器中执行真正依赖性的装置
公开(公告)号：US5898853A
公开(公告)日：1999-04-27
申请号：US882173
申请日：1997-06-25
申请人： Ramesh Panwar , Dani Y. Dakhil
发明人： Ramesh Panwar , Dani Y. Dakhil
IPC分类号： G06F9/38
CPC分类号： G06F9/3838 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： In a processor executing instructions speculatively or out-of-order, a dependency table tracks instruction dependencies between a current instruction and a live instruction. The table contains an instruction identifier and the destination register specified by the live instruction. The table can also contain information about the age of the entry, the validity of the entry, and the process which the entry is associated. A dependency between instructions is determined by one or more comparators comparing the destination register to the source registers of the current instruction. True dependencies are distinguished from false dependencies using the age information, the validity information, and the process information.
摘要翻译：在执行指令或乱序指令的处理器中，依赖表跟踪当前指令和实时指令之间的指令依赖关系。该表包含指令标识符和由实时指令指定的目标寄存器。该表还可以包含关于条目的年龄，条目的有效性以及条目相关联的进程的信息。指令之间的相关性由一个或多个将目的地寄存器与当前指令的源寄存器进行比较的比较器确定。使用年龄信息，有效性信息和过程信息将真依赖性与假依赖关系区分开。

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