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71. 发明授权

US07802057B2 Priority aware selective cache allocation 有权
标题翻译：优先级识别选择性缓存分配
公开(公告)号：US07802057B2
公开(公告)日：2010-09-21
申请号：US11965131
申请日：2007-12-27
申请人： Ravishankar Iyer , Ramesh Milekal , Donald Newell , Li Zhao
发明人： Ravishankar Iyer , Ramesh Milekal , Donald Newell , Li Zhao
IPC分类号： G06F12/06 , G06F9/50
CPC分类号： G06F12/126 , G06F9/5016 , G06F12/0888
摘要： A method and apparatus for is herein described providing priority aware and consumption guided dynamic probabilistic allocation for a cache memory. Utilization of a sample size of a cache memory is measured for each priority level of a computer system. Allocation probabilities for each priority level are updated based on the measured consumption/utilization, i.e. allocation is reduced for priority levels consuming too much of the cache and allocation is increased for priority levels consuming too little of the cache. In response to an allocation request, it is assigned a priority level. An allocation probability associated with the priority level is compared with a randomly generated number. If the number is less than the allocation probability, then a fill to the cache is performed normally. In contrast, a spatially or temporally limited fill is performed if the random number is greater than the allocation probability.
摘要翻译：本文描述了提供高速缓冲存储器的优先级感知和消耗引导的动态概率分配的方法和装置。针对计算机系统的每个优先级测量利用高速缓冲存储器的样本大小。基于所测量的消耗/利用率来更新每个优先级的分配概率，即对于消耗太多高速缓存的优先级降低了分配，并且对于消耗太多缓存的优先级来说，分配增加。响应于分配请求，它被分配优先级。将与优先级相关联的分配概率与随机生成的数字进行比较。如果该数量小于分配概率，则正常地执行对高速缓存的填充。相比之下，如果随机数大于分配概率，则执行空间或时间有限的填充。

72. 发明授权

US07725657B2 Dynamic quality of service (QoS) for a shared cache 有权
标题翻译：共享缓存的动态服务质量（QoS）
公开(公告)号：US07725657B2
公开(公告)日：2010-05-25
申请号：US11726238
申请日：2007-03-21
申请人： William C. Hasenplaugh , Li Zhao , Ravishankar Iyer , Ramesh Illikkal , Srihari Makineni , Donald Newell , Aamer Jaleel , Simon C. Steely, Jr.
发明人： William C. Hasenplaugh , Li Zhao , Ravishankar Iyer , Ramesh Illikkal , Srihari Makineni , Donald Newell , Aamer Jaleel , Simon C. Steely, Jr.
IPC分类号： G06F12/06
CPC分类号： G06F12/084 , G06F12/0842
摘要： In one embodiment, the present invention includes a method for associating a first priority indicator with data stored in a first entry of a shared cache memory by a core to indicate a priority level of a first thread, and associating a second priority indicator with data stored in a second entry of the shared cache memory by a graphics engine to indicate a priority level of a second thread. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于将第一优先级指示符与存储在共享高速缓冲存储器的第一条目中的数据相关联以指示第一线程的优先级，并且将第二优先级指示符与存储的数据相关联的方法在图形引擎的共享高速缓冲存储器的第二条目中指示第二线程的优先级。描述和要求保护其他实施例。

73. 发明申请

US20090172315A1 PRIORITY AWARE SELECTIVE CACHE ALLOCATION 有权
标题翻译：优先注意选择性高速缓存分配
公开(公告)号：US20090172315A1
公开(公告)日：2009-07-02
申请号：US11965131
申请日：2007-12-27
申请人： Ravishankar Iyer , Ramesh Milekal , Donald Newell , Li Zhao
发明人： Ravishankar Iyer , Ramesh Milekal , Donald Newell , Li Zhao
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F9/5016 , G06F12/0888
摘要： A method and apparatus for is herein described providing priority aware and consumption guided dynamic probabilistic allocation for a cache memory. Utilization of a sample size of a cache memory is measured for each priority level of a computer system. Allocation probabilities for each priority level are updated based on the measured consumption/utilization, i.e. allocation is reduced for priority levels consuming too much of the cache and allocation is increased for priority levels consuming too little of the cache. In response to an allocation request, it is assigned a priority level. An allocation probability associated with the priority level is compared with a randomly generated number. If the number is less than the allocation probability, then a fill to the cache is performed normally. In contrast, a spatially or temporally limited fill is performed if the random number is greater than the allocation probability.
摘要翻译：本文描述了提供高速缓冲存储器的优先级感知和消耗引导的动态概率分配的方法和装置。针对计算机系统的每个优先级测量利用高速缓冲存储器的样本大小。基于所测量的消耗/利用率来更新每个优先级的分配概率，即对于消耗太多高速缓存的优先级降低了分配，并且对于消耗太多缓存的优先级来说，分配增加。响应于分配请求，它被分配优先级。将与优先级相关联的分配概率与随机生成的数字进行比较。如果该数量小于分配概率，则正常地执行对高速缓存的填充。相比之下，如果随机数大于分配概率，则执行空间或时间有限的填充。

74. 发明申请

US20090165004A1 Resource-aware application scheduling 审中-公开
标题翻译：资源感知应用程序调度
公开(公告)号：US20090165004A1
公开(公告)日：2009-06-25
申请号：US12004756
申请日：2007-12-21
申请人： Jaideep Moses , Don K. Newell , Ramesh Illikkal , Ravishankar Iyer , Srihari Makineni , Li Zhao , Scott Hahn , Tong N. Li , Padmashree Apparao
发明人： Jaideep Moses , Don K. Newell , Ramesh Illikkal , Ravishankar Iyer , Srihari Makineni , Li Zhao , Scott Hahn , Tong N. Li , Padmashree Apparao
IPC分类号： G06F9/46
CPC分类号： G06F9/505 , G06F2209/507 , G06F2209/508
摘要： In one embodiment, a method provides capturing resource monitoring information for a plurality of applications; accessing the resource monitoring information; and scheduling at least one of the plurality of applications on a selected processing core of a plurality of processing cores based, at least in part, on the resource monitoring information.
摘要翻译：在一个实施例中，一种方法提供捕获用于多个应用的资源监视信息; 访问资源监控信息; 以及至少部分地基于所述资源监视信息，在所述多个处理核心的所选择的处理核心上调度所述多个应用中的至少一个。

75. 发明授权

US07552288B2 Selectively inclusive cache architecture 有权
标题翻译：选择性包容性缓存架构
公开(公告)号：US07552288B2
公开(公告)日：2009-06-23
申请号：US11503777
申请日：2006-08-14
申请人： Ravishankar Iyer , Li Zhao , Srihari Makineni , Donald Newell
发明人： Ravishankar Iyer , Li Zhao , Srihari Makineni , Donald Newell
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0831
摘要： In one embodiment, the present invention includes a method for maintaining data in a first level cache non-inclusively with data in a second level cache coupled to the first level cache. At the same time, at least a portion of directory information associated with the data in the first level cache may be maintained inclusively with a directory portion of the second level cache. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于在与第一级高速缓存耦合的第二级高速缓存中的数据非包含地维护第一级高速缓存中的数据的方法。同时，可以与第二级高速缓存的目录部分一起保持与第一级高速缓存中的数据相关联的目录信息的至少一部分。描述和要求保护其他实施例。

76. 发明申请

US20080244221A1 EXPOSING SYSTEM TOPOLOGY TO THE EXECUTION ENVIRONMENT 审中-公开
标题翻译：对执行环境的暴露系统拓扑
公开(公告)号：US20080244221A1
公开(公告)日：2008-10-02
申请号：US11694322
申请日：2007-03-30
申请人： Donald K. Newell , Jaideep Moses , Ravishankar Iyer , Rameshkumar G. Illikkal , Srihari Makineni
发明人： Donald K. Newell , Jaideep Moses , Ravishankar Iyer , Rameshkumar G. Illikkal , Srihari Makineni
IPC分类号： G06F15/00
CPC分类号： G06F15/16
摘要： Embodiments of apparatuses, methods, and systems for exposing system topology to an execution environment are disclosed. In one embodiment, an apparatus includes execution cores and resources on a single integrated circuit, and topology logic. The topology logic is to populate a data structure with information regarding a relationship between the execution cores and the resources.
摘要翻译：公开了将系统拓扑暴露给执行环境的装置，方法和系统的实施例。在一个实施例中，装置包括在单个集成电路上的执行核心和资源以及拓扑逻辑。拓扑逻辑是使用关于执行核心和资源之间的关系的信息来填充数据结构。

77. 发明申请

US20200228880A1 ON-DEMAND GENERATION AND PERSONALIZATION OF VIDEO CONTENT 审中-公开
公开(公告)号：US20200228880A1
公开(公告)日：2020-07-16
申请号：US16833582
申请日：2020-03-28
申请人： Ravishankar Iyer , Nilesh Kumar Jain , Rameshkumar Illikkal , Carl S. Marshall , Selvakumar Panneer , Rajesh Poornachandran
发明人： Ravishankar Iyer , Nilesh Kumar Jain , Rameshkumar Illikkal , Carl S. Marshall , Selvakumar Panneer , Rajesh Poornachandran
IPC分类号： H04N21/81 , H04N21/234 , H04N21/235 , H04N21/647
摘要： Various embodiments for dynamically generating an advertisement in a video stream are disclosed. In one embodiment, video stream content associated with a video stream for a user device is received. Video analytics data is obtained for the video stream content, which indicates a scene recognized in the video stream content. An advertisement to be generated and inserted into the video stream content is then selected based on the scene recognized in the video stream content, and an advertisement template for generating the selected advertisement is obtained. Video advertisement content corresponding to the advertisement is then generated based on the advertisement template and the video analytics data. The video advertisement content is then inserted into the video stream content, and the modified video stream content is transmitted to the user device.

78. 发明授权

US09626586B2 Optimized fast hessian matrix computation architecture 有权
公开(公告)号：US09626586B2
公开(公告)日：2017-04-18
申请号：US14320092
申请日：2014-06-30
申请人： Yong Zhang , Ravishankar Iyer , Rameshkumar G. Illikkal , Donald K. Newell , Jianping Zhou
发明人： Yong Zhang , Ravishankar Iyer , Rameshkumar G. Illikkal , Donald K. Newell , Jianping Zhou
IPC分类号： G06K9/00 , G06K9/48 , G06K9/46
CPC分类号： G06K9/481 , G06K9/00973 , G06K9/4671 , G06K2009/485
摘要： Methods and systems of recognizing images may include an apparatus having a hardware module with logic to, for a plurality of vectors in an image, determine a first intermediate computation based on even pixels of an image vector, and determine a second intermediate computation based on odd pixels of an image vector. The logic can also combine the first and second intermediate computations into a Hessian matrix computation.

79. 发明授权

US08799902B2 Priority based throttling for power/performance quality of service 有权
标题翻译：基于优先级的电源/性能质量服务节制
公开(公告)号：US08799902B2
公开(公告)日：2014-08-05
申请号：US11786019
申请日：2007-04-09
申请人： Ramesh Kumar Illikkal , Ravishankar Iyer , Jaideep Moses , Don Newell , Tryggve Fossum
发明人： Ramesh Kumar Illikkal , Ravishankar Iyer , Jaideep Moses , Don Newell , Tryggve Fossum
IPC分类号： G06F9/46 , G06F1/00 , G06F1/26 , G06F1/32 , G06F15/173
CPC分类号： G06F9/5077 , G06F9/5094 , G06F2209/504 , Y02D10/22 , Y02D10/36
摘要： A method and apparatus for throttling power and/or performance of processing elements based on a priority of software entities is herein described. Priority aware power management logic receives priority levels of software entities and modifies operating points of processing elements associated with the software entities accordingly. Therefore, in a power savings mode, processing elements executing low priority applications/tasks are reduced to a lower operating point, i.e. lower voltage, lower frequency, throttled instruction issue, throttled memory accesses, and/or less access to shared resources. In addition, utilization logic potentially trackes utilization of a resource per priority level, which allows the power manager to determine operating points based on the effect of each priority level on each other from the perspective of the resources themselves. Moreover, a software entity itself may assign operating points, which the power manager enforces.
摘要翻译：这里描述了一种基于软件实体的优先级来节制处理元件的功率和/或性能的方法和装置。优先级感知功率管理逻辑接收软件实体的优先级，并相应地修改与软件实体相关联的处理元件的工作点。因此，在省电模式中，执行低优先级应用/任务的处理元件被降低到较低的工作点，即较低的电压，较低的频率，节流的指令问题，节流的存储器访问和/或较少的对共享资源的访问。此外，利用逻辑潜在地追踪每个优先级别的资源的利用率，这允许电力管理者从资源本身的角度基于每个优先级的影响来确定工作点。此外，软件实体本身可以分配功率管理器执行的操作点。

80. 发明申请

US20140215240A1 Methods And Apparatuses For Controlling Thread Contention 审中-公开
公开(公告)号：US20140215240A1
公开(公告)日：2014-07-31
申请号：US14227680
申请日：2014-03-27
申请人： Andrew Herdrich , Ramesh Illikkal , Donald Newell , Ravishankar Iyer , Vineet Chadha
发明人： Andrew Herdrich , Ramesh Illikkal , Donald Newell , Ravishankar Iyer , Vineet Chadha
IPC分类号： G06F1/32
CPC分类号： G06F9/44505 , G06F1/10 , G06F1/32 , G06F1/3203 , G06F1/3206 , G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3296 , G06F9/50 , G06F9/5094 , G06F12/0891 , Y02D10/128
摘要： An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.

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