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71. 再颁专利

USRE38059E1 Semiconductor integrated logic circuit device using a pass transistor 有权
标题翻译：半导体集成逻辑电路器件采用传输晶体管
公开(公告)号：USRE38059E1
公开(公告)日：2003-04-01
申请号：US09783597
申请日：2001-02-15
申请人： Kazuo Yano , Yasuhiko Sasaki
发明人： Kazuo Yano , Yasuhiko Sasaki
IPC分类号： G06F1750
CPC分类号： H03K19/1735 , H01L27/0207 , H01L27/11807 , H01L2924/14 , H01L2924/00
摘要： The semiconductor integrated circuit enjoys a high performance and can be produced at a low production cost and within a short time. A cell has an internal circuit connection such that an output terminal is connected to a plurality of input terminals through source-drain paths of active devices connected in the tree form, and gate electrodes of the active devices are connected to other input terminals. Two such cells having the same internal circuit connection, the same disposition of the internal circuit devices and the same disposition of the input/output terminals are disposed on the same chip, and mutually different logics can be accomplished by changing the form of application of input signals from outside the cells to the input terminals. A chip area of an integrated circuit designed by CAD using a cell library can be reduced and a high speed circuit operation can be attained. The present invention provides remarkable effect for improving performance of an ASIC, a microprocessor, etc., and for reducing the cost of production.
摘要翻译：半导体集成电路具有高性能，可以在低成本和短时间内生产。单元具有内部电路连接，使得输出端子通过以树形形式连接的有源器件的源极 - 漏极路径连接到多个输入端子，并且有源器件的栅电极连接到其它输入端子。具有相同内部电路连接的两个这样的单元，内部电路装置的相同配置和输入/输出端子的相同布置被布置在同一芯片上，并且可以通过改变输入的应用形式来实现彼此不同的逻辑从单元外部到输入端子的信号。可以减少由CAD使用单元库设计的集成电路的芯片面积，并且可以实现高速电路操作。本发明对于提高ASIC，微处理器等的性能以及降低生产成本提供显着的效果。

72. 发明授权

US06505322B2 Logic circuit design method and cell library for use therewith 失效
公开(公告)号：US06505322B2
公开(公告)日：2003-01-07
申请号：US09904661
申请日：2001-07-16
申请人： Shunzo Yamashita , Kazuo Yano , Naoki Kato
发明人： Shunzo Yamashita , Kazuo Yano , Naoki Kato
IPC分类号： G06F1750
CPC分类号： G06F17/505
摘要： A method, system, and library for generating high-speed logic circuits with reduced path depths even in cases when a critical path diverges into a plurality of paths that eventually converge. By replacing the gates of a logic circuit by selectors with two inputs and one output, a selector-based circuit is generated where a local circuit between the path divergence node and convergence node is detected. The stages of the critical path are reduced by replacing the local circuit by a logically equivalent selector with two inputs and one output; wherein one input of the selector is controlled by a circuit formed by inputting a logical value of “0” to the divergence node from which the local circuit is developed and a second input of the selector is controlled by a circuit formed by inputting a logical value of “1” to the divergence node.

73. 发明授权

US06496952B1 Semiconductor integrated circuit device, method of manufacturing the device, and computer readable medium 有权
标题翻译：半导体集成电路器件，该器件的制造方法以及计算机可读介质
公开(公告)号：US06496952B1
公开(公告)日：2002-12-17
申请号：US09399330
申请日：1999-09-20
申请人： Kenichi Osada , Koichiro Ishibashi , Kazuo Yano , Tetsuro Honmura
发明人： Kenichi Osada , Koichiro Ishibashi , Kazuo Yano , Tetsuro Honmura
IPC分类号： G01R3128
CPC分类号： G11C29/028 , G11C15/00 , G11C29/50 , G11C29/50012 , G11C2029/0403
摘要： A semiconductor integrated circuit device, a method of manufacturing the device, and a medium for storing a processing procedure for deciding the number of delay circuits built in the device used for designing are disclosed. More particularly, a semiconductor integrated circuit device which guarantees the characteristics of writing into and reading from the built-in memory even when the manufacturing process conditions are varied is obtained. The semiconductor integrated circuit device is provided with a cache memory which includes a BIST circuit composed of a pattern generator, a pattern comparator, and an output register; a register controlled by a register control signal and a register write signal; a variable delay circuit controlled by the register; word lines, and a sense amplifier enable signal line. The timing for enabling the sense amplifier is changed and the memory is measured by the BIST, thereby deciding the optimal timing.
摘要翻译：公开了一种半导体集成电路器件，该器件的制造方法以及用于存储用于确定用于设计的器件中构建的延迟电路的数量的处理过程的介质。更具体地说，即使在制造工艺条件变化的情况下，也能够确保写入和读出内置存储器的特性的半导体集成电路器件。半导体集成电路装置具有高速缓冲存储器，其包括由图案发生器，图案比较器和输出寄存器构成的BIST电路; 由寄存器控制信号和寄存器写入信号控制的寄存器; 由寄存器控制的可变延迟电路; 字线和读出放大器使能信号线。改变启用读出放大器的定时，并通过BIST测量存储器，从而确定最佳定时。

74. 发明授权

US06313665B1 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US06313665B1
公开(公告)日：2001-11-06
申请号：US09402648
申请日：2000-02-03
申请人： Yasuhiko Sasaki , Kunihito Rikino , Kazuo Yano , Shunzo Yamashita
发明人： Yasuhiko Sasaki , Kunihito Rikino , Kazuo Yano , Shunzo Yamashita
IPC分类号： H01L2710
CPC分类号： H03K19/1737 , H01L27/0207 , H01L27/11898
摘要： The I/O terminal positions of a pass transistor logic circuit cell are distributed in the cell, an output amplifier is provided on the end part of the cell, the pass transistor circuit is arranged in the direction in which a potential supply line extends, a signal polarity inverting circuit is laid out in the cell and the arrangement of wells is different from the arrangement of a conventional CMOS logic circuit.
摘要翻译：传输晶体管逻辑电路单元的I / O端子位置分布在单元中，输出放大器设置在单元的端部，传输晶体管电路沿电位线延伸的方向排列，信号极性反转电路布置在单元中，并且阱的布置不同于传统CMOS逻辑电路的布置。

75. 外观设计

USD423434S Automobile instrument panel 失效
公开(公告)号：USD423434S
公开(公告)日：2000-04-25
申请号：US100580
申请日：1999-02-12
申请人： Kazuo Yano , Daniel Jerome Sims
设计人： Kazuo Yano , Daniel Jerome Sims

76. 发明授权

US6049232A Semiconductor integrated circuit 有权
公开(公告)号：US6049232A
公开(公告)日：2000-04-11
申请号：US225291
申请日：1999-01-05
申请人： Yasuhiko Sasaki , Kazuo Yano , Shunzo Yamashita , Koichi Seki
发明人： Yasuhiko Sasaki , Kazuo Yano , Shunzo Yamashita , Koichi Seki
IPC分类号： G06F17/50 , H03K19/173 , H03K19/0948
CPC分类号： H03K19/1736 , G06F17/505 , H03K19/1737
摘要： For the relation between the first and second pass-transistor circuits (PT1, PT2), the output signal of the preceding-stage is supplied to the gate of the succeeding-stage, and for the relation between the second and third pass-transistor circuits (PT2, PT3), the output signal of the preceding-stage is supplied to the source-drain path of the succeeding-stage. The first pass-transistor circuit (PT1) receives on its first input node (In1) and second input node (In2) the first input signal and the second input signal that are logically independent from each other. This logic circuit requires a smaller number of transistors and is capable of reducing the power consumption and delay and accomplishing an intricate logic function.

77. 发明授权

US5712792A Logic circuit sythesizing method utilizing binary decision diagram explored based upon hierarchy of correlation between input variables 失效
标题翻译：基于输入变量之间相关性层次的二元决策图的逻辑电路协调方法
公开(公告)号：US5712792A
公开(公告)日：1998-01-27
申请号：US633486
申请日：1996-04-17
申请人： Shunzo Yamashita , Kazuo Yano , Yasuhiko Sasaki , Koichi Seki
发明人： Shunzo Yamashita , Kazuo Yano , Yasuhiko Sasaki , Koichi Seki
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： In order to effectively explore a binary decision diagram for synthesizing a logic circuit, a tentative circuit comprised of AND gates and OR gates is synthesized from a logic function. The number of gates in this circuit to which two input variables are simultaneously associated are counted and used as correlation between the two input variables. A correlation matrix for correlation among all of the input variables is generated. The input variables are sequentially grouped from a set of input variables with strongest correlation in the correlation matrix: These groups are registered into a correlation tree, and an intergroup correlation tree is produced. These groups are sequentially selected from a group with the least correlation, and the intragroup order of the selected group is changed from one to another. A binary decision diagram is explored which satisfies the most appropriate condition in that group (such as the minimum number of nodes, the minimum delay, and the minimum area). The above processes repeated for all groups. Each node of the binary decision diagram thus obtained is substituted by a selector and each selector circuit is substituted by a circuit of a transistor level.
摘要翻译：为了有效地研究用于合成逻辑电路的二进制判定图，从逻辑功能合成了由与门和或门组成的暂定电路。两个输入变量同时关联的该电路中的门数被计数并用作两个输入变量之间的相关。生成所有输入变量之间相关的相关矩阵。输入变量从相关矩阵中具有最强相关性的一组输入变量顺序分组：将这些组注册到相关树中，并产生一个组间相关树。从具有最小相关性的组中顺序地选择这些组，并且所选择的组的组内顺序从一个改变为另一组。探讨了满足该组中最合适条件（如最小节点数，最小延迟和最小面积）的二进制决策图。上述过程对所有组重复。由此获得的二进制判定图的每个节点由选择器代替，并且每个选择器电路被晶体管电平的电路代替。

78. 发明授权

US5363770A Drive unit for transport trolley having plastic center link and drive dog covering for noise reduction 失效
标题翻译：用于运输手推车的驱动单元，具有塑料中心链接和用于降噪的驱动狗盖
公开(公告)号：US5363770A
公开(公告)日：1994-11-15
申请号：US63893
申请日：1993-05-17
申请人： Katsuyoshi Makimura , Kazuo Yano
发明人： Katsuyoshi Makimura , Kazuo Yano
IPC分类号： B61B10/00 , B61B10/02 , B65G17/20 , B65G17/38 , B65G35/06 , B61B12/00
CPC分类号： B61B10/025
摘要： The present invention intends to prevent generation of metallic noise when both longitudinal sides of the chain supporting trolley (22) installed to the center link (19) of the chain collide against the ends of the adjoining side links (20a, 20b, 25) when the driving chains (18) which comprise linkchains in which a center link (19) whose plane shape is an elongated ring and a pair of top and bottom side links (20a, 20b, 25) are linked alternately become loose. The present invention comprises a rib (32) installed to the center link (19) at the longitudinal center, vertically notched grooves (27c, 28c, 33), in which the rib (32) of the center link is fitted, provided to the vertical portion (27a, 28a) penetrating the center link (19) of a pair of left and right trolley units (27, 28) composing the chain supporting trolley (22) and to a plate type spacer (29) which intervenes between both vertical portions (27a, 28a) and is made of plastics, and a portion of both front and rear sides of the said plate shape spacer (29), which at least adjoins the ends of the side links (20a, 20b, 25), protruded longitudinally outward from the vertical portion (27a, 28a) of each trolley unit.
摘要翻译：本发明旨在防止在安装在链条的中心连杆（19）上的链条支撑台车（22）的两个纵向侧面相邻于相邻的侧连杆（20a，20b，25）的端部的情况下产生金属噪音，其中包括其平面形状为细长环的中心连杆（19）和一对顶侧和底侧连杆（20a，20b，25）交替连接的链节的驱动链（18）变得松动。本发明包括在纵向中心处安装到中心连杆（19）的肋（32），其中装配有中心连杆的肋（32）的垂直切口槽（27c，28c，33）穿过构成链条支撑台车（22）的一对左右手推车单元（27,28）的中心连杆（19）的垂直部分（27a，28a）和介于两个垂直方向部分（27a，28a）并且由塑料制成，并且所述板形间隔件（29）的前侧和后侧的至少邻近侧连杆（20a，20b，25）的端部的一部分突出从每个台车单元的垂直部分（27a，28a）纵向向外延伸。

79. 发明授权

US5284367A Flexible pipe joint 失效
标题翻译：柔性管接头
公开(公告)号：US5284367A
公开(公告)日：1994-02-08
申请号：US914919
申请日：1992-07-17
申请人： Kazuo Yano
发明人： Kazuo Yano
IPC分类号： F16L37/23 , F16L27/04 , F16L27/113
CPC分类号： F16L27/113 , F16L27/04
摘要： A flexible pipe joint capable of joining connecting portions of connected objects such as pipes to each other while permitting the direction of joining between both to be varied as desired. First and second joint members (11,31) are formed with spherical inner surfaces (13,37) which slidably contact spherical outer surfaces (54,56) on an interpolating member (51) located between the joint members. Thus, the interpolating member (51) is rockable relative to the joint members (11,31) about the centre of each of the spherical outer surfaces (54,56). Press rings (16,40) are arranged to keep both spherical outer (54,56) and inner (13,37) surfaces in contact with each other through bearing balls (23,47).
摘要翻译：一种柔性管接合件，其能够将诸如管道的连接物体的连接部分彼此连接，同时允许两者之间的接合方向根据需要变化。第一和第二关节构件（11,31）形成有球形内表面（13,37），其可滑动地接触位于联合构件之间的内插构件（51）上的球形外表面（54,56）。因此，内插构件51围绕每个球形外表面54,56的中心相对于接合构件11,31摆动。压环（16,40）布置成通过轴承球（23,47）保持球形外壳（54,56）和内（13,37）两个表面彼此接触。

80. 发明授权

US4949145A Homo-junction bipolar transistor having high base concentration and suitable for low temperature operation 失效
标题翻译：具有高碱浓度并适用于低温操作的同相双极晶体管
公开(公告)号：US4949145A
公开(公告)日：1990-08-14
申请号：US253228
申请日：1988-10-04
申请人： Kazuo Yano , Masaaki Aoki , Toshiaki Masuhara , Katsuhiro Shimohigashi
发明人： Kazuo Yano , Masaaki Aoki , Toshiaki Masuhara , Katsuhiro Shimohigashi
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8249 , H01L27/06 , H01L29/36 , H01L29/66 , H01L29/732
CPC分类号： H01L29/66992 , H01L27/0623 , H01L29/36
摘要： In a homo-junction bipolar transistor suitable for a low temperature operation below 200.degree.K. (particularly below 77 K), the maximum value of the impurity concentration of an intrinsic base region is set to be at least 1.times.10.sup.18 /cm.sup.3. The impurity concentration of an emitter region is set to a value lower than this maximum value. Thus, a base resistance can be reduced and high speed operation becomes possible. Furthermore, bandgap narrowing develops in the intrinsic base region and a common-emitter current gain in the low temperature operation can be kept at a sufficient value. When this homo-junction bipolar transistor is formed together with complementary insulated gate field effect transistors on the surface of a semiconductor substrate, there can be obtained a Bi-CMOS device capable of a high speed operation even in the low temperature operation.
摘要翻译：在适用于低于200°K（特别是低于77K）的低温操作的同相双极晶体管中，本征基区的杂质浓度的最大值设定为至少1×1018 / cm3。发射极区域的杂质浓度设定为比该最大值低的值。因此，可以降低基极电阻并且可以进行高速运行。此外，在本征基极区域中产生带隙变窄，并且可以将低温操作中的共发射极电流增益保持在足够的值。当这种同相双极晶体管与半导体衬底表面上的互补绝缘栅场效应晶体管一起形成时，即使在低温操作中也可以获得能够进行高速运行的Bi-CMOS器件。

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