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71. 发明申请

US20080195993A1 Method of Generating Wiring Routes with Matching Delay in the Presence of Process Variation 有权
标题翻译：在过程变化存在下生成具有匹配延迟的接线路由的方法
公开(公告)号：US20080195993A1
公开(公告)日：2008-08-14
申请号：US12107158
申请日：2008-04-22
申请人： Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
发明人： Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first wiring path, a second wiring path, etc. Two or more of the wiring paths are designed to have matching timing, such that the time needed for a signal to travel along the first wiring path is about the same time needed for a signal to travel along the second wiring path, the third path, etc. The method/service designs one or all of the wiring paths to make the paths traverse wire segments of about the same length and orientation, within each wiring level that the first wiring path and the second wiring path traverse. Also, this process makes the first wiring path and the second wiring path traverse the wire segments in the same order, within each wiring level that the first wiring path and the second wiring path traverse.
摘要翻译：电路设计中的平衡延迟的方法和服务从通过布线设计连接在一起的节点开始，或通过提供要被改变的初始布线设计。布线设计将具有许多布线路径，例如第一布线路径，第二布线路径等。两条或多条布线路径被设计成具有匹配的定时，使得信号沿着第一布线路径行进所需的时间信号沿着第二布线路径，第三路径等移动所需的大致相同的时间。该方法/服务设计一个或所有布线路径，以使路径穿过大约相同长度的线段，并且在第一布线路径和第二布线路径横越的各布线层内。此外，该处理使得第一布线路径和第二布线路径在第一布线路径和第二布线路径横越的各布线层内以相同的顺序横穿线段。

72. 发明授权

US06624651B1 Kerf circuit for modeling of BEOL capacitances 有权
标题翻译：用于BEOL电容建模的Kerf电路
公开(公告)号：US06624651B1
公开(公告)日：2003-09-23
申请号：US09684849
申请日：2000-10-06
申请人： David M. Fried , Peter A. Habitz
发明人： David M. Fried , Peter A. Habitz
IPC分类号： G01R3126
CPC分类号： G01R31/006
摘要： A kerf circuit for modeling of Back End Of Line (BEOL) capacitances is disclosed. The kerf circuit contains a clock circuit connected to a number of capacitance testing circuits. Each capacitance testing circuit acts a “bay” that can be configured to test one particular capacitance. The clock circuit allows the capacitance testing circuits to charge and discharge the capacitive structures being tested. By having a number of different capacitance testing circuits, capacitances of many different structures may be tested at one time. This is particularly true if the kerf circuit is repeated several or many times, with each different kerf circuit containing different capacitive testing circuits that themselves contain different capacitive structures. The kerf circuit interfaces to testing equipment through pads. The pads connect to each capacitive testing circuit and allow capacitance measurements to be performed by measuring current.
摘要翻译：公开了一种用于线路后端（BEOL）电容建模的切口电路。切口电路包含连接到多个电容测试电路的时钟电路。每个电容测试电路都作为一个“间隔”，可以配置为测试一个特定的电容。时钟电路允许电容测试电路对被测试的电容结构进行充电和放电。通过具有多个不同的电容测试电路，可以一次测试许多不同结构的电容。如果切割电路重复数次或多次，则特别如此，每个不同的切屑回路包含不同的电容测试电路，它们本身包含不同的电容结构。切口电路通过焊盘与测试设备接口。焊盘连接到每个电容测试电路，并通过测量电流来进行电容测量。

73. 发明授权

US06519752B1 Method of performing parasitic extraction for a multi-fingered transistor 失效
标题翻译：对多指晶体管进行寄生提取的方法
公开(公告)号：US06519752B1
公开(公告)日：2003-02-11
申请号：US09561096
申请日：2000-04-28
申请人： William C. Bakker , L. William Dewey, III , Peter A. Habitz , Judith H. McCullen , Edward W. Seibert , Michael J. Sullivan
发明人： William C. Bakker , L. William Dewey, III , Peter A. Habitz , Judith H. McCullen , Edward W. Seibert , Michael J. Sullivan
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A method and structure for performing parasitic extraction for a multi-fingered device comprising of establishing a maximum processing width of a finger of the device, dividing fingers of the device that exceed the maximum width into sub-fingers, determining whether ones of the fingers and the sub-fingers have similar characteristics, combining ones of the fingers and the sub-fingers that have similar characteristics into combined fingers, and extracting parasitic values from the fingers, the sub-fingers and the combined fingers.
摘要翻译：一种用于对多指装置执行寄生提取的方法和结构，包括：建立装置的手指的最大处理宽度，将超过最大宽度的装置的手指分成子手指，确定手指中是否有手指子手指具有类似的特征，将具有类似特征的手指和子手指组合成组合手指，并从手指，子手指和组合手指中提取寄生值。

74. 发明授权

US06460167B1 Efficient system for multi-level shape interactions 失效
标题翻译：用于多层次形状相互作用的高效系统
公开(公告)号：US06460167B1
公开(公告)日：2002-10-01
申请号：US09559800
申请日：2000-04-27
申请人： L. William Dewey, III , Peter A. Habitz
发明人： L. William Dewey, III , Peter A. Habitz
IPC分类号： G06F1750
CPC分类号： G06F17/5081
摘要： A structure and method for evaluating an integrated circuit design includes adding a superseding layer of the integrated circuit design over a previous layer of the integrated circuit structure, identifying database pointers for regions and edges within the superseding layer and the previous layer, removing database pointers for regions of the previous layer overlapped by the superseding layer, classifying the superseding layer and the previous layer as the previous layer, and repeating the method until all layers of the integrated circuit are evaluated.
摘要翻译：用于评估集成电路设计的结构和方法包括在集成电路结构的先前层上添加集成电路设计的替代层，识别替代层和先前层中的区域和边缘的数据库指针，去除数据库指针上一层的区域与替代层重叠，将取代层和先前层分类为上一层，并重复该方法直到评估集成电路的所有层。

75. 发明授权

US5761080A Method and apparatus for modeling capacitance in an integrated circuit 失效
标题翻译：用于对集成电路中的电容进行建模的方法和装置
公开(公告)号：US5761080A
公开(公告)日：1998-06-02
申请号：US561647
申请日：1995-11-22
申请人： William F. DeCamp , John J. Ellis-Monaghan , Peter A. Habitz , Edward W. Seibert
发明人： William F. DeCamp , John J. Ellis-Monaghan , Peter A. Habitz , Edward W. Seibert
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , Y10S706/921
摘要： According to the present embodiment, a method for calculating the parasitic capacitance in a semiconductor device is disclosed. According to the preferred method, a layout file containing the shapes of a semiconductor device is provided. The dimensions of the layout file are then adjusted to wafer dimensions so as reflect actual production devices. The shapes of the layout file are then partitioned into simpler shapes, typically abutted rectangles, called tiles. Each tile is then decomposed into overlap and fringe capacitance components, each component having a uniform capacitance environment with respect to its capacitance elements. The parasitic capacitance of the semiconductor device can thus be accurately computed, with an efficient use of resources. Additionally the preferred embodiment is easily adaptable to a wide range of technology types.
摘要翻译：根据本实施例，公开了一种用于计算半导体器件中的寄生电容的方法。根据优选方法，提供了包含半导体器件的形状的布局文件。然后将布局文件的尺寸调整为晶圆尺寸，以反映实际的生产设备。然后，布局文件的形状被分割成更简单的形状，通常是称为块的邻接矩形。然后，每个瓦片被分解成重叠和边缘电容分量，每个部件相对于其电容元件具有均匀的电容环境。因此，可以有效利用资源来准确地计算半导体器件的寄生电容。此外，优选实施例容易适应于广泛的技术类型。

76. 发明授权

US08239810B2 Method and system for optimizing a device with current source models 有权
标题翻译：使用当前源模型优化设备的方法和系统
公开(公告)号：US08239810B2
公开(公告)日：2012-08-07
申请号：US12944480
申请日：2010-11-11
申请人： Soroush Abbaspour , Peter Feldmann , Peter A. Habitz , Safar Hatami
发明人： Soroush Abbaspour , Peter Feldmann , Peter A. Habitz , Safar Hatami
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5031 , G06F2217/80 , G06F2217/84
摘要： A method for optimizing a circuit includes at least a first branch and a second branch includes defining an objective function using a shape of waveforms measured at a timing point in each branch, and optimizing the objective function to minimize a variance of clock skew of the first branch and the second branch across different process voltage temperature values.
摘要翻译：一种用于优化电路的方法包括至少第一分支和第二分支，包括使用在每个分支中的定时点测量的波形的形状来定义目标函数，以及优化目标函数以最小化第一分支的时钟偏差的方差分支和第二分支横跨不同的过程电压温度值。

77. 发明授权

US06848089B2 Method and apparatus for detecting devices that can latchup 失效
标题翻译：用于检测可能闭锁的装置的方法和装置
公开(公告)号：US06848089B2
公开(公告)日：2005-01-25
申请号：US10209144
申请日：2002-07-31
申请人： Micah S. Galland , Peter A. Habitz , Steven E. Washburn
发明人： Micah S. Galland , Peter A. Habitz , Steven E. Washburn
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5036 , G06F17/5081
摘要： A method and apparratus for for identifying circuits within an integrated circuit design that are likely to latchup. The present invention accomplishes the identification by searching for suspect circuits and then modifying these circuits to represent a device known by an EDA tool (e.g. FET device). The EDA tool can then be used to determine the likelihood of latchup occuring based upon the modified device.
摘要翻译：用于识别集成电路设计中可能闭锁的电路的方法和附件。本发明通过搜索可疑电路来完成识别，然后修改这些电路以表示由EDA工具（例如FET装置）已知的装置。然后可以使用EDA工具来确定基于修改的装置发生闩锁的可能性。

78. 发明授权

US06757876B2 Method for use of hierarchy in extraction 失效
标题翻译：提取中使用层次结构的方法
公开(公告)号：US06757876B2
公开(公告)日：2004-06-29
申请号：US10064444
申请日：2002-07-15
申请人： Peter A. Habitz
发明人： Peter A. Habitz
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A method and system for extracting circuit characteristics from a circuit design comprises extracting first cell characteristics from a portion of said circuit design using a first set of environmental conditions. The invention then extracts second cell characteristics from the portion of the circuit design using a second set of environmental conditions. The invention determines a difference between the first cell characteristics and the second cell characteristics and labels a placeability of the portion of the circuit design based on the difference.
摘要翻译：用于从电路设计中提取电路特性的方法和系统包括使用第一组环境条件从所述电路设计的一部分中提取第一单元特性。然后，本发明使用第二组环境条件从电路设计的部分中提取第二电池特性。本发明确定了第一单元特性和第二单元特性之间的差异，并且基于该差来标记电路设计的该部分的可放置性。

79. 发明授权

US06430729B1 Process and system for maintaining 3 sigma process tolerance for parasitic extraction with on-the-fly biasing 失效
标题翻译：用于通过动态偏置来保持寄生提取的3西格玛过程公差的过程和系统
公开(公告)号：US06430729B1
公开(公告)日：2002-08-06
申请号：US09494975
申请日：2000-01-31
申请人： L. William Dewey , Peter A. Habitz , Judith H. McCullen , Edward W. Seibert
发明人： L. William Dewey , Peter A. Habitz , Judith H. McCullen , Edward W. Seibert
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A method and structure for a method of determining characteristics of parasitic elements in an integrated circuit comprising, identifying manufacturing process parameters of devices in the integrated circuit, calculating a parasitic performance distribution for each of the devices based on the manufacturing process parameters, combining the parasitic performance distribution for each of the devices into a net parasitic value, and forming a parameterized model based on the net parasitic values.
摘要翻译：一种用于确定集成电路中的寄生元件的特性的方法的方法和结构，包括：识别集成电路中的器件的制造工艺参数，基于制造工艺参数计算每个器件的寄生性能分布，组合寄生每个器件的性能分布成为净寄生值，并且基于净寄生值形成参数化模型。

80. 发明授权

US08855993B2 Integrated circuit design simulation matrix interpolation 有权
标题翻译：集成电路设计仿真矩阵插值
公开(公告)号：US08855993B2
公开(公告)日：2014-10-07
申请号：US13251517
申请日：2011-10-03
申请人： Peter A. Habitz , Amol A. Joshi
发明人： Peter A. Habitz , Amol A. Joshi
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Methods and systems perform a simulation on an integrated circuit design by applying a first value to a first variable and a second value to a second variable of the simulation to produce a first matrix corner simulation value. The methods and systems repeat the simulation using different values for the first and said second variables to produce a second matrix corner simulation value, a third matrix corner simulation value, and a fourth matrix corner simulation value. The methods and systems create a matrix, and the matrix has the first matrix corner simulation value, the second matrix corner simulation value, the third matrix corner simulation value, and the fourth matrix corner simulation value. The methods and systems interpolate all remaining values within the matrix based upon existing simulation values within the matrix.
摘要翻译：方法和系统通过将第一值应用于第一变量和第二值到模拟的第二变量来对集成电路设计进行仿真以产生第一矩阵角模拟值。方法和系统使用不同的值对第一和第二变量重复模拟，以产生第二矩阵角模拟值，第三矩阵角模拟值和第四矩阵角模拟值。方法和系统创建矩阵，矩阵具有第一矩阵角模拟值，第二矩阵角模拟值，第三矩阵角模拟值和第四矩阵角模拟值。方法和系统基于矩阵内的现有模拟值来内插矩阵内的所有剩余值。

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