专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明授权

US07495956B2 Reducing read disturb for non-volatile storage 有权
标题翻译：减少非易失性存储的读取干扰
公开(公告)号：US07495956B2
公开(公告)日：2009-02-24
申请号：US12021761
申请日：2008-01-29
申请人： Yupin Fong , Jun Wan , Jeffrey Lutze
发明人： Yupin Fong , Jun Wan , Jeffrey Lutze
IPC分类号： G11C11/34
CPC分类号： G11C16/3418 , G11C16/3427
摘要： A system is disclosed for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the memory elements. For example, one implementation prevents or reduces boosting of the source side of the NAND string channel during a read process. Because the source side of the NAND string channel is not boosted, at least one form of read disturb is minimized or does not occur.
摘要翻译：公开了一种用于减少或去除非易失性存储设备中的读取干扰形式的系统。一个实施例旨在通过消除或最小化存储器元件的通道的升高来防止读取干扰。例如，一个实施方式在读取过程期间防止或减少NAND串通道的源极侧的升压。因为NAND串通道的源极侧不被提升，所以读取干扰的至少一种形式被最小化或不发生。

72. 发明申请

US20090004843A1 METHOD FOR FORMING DUAL BIT LINE METAL LAYERS FOR NON-VOLATILE MEMORY 有权
标题翻译：用于形成用于非易失性存储器的双位线金属层的方法
公开(公告)号：US20090004843A1
公开(公告)日：2009-01-01
申请号：US11768461
申请日：2007-06-26
申请人： Nima Mokhlesi , Jun Wan
发明人： Nima Mokhlesi , Jun Wan
IPC分类号： H01L21/768
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： Structures and techniques are disclosed for reducing bit line to bit line capacitance in a non-volatile storage system. The bit lines are formed at a 4f pitch in each of two separate metal layers, and arranged to alternate between each of the layers. In an alternative embodiment, shields are formed between each of the bit lines on each metal layer.
摘要翻译：公开了用于在非易失性存储系统中减少位线到位线电容的结构和技术。位线在两个分离的金属层的每一个中以4f间距形成，并且布置成在每个层之间交替。在替代实施例中，在每个金属层上的每个位线之间形成屏蔽。

73. 发明申请

US20090003025A1 DUAL BIT LINE METAL LAYERS FOR NON-VOLATILE MEMORY 有权
标题翻译：用于非易失性存储器的双位线金属层
公开(公告)号：US20090003025A1
公开(公告)日：2009-01-01
申请号：US11768468
申请日：2007-06-26
申请人： Nima Mokhlesi , Jun Wan
发明人： Nima Mokhlesi , Jun Wan
IPC分类号： G11C5/02
CPC分类号： G11C5/063 , G11C7/02 , G11C7/1006 , G11C7/18 , G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： Structures and techniques are disclosed for reducing bit line to bit line capacitance in a non-volatile storage system. The bit lines are formed at a 4 f pitch in each of two separate metal layers, and arranged to alternate between each of the layers. In an alternative embodiment, shields are formed between each of the bit lines on each metal layer.
摘要翻译：公开了用于在非易失性存储系统中减少位线到位线电容的结构和技术。在两个分离的金属层的每一个中，位线以4f间距形成，并且布置成在每个层之间交替。在替代实施例中，在每个金属层上的每个位线之间形成屏蔽。

74. 发明申请

US20080137424A1 REDUCING READ DISTURB FOR NON-VOLATILE STORAGE 有权
标题翻译：减少读取干扰非易失性存储
公开(公告)号：US20080137424A1
公开(公告)日：2008-06-12
申请号：US12021741
申请日：2008-01-29
申请人： Yupin Fong , Jun Wan , Jeffrey Lutze
发明人： Yupin Fong , Jun Wan , Jeffrey Lutze
IPC分类号： G11C16/06
CPC分类号： G11C16/3418 , G11C16/3427
摘要： A system is disclosed for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the memory elements. For example, one implementation prevents or reduces boosting of the source side of the NAND string channel during a read process. Because the source side of the NAND string channel is not boosted, at least one form of read disturb is minimized or does not occur.
摘要翻译：公开了一种用于减少或去除非易失性存储设备中的读取干扰形式的系统。一个实施例旨在通过消除或最小化存储器元件的通道的升高来防止读取干扰。例如，一个实施方式在读取过程期间防止或减少NAND串通道的源极侧的升压。因为NAND串通道的源极侧不被提升，所以读取干扰的至少一种形式被最小化或不发生。

75. 发明授权

US07372392B1 Charge balancing method in a current input ADC 有权
标题翻译：电流输入ADC中的电荷平衡方法
公开(公告)号：US07372392B1
公开(公告)日：2008-05-13
申请号：US11679070
申请日：2007-02-26
申请人： Jun Wan , Peter R. Holloway
发明人： Jun Wan , Peter R. Holloway
IPC分类号： H03M1/12
CPC分类号： H03M1/0607 , H03F3/45179 , H03F3/45183 , H03F3/45475 , H03F3/45766 , H03F2200/264 , H03F2203/45136 , H03F2203/45212 , H03F2203/45342 , H03F2203/45352
摘要： A method for charge balancing in a current input ADC including maintaining a low capacitance value at the integrator output node where the capacitance value is independent of the integrator output voltage and operating conditions, generating a first voltage pedestal at a first active device switch at the end of the autozero phase having a first voltage polarity and a first magnitude, generating a second voltage pedestal at a second active device switch at the end of the integration phase having an opposite voltage polarity and the first magnitude, and summing the first voltage pedestal with the second voltage pedestal. The difference between the first voltage pedestal and the second voltage pedestal results in a net voltage error. The first and second voltage pedestals have the first magnitude under all operating conditions of the modulator and the two voltage pedestals cancel to yield a small net voltage error.
摘要翻译：一种用于电流输入ADC中的电荷平衡的方法，包括在积分器输出节点处维持低电容值，其中电容值与积分器输出电压和工作条件无关，在最终的第一有源器件开关处产生第一电压基座的自相位相具有第一电压极性和第一幅度，在具有相反电压极性和第一幅度的积分相位结束时在第二有源器件开关处产生第二电压基座，并且将第一电压基座与第二电压基座。第一电压基座和第二电压基座之间的差异导致净电压误差。第一和第二电压基座在调制器的所有工作条件下都具有第一幅度，并且两个电压基座取消以产生小的净电压误差。

76. 发明授权

US07331708B2 Frequency ratio digitizing temperature sensor with linearity correction 有权
标题翻译：频率比数字化温度传感器具有线性校正
公开(公告)号：US07331708B2
公开(公告)日：2008-02-19
申请号：US11361912
申请日：2006-02-23
申请人： Eric D. Blom , Jun Wan , Stuart H. Urie
发明人： Eric D. Blom , Jun Wan , Stuart H. Urie
IPC分类号： G01K7/14 , H03K3/01
CPC分类号： G01K7/01
摘要： A frequency ratio digitizing temperature sensor for generating a linearity-corrected temperature output signal includes an input generation circuit receiving a PTAT current and a CTAT current and a frequency ratio ADC including data and reference oscillators. The input generation circuit generates a first current from the weighted sum of the PTAT current and the CTAT current and also generates a first corrected current being the sum of the first current and a first portion of the PTAT current. The input generation circuit provides a first output current indicative of the PTAT current and a first output voltage generated by applying the first corrected current to a first resistor for use with the data oscillator and provides a second output current being the first corrected current and a second output voltage generated by applying the first current to a second resistor for use with the reference oscillator of the ADC.
摘要翻译：用于产生线性校正温度输出信号的频率比数字化温度传感器包括接收PTAT电流和CTAT电流的输入产生电路和包括数据和参考振荡器的频率比ADC。输入产生电路根据PTAT电流和CTAT电流的加权和产生第一电流，并且还产生第一校正电流，该第一校正电流是PTAT电流的第一电流和第一部分之和。输入产生电路提供指示PTAT电流的第一输出电流和通过将第一校正电流施加到与数据振荡器一起使用的第一电阻器产生的第一输出电压，并提供作为第一校正电流的第二输出电流和第二输出电流通过将第一电流施加到与ADC的参考振荡器一起使用的第二电阻器产生的输出电压。

77. 发明授权

US07295473B2 System for reducing read disturb for non-volatile storage 有权
标题翻译：用于减少非易失性存储的读取干扰的系统
公开(公告)号：US07295473B2
公开(公告)日：2007-11-13
申请号：US11681188
申请日：2007-03-02
申请人： Yupin Fong , Jun Wan , Jeffrey Lutze
发明人： Yupin Fong , Jun Wan , Jeffrey Lutze
IPC分类号： G11C11/34
CPC分类号： G11C16/3418 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/3427
摘要： A system for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the memory elements. For example, one implementation prevents or reduces boosting of the source side of the NAND string channel during a read process. Because the source side of the NAND string channel is not boosted, at least one form of read disturb is minimized or does not occur.
摘要翻译：一种用于在非易失性存储设备中减少或去除读取干扰形式的系统。一个实施例旨在通过消除或最小化存储器元件的通道的升高来防止读取干扰。例如，一个实施方式在读取过程期间防止或减少NAND串通道的源极侧的升压。因为NAND串通道的源极侧不被提升，所以读取干扰的至少一种形式被最小化或不发生。

78. 发明申请

US20070195856A1 Frequency ratio digitizing temperature sensor with linearity correction 有权
标题翻译：频率比数字化温度传感器具有线性校正
公开(公告)号：US20070195856A1
公开(公告)日：2007-08-23
申请号：US11361912
申请日：2006-02-23
申请人： Eric Blom , Jun Wan , Stuart Urie
发明人： Eric Blom , Jun Wan , Stuart Urie
IPC分类号： G01K11/22
CPC分类号： G01K7/01
摘要： A frequency ratio digitizing temperature sensor for generating a linearity-corrected temperature output signal includes an input generation circuit receiving a PTAT current and a CTAT current and a frequency ratio ADC including data and reference oscillators. The input generation circuit generates a first current from the weighted sum of the PTAT current and the CTAT current and also generates a first corrected current being the sum of the first current and a first portion of the PTAT current. The input generation circuit provides a first output current indicative of the PTAT current and a first output voltage generated by applying the first corrected current to a first resistor for use with the data oscillator and provides a second output current being the first corrected current and a second output voltage generated by applying the first current to a second resistor for use with the reference oscillator of the ADC.
摘要翻译：用于产生线性校正温度输出信号的频率比数字化温度传感器包括接收PTAT电流和CTAT电流的输入产生电路和包括数据和参考振荡器的频率比ADC。输入产生电路根据PTAT电流和CTAT电流的加权和产生第一电流，并且还产生第一校正电流，该第一校正电流是PTAT电流的第一电流和第一部分之和。输入产生电路提供指示PTAT电流的第一输出电流和通过将第一校正电流施加到与数据振荡器一起使用的第一电阻器产生的第一输出电压，并提供作为第一校正电流的第二输出电流和第二输出电流通过将第一电流施加到与ADC的参考振荡器一起使用的第二电阻器产生的输出电压。

79. 发明授权

US07119612B1 Dual-channel instrumentation amplifier 有权
标题翻译：双通道仪表放大器
公开(公告)号：US07119612B1
公开(公告)日：2006-10-10
申请号：US10954417
申请日：2004-09-29
申请人： Peter R. Holloway , Jun Wan
发明人： Peter R. Holloway , Jun Wan
IPC分类号： H03F1/02 , H03F3/45
CPC分类号： H03F1/02 , H03F3/45179 , H03F3/45188 , H03F3/45475 , H03F3/68 , H03F2200/261 , H03F2200/78 , H03F2203/45318 , H03F2203/45521
摘要： A dual-channel instrumentation amplifier includes two channels of PMOS transistor differential pairs which are configured in a Y-connection and cross-coupled to two diode-connected NMOS transistors. Each input channel has a non-linear voltage-current characteristic. But when the differential currents cancel at the NMOS transistor diodes, both input channels have the same differential input voltage, regardless of any non-linearity. As thus configured, a high accuracy instrumentation amplifier which operates in current mode is realized with excellent DC matching and high common mode rejection ratio. In one embodiment, the dual-channel instrumentation amplifier is used as input stage for the linear comparator to enable the linear comparator to operate at a high rate of speed with excellent channel matching.
摘要翻译：双通道仪表放大器包括两个PMOS晶体管差分对通道，它们被配置为Y形连接并交叉耦合到两个二极管连接的NMOS晶体管。每个输入通道具有非线性电压 - 电流特性。但是当NMOS晶体管二极管上的差分电流消失时，两个输入通道都具有相同的差分输入电压，无论任何非线性。如此配置，通过优异的直流匹配和高共模抑制比实现了以电流模式工作的高精度仪表放大器。在一个实施例中，双通道仪表放大器用作线性比较器的输入级，使得线性比较器能够以高速率运行，具有出色的通道匹配。

80. 发明授权

US07023737B1 System for programming non-volatile memory with self-adjusting maximum program loop 有权
标题翻译：用于自适应最大程序循环编程非易失性存储器的系统
公开(公告)号：US07023737B1
公开(公告)日：2006-04-04
申请号：US11194827
申请日：2005-08-01
申请人： Jun Wan , Jeffrey W. Lutze
发明人： Jun Wan , Jeffrey W. Lutze
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10
摘要： The maximum allowable number of voltage programming pulses to program memory elements of a non-volatile memory device is adjusted to account for changes in the memory elements which occur over time. Programming pulses are applied until the threshold voltage of one or more memory elements reaches a certain verify level, after which a defined maximum number of additional pulses may be applied to other memory elements to allow them to also reach associated target threshold voltage levels. The technique enforces a maximum allowable number of programming pulses that can change over time as the memory is cycled.
摘要翻译：调整非易失性存储器件对程序存储器元件的电压编程脉冲的最大允许数量，以便考虑随时间发生的存储元件的变化。施加编程脉冲，直到一个或多个存储器元件的阈值电压达到某个验证电平，之后可以将限定的最大数量的附加脉冲施加到其它存储器元件以允许它们也达到相关联的目标阈值电压电平。该技术实现了随着存储器循环而随时间变化的最大允许编程脉冲数。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式