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71. 发明授权

US08275644B2 Generating an optimized analytical business transformation 失效
标题翻译：生成优化的分析业务转型
公开(公告)号：US08275644B2
公开(公告)日：2012-09-25
申请号：US12103757
申请日：2008-04-16
申请人： Moises Cases , Bhyrav M. Mutnury
发明人： Moises Cases , Bhyrav M. Mutnury
IPC分类号： G06F17/30
CPC分类号： G09B19/18 , G06Q10/06 , G06Q10/0633
摘要： Techniques for optimizing a Business Process Model (BPM) having at least one work process are presented. At a simulation client, a determination is made whether a simulated business outcome associated with a test BPM satisfies a business value deficiency associated with a current BPM. In response to a determination that the simulated business outcome does not satisfy the business value deficiency, the test BPM is optimized. Once the simulation client determines that the simulated business outcome satisfies the business value deficiency, the test BPM is implemented as an actual BPM. Moreover, an actual business outcome associated with the actual BPM is generated. A determination is made whether the actual business outcome satisfies the simulated business outcome. In response to a determination that the actual business outcome does not satisfy the simulated business outcome, the actual BPM is optimized.
摘要翻译：提出了具有至少一个工作流程的优化业务流程模型（BPM）的技术。在模拟客户端，确定与测试BPM相关联的模拟业务结果是否满足与当前BPM相关联的业务价值缺陷。针对模拟业务成果不能满足业务价值不足的判断，对BPM进行了优化。一旦模拟客户端确定模拟业务结果满足业务价值不足，则将测试BPM实现为实际BPM。此外，生成与实际BPM相关联的实际业务成果。确定实际业务成果是否满足模拟业务成果。针对实际业务成果不符合模拟业务成果的判断，实际BPM得到优化。

72. 发明申请

US20120193135A1 Through-Hole-Vias In Multi-Layer Printed Circuit Boards 有权
标题翻译：多层印刷电路板中的通孔
公开(公告)号：US20120193135A1
公开(公告)日：2012-08-02
申请号：US13446727
申请日：2012-04-13
申请人： Moises Cases , Tae Hong Kim , Rohan U. Mandrekar , Nusrat I. Sherali
发明人： Moises Cases , Tae Hong Kim , Rohan U. Mandrekar , Nusrat I. Sherali
IPC分类号： H05K1/11
CPC分类号： H05K3/0094 , H05K1/0234 , H05K1/0242 , H05K1/0251 , H05K1/09 , H05K1/167 , H05K3/0047 , H05K3/244 , H05K3/429 , H05K2201/0391 , Y10T29/49126 , Y10T29/4913 , Y10T29/49155 , Y10T29/49165 , Y10T156/1057 , Y10T428/12528
摘要： Example multi-layer printed circuit boards (‘PCBs’) are described as well as methods of making and using such PCBs that include layers of laminate; at least one via hole traversing the layers of laminate, and a via conductor contained within the via hole, the via conductor comprising a used portion and an unused portion, the via conductor comprising copper coated with a metal having a conductivity lower than the conductivity of copper.
摘要翻译：描述了例如多层印刷电路板（“PCB”），以及制造和使用这种包括层压层的PCB的方法; 穿过层压体层的至少一个通孔，以及包含在通孔内的通孔导体，所述通孔导体包括使用部分和未使用部分，所述通孔导体包括涂覆有电导率低于铜。

73. 发明授权

US08201133B2 Printed circuit board with reduced signal distortion 有权
标题翻译：印刷电路板，信号失真减少
公开(公告)号：US08201133B2
公开(公告)日：2012-06-12
申请号：US12140730
申请日：2008-06-17
申请人： Moises Cases , Tae H. Kim , Bhyrav M. Mutnury
发明人： Moises Cases , Tae H. Kim , Bhyrav M. Mutnury
IPC分类号： G06F17/50
CPC分类号： H05K1/0224 , H05K1/0225 , H05K1/0237 , H05K1/0253 , H05K3/0005 , H05K2201/09681 , Y10T29/49124
摘要： A printed circuit board with reduced signal distortion, including one or more layers of non-conductive substrate upon which are disposed conductive pathways that conduct signals, the signals characterized by distortion at least partly caused by orientation of the conductive pathways on the layers of the printed circuit board, and a periodically patterned reference plane; each conductive pathway that conducts signals oriented orthogonally or diagonally at forty-five degrees with respect to other conductive pathways that conduct signals on the printed circuit board; the periodically patterned reference plane comprising a conductor having discontinuities arranged in a periodically recurring pattern, the pattern of the discontinuities oriented on a surface of a layer of the printed circuit board at an optimum angle, with respect to the conductive pathways that conduct signals on the printed circuit board, that reduces distortion of the signals.
摘要翻译：具有降低的信号失真的印刷电路板，包括一层或多层不导电基底，在其上设置传导信号的导电路径，其特征在于至少部分地由印刷的层上的导电路径的取向引起的变形电路板和周期性图案化参考平面; 每个导电通路相对于在印刷电路板上传导信号的其它导电通路传导正交或对角地定向四十五度的信号; 所述周期性图案化参考平面包括具有以周期性重复图案布置的不连续性的导体，所述不连续性的图案相对于在所述印刷电路板上传导信号的导电路径以最佳角度定向在所述印刷电路板的层的表面上印刷电路板，可以减少信号的失真。

74. 发明授权

US08140441B2 Workflow management in a global support organization 有权
标题翻译：全球支持机构的工作流管理
公开(公告)号：US08140441B2
公开(公告)日：2012-03-20
申请号：US12254092
申请日：2008-10-20
申请人： Moises Cases , Oliver R. Fasterling , Bhyrav M. Mutnury
发明人： Moises Cases , Oliver R. Fasterling , Bhyrav M. Mutnury
IPC分类号： G06Q10/00
CPC分类号： G06Q10/10 , G06Q10/06 , G06Q10/0633 , G06Q30/016
摘要： Customer support involves multiple levels of support, where customer support personnel at higher levels have more experience and a higher cost associated with their services. A random assignment of support personnel to a problem, at lower levels, can lead to multiple call transfers, a customer being put “on hold”, ineffective resource utilization, and high service costs being billed to customers. Functionality can be implemented to assign a support person to resolve the customer's problem based on a multi-dimensional dynamic social network database of resources (e.g., personnel experience, success rate, skill set, social network, etc.) which allows for efficient assignment of support personnel to a problem. Routing a customer call to the most appropriate support person at a given level before determining support personnel at higher levels can ensure optimization in terms of return on investment and resource utilization. Optimally selecting and assigning support personnel can also ensure customer satisfaction.
摘要翻译：客户支持涉及多层次的支持，上级的客户支持人员具有更多的经验和更高的与其服务相关的成本。支持人员在较低层面随机分配问题可导致多次呼叫转移，客户被“搁置”，资源利用率低下，并向客户收取高昂的服务费用。基于多维动态社会网络资源数据库（如人事经验，成功率，技能，社交网络等），可以实施功能来分配支持人员来解决客户的问题，从而有效地分配支持人员出现问题。在确定较高级别的支持人员之前，将客户呼叫路由到最适合的支持人员，以确保优化投资回报和资源利用率。最优选择和分配支持人员也可以确保客户满意。

75. 发明授权

US08102042B2 Reducing plating stub reflections in a chip package using resistive coupling 失效
标题翻译：使用电阻耦合减少芯片封装中的电镀短截线反射
公开(公告)号：US08102042B2
公开(公告)日：2012-01-24
申请号：US12630720
申请日：2009-12-03
申请人： Moises Cases , Bhyrav M. Mutnury , Nanju Na
发明人： Moises Cases , Bhyrav M. Mutnury , Nanju Na
IPC分类号： H01L23/498
CPC分类号： H05K1/0234 , H01L24/73 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2924/14 , H01L2924/15311 , H05K3/242 , H05K2203/049 , Y10T29/49128 , H01L2924/00012 , H01L2924/00014 , H01L2924/00
摘要： Improving signal quality in a high-frequency chip package by resistively connecting an open-ended plating stub to ground. One embodiment provides a multi-layer substrate for interfacing a chip with a printed circuit board. A conductive first layer provides a chip mounting location. A signal interconnect is spaced from the chip mounting location, and a signal trace extends from near the chip mounting location to the signal interconnect. A chip mounted at the chip mounting location may be connected to the signal trace by wirebonding. A plating stub extends from the signal interconnect, such as to a periphery of the substrate. A resistor is used to resistively couple the plating stub to a ground layer.
摘要翻译：通过将开口电镀短截线电阻连接到地来提高高频芯片封装中的信号质量。一个实施例提供了用于将芯片与印刷电路板接口的多层基板。导电第一层提供芯片安装位置。信号互连与芯片安装位置间隔开，并且信号迹线从芯片安装位置附近延伸到信号互连。安装在芯片安装位置的芯片可以通过引线键合连接到信号迹线。电镀短截线从信号互连延伸到衬底的周围。电阻器用于将电镀端子电阻耦合到接地层。

76. 发明授权

US08084692B2 Reducing noise coupling in high speed digital systems 有权
标题翻译：降低高速数字系统中的噪声耦合
公开(公告)号：US08084692B2
公开(公告)日：2011-12-27
申请号：US11924416
申请日：2007-10-25
申请人： Moises Cases , Bradley D. Herrman , Kent B. Howieson , Erdem Matoglu , Bhyrav M. Mutnury , Pravin S. Patel , Nam H. Pham , Caleb J. Wesley
发明人： Moises Cases , Bradley D. Herrman , Kent B. Howieson , Erdem Matoglu , Bhyrav M. Mutnury , Pravin S. Patel , Nam H. Pham , Caleb J. Wesley
IPC分类号： H05K1/03
CPC分类号： H05K1/024 , H05K3/4611 , H05K3/4697 , H05K2201/09236 , H05K2201/09318 , H05K2203/063 , Y10T29/49117 , Y10T29/49126 , Y10T29/4913 , Y10T29/49155 , Y10T29/49158 , Y10T29/49165 , Y10T156/1013
摘要： An apparatus having reduced noise coupling includes a core layer having an upper and lower surface, the upper and lower surface each including a copper sheet layer, a pre-preg layer having an upper surface and a lower surface, the upper surface of the pre-preg layer coupled to the lower surface of the core layer, a core insulating layer having an upper surface and a lower surface, the upper surface of the core insulating layer coupled to the lower surface of the pre-preg layer, a return current reference layer disposed on the lower surface of the core insulator layer and high-speed signal traces disposed on the upper surface of the core insulating layer, each of the high speed signal traces disposed on a pedestal defined by a section of the pre-preg layer and the core insulating layer, each pedestal being separated by an air gap disposed between adjacent pedestals.
摘要翻译：具有降低的噪声耦合的装置包括具有上表面和下表面的芯层，所述上表面和下表面各自包括铜片层，具有上表面和下表面的预浸层，耦合到芯层的下表面的芯层绝缘层，具有上表面和下表面的芯绝缘层，芯绝缘层的上表面耦合到预浸层的下表面，返回电流参考层设置在芯绝缘体层的下表面和设置在芯绝缘层的上表面上的高速信号迹线，每个高速信号迹线设置在由预浸层的一部分限定的基座上，芯绝缘层，每个基座由设置在相邻基座之间的气隙分隔开。

77. 发明授权

US07987110B2 Managing organizational resources 失效
标题翻译：管理组织资源
公开(公告)号：US07987110B2
公开(公告)日：2011-07-26
申请号：US11828111
申请日：2007-07-25
申请人： Moises Cases , Candice Leontine Coletrane , Bhyrav Murthy Mutnury , Scott Lee Winters
发明人： Moises Cases , Candice Leontine Coletrane , Bhyrav Murthy Mutnury , Scott Lee Winters
IPC分类号： G06Q10/00
CPC分类号： G06Q30/02 , G06Q10/06311 , G06Q10/06315 , G06Q50/01
摘要： A computer implemented method, apparatus, and computer program product for managing organizational resources. The process combines social group data with management information data to form social network data, wherein social group data is derived from interactions among a plurality of users of a social group. The process analyzes the social network data to identify associations among the plurality of users, and generates a multidimensional social network model using the associations among the plurality of users. Thereafter, the process presents a set of recommendations for allocation of the organizational resources, wherein the set of recommendations are derived from the social network model.
摘要翻译：一种用于管理组织资源的计算机实现的方法，装置和计算机程序产品。该过程将社会群体数据与管理信息数据组合以形成社交网络数据，其中社交群组数据源自社交群体的多个用户之间的交互。该过程分析社交网络数据以识别多个用户之间的关联，并且使用多个用户之间的关联来生成多维社交网络模型。此后，该过程提出了一组关于组织资源分配的建议，其中一组建议源于社交网络模型。

78. 发明申请

US20110140709A1 LOCATING SHORT CIRCUITS IN PRINTED CIRCUIT BOARDS 有权
标题翻译：在印刷电路板中定位短路
公开(公告)号：US20110140709A1
公开(公告)日：2011-06-16
申请号：US12638044
申请日：2009-12-15
申请人： Moises Cases , Bhyrav M. Mutnury , Terence Rodrigues
发明人： Moises Cases , Bhyrav M. Mutnury , Terence Rodrigues
IPC分类号： G01R31/28 , G01R31/11
CPC分类号： G01R31/2812
摘要： One embodiment provides a method of locating a short circuit in a printed circuit board. Test signals may be injected at different test points on the circuit board. The distance between each test point and the short circuit may be determined according to how long it takes for a signal reflection at the short circuit to propagate back to each test point. The distances between the various test points and the short circuit can be used to narrow the possible locations of the short circuit or even to pinpoint the location of the short circuit.
摘要翻译：一个实施例提供了一种定位印刷电路板中的短路的方法。测试信号可以在电路板上的不同测试点注入。每个测试点和短路之间的距离可以根据短路信号反射传播回每个测试点所需的时间来确定。各种测试点和短路之间的距离可用于缩小短路的可能位置，甚至可以精确定位短路位置。

79. 发明申请

US20110103030A1 Packages and Methods for Mitigating Plating Stub Effects 审中-公开
标题翻译：减轻电镀桩影响的包装和方法
公开(公告)号：US20110103030A1
公开(公告)日：2011-05-05
申请号：US12610413
申请日：2009-11-02
申请人： Moises Cases , Tae Hong Kim , Bhyrav M. Mutnury , Nanju Na
发明人： Moises Cases , Tae Hong Kim , Bhyrav M. Mutnury , Nanju Na
IPC分类号： H01L23/52 , H01L21/60 , H05K7/00
CPC分类号： H01L23/647 , H01L23/49838 , H01L23/66 , H01L24/45 , H01L24/48 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/19105 , H01L2924/3011 , H01L2924/00014
摘要： Packages and methods for mitigating plating stub effects. The semiconductor package includes an interposer substrate having a first side, a second side, a peripheral edge connecting the first side with the second side, a signal line on the first side, and an electrode pad on the first side. A semiconductor element is mounted on the first side of the interposer substrate. The semiconductor element is connected with the electrode pad by the signal line. A terminating resistor is mounted on the interposer substrate. A plating stub, which is located on the interposer substrate, has a first end portion that terminates near the peripheral edge of the interposer substrate and a second end portion that is electrically connected to the electrode. The first end portion is electrically connected through the terminating resistor to an electrical ground.
摘要翻译：用于减轻电镀桩效应的包装和方法。半导体封装包括具有第一侧，第二侧，连接第一侧与第二侧的周边边缘，第一侧上的信号线和第一侧上的电极焊盘的插入器基板。半导体元件安装在插入器基板的第一侧上。半导体元件通过信号线与电极焊盘连接。终端电阻器安装在插入器基板上。位于内插基板上的电镀短截线具有在中介基板的周缘附近终止的第一端部和与该电极电连接的第二端部。第一端部通过终端电阻器电连接到电接地。

80. 发明授权

US07868652B1 Off-die termination module with a spring loaded pin in a DIMM socket 有权
标题翻译：脱模终端模块，弹簧加载销插入DIMM插槽
公开(公告)号：US07868652B1
公开(公告)日：2011-01-11
申请号：US12632864
申请日：2009-12-08
申请人： Moises Cases , Bhyrav M. Mutnury , Nam H. Pham
发明人： Moises Cases , Bhyrav M. Mutnury , Nam H. Pham
IPC分类号： H03K17/16
CPC分类号： G06F13/4086
摘要： Off-die termination module for terminating memory module signal lines in a computer memory subsystem, the computer memory subsystem including a memory controller and a DIMM socket, the memory controller coupled to the DIMM socket via a memory module signal line, the off-die termination module including: an off-die termination component configured to terminate the memory module signal line upon activation; and a spring loaded notch pin implemented as part of the DIMM socket, the spring loaded notch pin configured to toggle activation of the off-die termination component in dependence upon presence of a DIMM in the DIMM socket including activating the off-die termination component upon removal of a DIMM from the DIMM socket and deactivating the off-die termination component upon installation of a DIMM in the DIMM socket.
摘要翻译：用于终止计算机存储器子系统中的存储器模块信号线的裸片终端模块，所述计算机存储器子系统包括存储器控制器和DIMM插槽，所述存储器控制器经由存储器模块信号线耦合到所述DIMM插槽，所述离线端子模块包括：非激活终端组件，被配置为在激活时终止所述存储器模块信号线; 以及作为所述DIMM插座的一部分实现的弹簧加载的凹口销，所述弹簧加载的凹口销被配置为根据DIMM插槽中存在的DIMM来切换所述离模端接部件的启动，包括在所述DIMM插座上激活所述离模终端组件从DIMM插槽中取出DIMM，并在DIMM插槽中安装DIMM时停用裸片端接组件。

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