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71. 发明申请

US20090223796A1 ROTARY SWITCH 失效
标题翻译：旋转开关
公开(公告)号：US20090223796A1
公开(公告)日：2009-09-10
申请号：US11980824
申请日：2007-10-31
申请人： Chen-Hong Huang , Chien-Hung Chen , Chia-Yi Cheng
发明人： Chen-Hong Huang , Chien-Hung Chen , Chia-Yi Cheng
IPC分类号： H01H19/63
CPC分类号： H01H19/63
摘要： A rotary switch includes a holder base holding two metal contact plates and one metal connection plate, a rotary handle vertically pivotally coupled to a pivot shaft of the holder base and rotatable relative to the holder base between a first position where a bottom recess of a circular actuating member of the rotary handle receives a respective electric connection portion of each metal contact plate and the electric connection portion of the metal connection plate contacts the electric connection portions of the metal contact plates and a second position where a protrusion of the circular actuating member forces the electric connection portion of one metal contact plate away from the metal connection plate to produce an electrical signal, and a torsion spring sleeved on the rotary handle with its two ends respective connected to the actuating member and the holder base for returning the rotary handle automatically after each rotary motion.
摘要翻译：旋转开关包括保持基座，其保持两个金属接触板和一个金属连接板，旋转手柄垂直地枢转地联接到保持器基座的枢轴并且可相对于保持器基座旋转，在第一位置和第二位置之间，旋转手柄的致动构件接收每个金属接触板的相应电连接部分，并且金属连接板的电连接部分接触金属接触板的电连接部分和第二位置，其中圆形致动部件的突出部分一个金属接触板的电连接部分远离金属连接板以产生电信号，以及一个套在旋转手柄上的扭力弹簧，其两端分别连接到致动构件和保持架底座，用于自动返回旋转手柄每次旋转运动后。

72. 发明申请

US20090191691A1 Method for singulating semiconductor devices 审中-公开
标题翻译：分离半导体器件的方法
公开(公告)号：US20090191691A1
公开(公告)日：2009-07-30
申请号：US12010723
申请日：2008-01-29
申请人： Chien-Hung Chen
发明人： Chien-Hung Chen
IPC分类号： H01L21/304
CPC分类号： H01L21/78 , B23K26/18 , B23K26/702 , H01L21/481 , H01L23/544 , H01L24/48 , H01L24/97 , H01L2223/5442 , H01L2223/54473 , H01L2224/16 , H01L2224/48091 , H01L2224/48227 , H01L2224/97 , H01L2924/00014 , H01L2924/01033 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/15311 , H01L2924/181 , H05K3/0032 , H05K3/0052 , H05K2203/0191 , H05K2203/1383 , H01L2224/85 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Disclosed is a method for singulating semiconductor devices. The substrate has a plurality of scribe lines between the substrate units. A protecting film is provided having a patterned adhesive layer formed thereon corresponding to the scribe lines. The protecting film is attached and aligned to the substrate in a manner that the patterned adhesive layer adheres to the scribe lines without covering the substrate units. The substrate is cut by a laser beam aimed at the protecting film firstly and cut through the substrate along the peripheries of the scribe lines to singulate the substrate units. Therefore, the residue films of the protecting film on the substrate units can easily be removed. The contaminations of the substrate units by the sputtered particles and the melted protecting film during laser cutting can be eliminated. The shapes of the substrate units can be diverse.
摘要翻译：公开了一种用于单片半导体器件的方法。衬底在衬底单元之间具有多个划线。提供保护膜，其上形成有对应于划线的图案化粘合剂层。保护膜以图案化的粘合剂层粘附到划线而不覆盖基板单元的方式附接并对准到基板。首先通过瞄准保护膜的激光束切割基板，并沿着划线的周边切割基板以对基板单元进行分割。因此，可以容易地除去基板单元上的保护膜的残留膜。可以消除在激光切割期间由溅射颗粒和熔融保护膜引起的基板单元的污染。基板单元的形状可以是多样的。

73. 发明授权

US07464346B2 Method for designing phase-lock loop circuits 有权
标题翻译：设计锁相环电路的方法
公开(公告)号：US07464346B2
公开(公告)日：2008-12-09
申请号：US11472199
申请日：2006-06-20
申请人： Mu-Jen Huang , Chien-Hung Chen , Chih-Chiang Chang
发明人： Mu-Jen Huang , Chien-Hung Chen , Chih-Chiang Chang
IPC分类号： G06F17/50
CPC分类号： H03L7/00
摘要： A method for designing a phase-lock loop (PLL) circuit is disclosed. The method includes the following steps. A first set of intellectual properties, each of which represents a control circuit implemented on a semiconductor substrate, is provided. A second set of intellectual properties, each of which represents a filter implemented on the semiconductor substrate, is provided. Intellectual properties are selected from the first and second sets based on a predetermined specification of the PLL circuit. The selected intellectual properties are integrated as an integrated intellectual property representing the PLL circuit, such that a layout area of the PLL circuit implemented by using the integrated intellectual property is configured based on the predetermined specification.
摘要翻译：公开了一种用于设计锁相环（PLL）电路的方法。该方法包括以下步骤。提供了第一组知识产权，其中每个都代表在半导体衬底上实现的控制电路。提供了第二组知识产权，其中每一个代表在半导体衬底上实现的滤波器。基于PLL电路的预定规格，从第一和第二组中选择智能属性。所选择的知识产权被集成为代表PLL电路的综合知识产权，使得基于预定规范配置通过使用集成知识产权实现的PLL电路的布局区域。

74. 发明授权

US07441310B2 Pliable handle on which a button can be installed 失效
标题翻译：可以安装按钮的柔韧手柄
公开(公告)号：US07441310B2
公开(公告)日：2008-10-28
申请号：US11262390
申请日：2005-10-28
申请人： Chien-Hung Chen
发明人： Chien-Hung Chen
IPC分类号： A45C13/26
CPC分类号： B25G1/102 , A45B9/02 , G05G1/06 , Y10S16/12 , Y10T16/476 , Y10T16/48
摘要： A pliable handle on which a button can be installed, includes a rigid core member, a bore in the rigid plastic core member along the longitudinal axis for locking the bottom of the central rod; a flexible outer sheath is disposed about the core member hermetically, and deformable gel is disposed between the core member and the outer sheath. A space for receiving the button which can move in radial direction is set in the core member, a through opening for button to be inserted through is disposed in the side wall of the core member, the side wall corresponds to the space; an outer annular flange is formed on the exterior surface of the core member which corresponds to the through opening; an opening is set on the flexible outer sheath for containing the outer annular flange of the core member.
摘要翻译：可以安装按钮的柔软手柄包括刚性芯构件，沿着纵向轴线的刚性塑料芯构件中的孔，用于锁定中心杆的底部; 柔性外护套围绕芯构件气密地设置，并且可变形凝胶设置在芯构件和外护套之间。用于容纳可沿径向移动的按钮的空间设置在芯构件中，用于插入的按钮用通孔设置在芯构件的侧壁中，侧壁对应于空间; 在对应于通孔的芯构件的外表面上形成外环形凸缘; 在柔性外护套上设置开口以容纳芯构件的外环形凸缘。

75. 发明申请

US20080176822A1 NOVEL COMPOSITION FOR TREATING METABOLIC SYNDROME 有权
标题翻译：治疗代谢综合征的新型组合物
公开(公告)号：US20080176822A1
公开(公告)日：2008-07-24
申请号：US12014932
申请日：2008-01-16
申请人： Chien-Hung Chen
发明人： Chien-Hung Chen
IPC分类号： A61K31/60 , A61K31/155 , A61K31/405 , A61P25/16 , A61P3/10 , A61P9/12 , A61P3/04 , A61P3/00
CPC分类号： A61K45/06 , A61K31/155 , A61K31/4045 , A61K31/616 , A61K2300/00
摘要： The invention relates to a composition that includes a first agent selected from the group consisting of an oxidative phosphorylation inhibitor, an ionophore, and an adenosine 5′-monophosphate-activated Protein kinase (AMPK) activator; a second agent that possesses anti-inflammatory activity; and a third agent that possesses serotonin activity.
摘要翻译：本发明涉及包含选自氧化磷酸化抑制剂，离子载体和腺苷5'-单磷酸激活蛋白激酶（AMPK）激活剂的第一药剂的组合物。具有抗炎活性的第二药剂; 和具有5-羟色胺活性的第三种药剂。

76. 发明申请

US20080007348A1 Method for designing phase-lock loop circuits 有权
公开(公告)号：US20080007348A1
公开(公告)日：2008-01-10
申请号：US11472199
申请日：2006-06-20
申请人： Mu-Jen Huang , Chien-Hung Chen , Chih-Chiang Chang
发明人： Mu-Jen Huang , Chien-Hung Chen , Chih-Chiang Chang
IPC分类号： H03L7/00
CPC分类号： H03L7/00
摘要： A method for designing a phase-lock loop (PLL) circuit is disclosed. The method includes the following steps. A first set of intellectual properties, each of which represents a control circuit implemented on a semiconductor substrate, is provided. A second set of intellectual properties, each of which represents a filter implemented on the semiconductor substrate, is provided. Intellectual properties are selected from the first and second sets based on a predetermined specification of the PLL circuit. The selected intellectual properties are integrated as an integrated intellectual property representing the PLL circuit, such that a layout area of the PLL circuit implemented by using the integrated intellectual property is configured based on the predetermined specification.

77. 发明申请

US20070292998A1 THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：薄膜晶体管阵列基板及其制造方法
公开(公告)号：US20070292998A1
公开(公告)日：2007-12-20
申请号：US11558451
申请日：2006-11-10
申请人： Wei-Sheng Yu , Chien-Hung Chen
发明人： Wei-Sheng Yu , Chien-Hung Chen
IPC分类号： H01L21/338
CPC分类号： H01L27/1288 , G02F1/13439 , G02F1/13458 , G02F1/136209 , G02F2001/136222 , H01L27/1214
摘要： A thin film transistor array (TFT) substrate and a method for manufacturing the same are provided. The manufacturing method needs only or even less than six mask processes for manufacturing the TFT array substrate integrated with a color filter pattern. Therefore, the manufacturing method is simpler and the manufacturing cost is reduced. In addition, the manufacturing method needs not to form a contact window in a relative thick film layer such as a planarization layer or a color filter layer, so as to connect the pixel electrode to the source/drain, thus the difficulty of the manufacturing process is effectively reduced.
摘要翻译：提供薄膜晶体管阵列（TFT）基板及其制造方法。该制造方法仅需要或甚至少于六个用于制造与滤色器图案集成的TFT阵列基板的掩模工艺。因此，制造方法更简单，制造成本降低。此外，制造方法不需要在诸如平坦化层或滤色器层的相对厚膜层中形成接触窗口，以将像素电极连接到源极/漏极，因此制造过程的难度有效减少。

78. 发明申请

US20060284957A1 Color filter and manufacturing method therefor 失效
标题翻译：滤色器及其制造方法
公开(公告)号：US20060284957A1
公开(公告)日：2006-12-21
申请号：US11450257
申请日：2006-06-09
申请人： Ching-Yu Chou , Chien-Hung Chen
发明人： Ching-Yu Chou , Chien-Hung Chen
IPC分类号： G02B5/20
CPC分类号： G02B5/201 , B41M3/003 , G02F1/133516
摘要： A color filter includes a transparent substrate, a black matrix formed on the transparent substrate, a plurality of banks superposed on the black matrix, and a color layer formed of R, G and B color portions. The black matrix defines a plurality of sub-pixels of the color filter. The banks and the black matrix enclose a plurality of spaces for respectively accommodating the R, G and B color portions. Wherein, a plurality of groups is defined, each group includes a plurality of sub-pixels of concolorous color portions, at least one channel is formed on the bank between adjacent sub-pixels of concolorous color portions in the group. In a manufacturing method for the color filter, the ink can flow over between the adjacent sub-pixels in a defined group and level through the channel, thus the uniformity of the color portions can be improved.
摘要翻译：滤色器包括透明基板，形成在透明基板上的黑矩阵，叠置在黑矩阵上的多个堤，以及由R，G和B彩色部分形成的彩色层。黑矩阵定义滤色器的多个子像素。堤和黑矩阵包围用于分别容纳R，G和B颜色部分的多个空间。其中，定义多个组，每个组包括多个彩色部分的子像素，在组中的彩色部分的相邻子像素之间的组上形成至少一个通道。在滤色片的制造方法中，油墨可以在限定的组中相邻的子像素之间流过，通过通道流过，从而可以提高颜色部分的均匀性。

79. 发明授权

US07054196B2 Method for programming P-channel EEPROM 有权
标题翻译： P通道EEPROM编程方法
公开(公告)号：US07054196B2
公开(公告)日：2006-05-30
申请号：US10728137
申请日：2003-12-03
申请人： Chien-Hung Chen , Shui-Chin Huang
发明人： Chien-Hung Chen , Shui-Chin Huang
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/0433 , H01L27/115
摘要： A method for programming a P-channel EEPROM having an N-well, a floating gate, a control gate, a P-type source region and a P-type drain region is provided. In the method, the N-well is grounded, a first positive voltage is applied to the control gate, a second positive voltage or a programming current is applied to the P-type source region, and a negative voltage is applied to the P-type drain region.
摘要翻译：提供了一种用于编程具有N阱，浮动栅极，控制栅极，P型源极区域和P型漏极区域的P沟道EEPROM的方法。在该方法中，N阱接地，第一正电压施加到控制栅极，第二正电压或编程电流施加到P型源极区域，负电压施加到P- 型漏极区域。

80. 发明授权

US06930002B1 Method for programming single-poly EPROM at low operation voltages 有权
标题翻译：在低工作电压下编程单聚EPROM的方法
公开(公告)号：US06930002B1
公开(公告)日：2005-08-16
申请号：US10709370
申请日：2004-04-29
申请人： Chien-Hung Chen , Chungchin Shih
发明人： Chien-Hung Chen , Chungchin Shih
IPC分类号： G11C16/04 , H01L21/336 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , G11C16/0416 , G11C2216/10 , H01L27/115 , H01L27/11558
摘要： A method for programming a single-poly EPROM cell at relatively low operation voltages (±Vcc) is disclosed. According to this invention, the single-poly EPROM cell includes a P-channel floating-gate transistor formed on an N well of a P type substrate, and an N-channel coupling device. The P-channel floating-gate transistor has a P+ doped drain, P+ doped source, a P channel defined between the P+ doped drain and P+ doped source, a tunnel oxide layer on the P channel, and a floating doped poly gate disposed on the tunnel oxide layer. The N-channel coupling device includes a floating poly electrode, which is electrically connected to the floating doped poly gate of the P-channel floating-gate transistor, and is capacitively coupled to a control region doped in the P type substrate.
摘要翻译：公开了一种在相对低的操作电压（±Vcc）下编程单聚EPROM单元的方法。根据本发明，单聚EPROM单元包括形成在P型衬底的N阱上的P沟道浮栅晶体管和N沟道耦合器件。 P沟道浮栅晶体管具有掺杂POD的掺杂漏极，P + SUP掺杂源，在P +掺杂的P + 漏极和P + SUP掺杂源，P沟道上的隧道氧化物层，以及设置在隧道氧化物层上的浮置掺杂多晶硅栅极。 N沟道耦合器件包括浮动多晶硅电极，其与P沟道浮栅晶体管的浮置掺杂多晶硅栅极电连接，并且电容耦合到掺杂在P型衬底中的控制区域。

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