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71. 发明授权

US08836709B2 Vector register file caching of context data structure for maintaining state data in a multithreaded image processing pipeline 有权
标题翻译：用于在多线程图像处理管道中维护状态数据的上下文数据结构的向量寄存器文件缓存
公开(公告)号：US08836709B2
公开(公告)日：2014-09-16
申请号：US13212418
申请日：2011-08-18
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06T1/00 , G09G5/36 , G06T1/20 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30 , G06F9/38 , G06F9/383 , G06T1/20
摘要： Frequently accessed state data used in a multithreaded graphics processing architecture is cached within a vector register file of a processing unit to optimize accesses to the state data and minimize memory bus utilization associated therewith. A processing unit may include a fixed point execution unit as well as a vector floating point execution unit, and a vector register file utilized by the vector floating point execution unit may be used to cache state data used by the fixed point execution unit and transferred as needed into the general purpose registers accessible by the fixed point execution unit, thereby reducing the need to repeatedly retrieve and write back the state data from and to an L1 or lower level cache accessed by the fixed point execution unit.
摘要翻译：在多线程图形处理架构中使用的经常访问的状态数据被缓存在处理单元的向量寄存器文件中，以优化对状态数据的访问并最小化与其相关联的存储器总线利用。处理单元可以包括固定点执行单元以及向量浮点执行单元，并且向量浮点执行单元使用的向量寄存器文件可用于对由固定点执行单元使用的状态数据进行缓存并转移为需要进入由固定点执行单元访问的通用寄存器，从而减少了从固定点执行单元访问的L1或更低级高速缓存重复检索和回写状态数据的需要。

72. 发明授权

US08587596B2 Multithreaded software rendering pipeline with dynamic performance-based reallocation of raster threads 失效
标题翻译：多线程软件渲染管道与基于动态性能的光栅线程重新分配
公开(公告)号：US08587596B2
公开(公告)日：2013-11-19
申请号：US12824727
申请日：2010-06-28
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F15/80
CPC分类号： G06T1/20
摘要： A multithreaded rendering software pipeline architecture dynamically reallocates regions of an image space to raster threads based upon performance data collected by the raster threads. The reallocation of the regions typically includes resizing the regions assigned to particular raster threads and/or reassigning regions to different raster threads to better balance the relative workloads of the raster threads.
摘要翻译：多线程渲染软件流水线架构基于栅格线程收集的性能数据，将图像空间的区域动态重新分配给栅格线程。区域的重新分配通常包括调整分配给特定光栅线程的区域和/或重新分配区域到不同的光栅线程，以更好地平衡光栅线程的相对工作负载。

73. 发明申请

US20130138918A1 DIRECT INTERTHREAD COMMUNICATION DATAPORT PACK/UNPACK AND LOAD/SAVE 有权
标题翻译：直接通讯通讯数据包/解压和负载/保存
公开(公告)号：US20130138918A1
公开(公告)日：2013-05-30
申请号：US13307609
申请日：2011-11-30
申请人： Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F15/76
CPC分类号： G06F15/7832 , G06F15/7825
摘要： A circuit arrangement, method, and program product for compressing and decompressing data in a node of a system including a plurality of nodes interconnected via an on-chip network. Compressed data may be received and stored at an input buffer of a node, and in parallel with moving the compressed data to an execution register of the node, decompression logic of the node may decompress the data to generate uncompressed data, such that uncompressed data is stored in the execution register for utilization by an execution unit of the node. Uncompressed data may be output by the execution unit into the execution register, and in parallel with moving the uncompressed data to an output buffer of the node connected to the on-chip network, compression logic may compress the uncompressed data to generate compressed data, such that compressed data is stored at the output buffer.
摘要翻译：一种用于在包括通过片上网络互连的多个节点的系统的节点中压缩和解压缩数据的电路装置，方法和程序产品。压缩数据可以被接收并存储在节点的输入缓冲器处，并且与将压缩数据移动到节点的执行寄存器并行地，节点的解压缩逻辑可以解压缩数据以生成未压缩数据，使得未压缩数据为存储在执行寄存器中以供节点的执行单元利用。未经压缩的数据可以由执行单元输出到执行寄存器中，并且与将未压缩数据移动到连接到片上网络的节点的输出缓冲器并行地，压缩逻辑可压缩未压缩数据以产生压缩数据，该压缩数据被存储在输出缓冲器中。

74. 发明授权

US08413166B2 Multithreaded physics engine with impulse propagation 失效
标题翻译：具脉冲传播的多线程物理引擎
公开(公告)号：US08413166B2
公开(公告)日：2013-04-02
申请号：US13212403
申请日：2011-08-18
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F3/00
CPC分类号： G06T1/20 , A63F2300/203 , A63F2300/64 , G06F9/544
摘要： A circuit arrangement and method implement impulse propagation in a multithreaded physics engine by assigning ownership of objects in a scene to individual threads and propagating impulses between objects that are in contact with one another by passing inter-thread impulse messages between the threads that own the contacting objects, while locally propagating impulses through objects using the threads to which such objects are assigned.
摘要翻译：电路布置和方法通过将场景中的对象的所有权分配给单独的线程并且在彼此接触的对象之间传播脉冲来实现多线程物理引擎中的脉冲传播，所述对象通过在拥有所述接触的线程之间传递线间脉冲消息对象，同时通过使用分配了这些对象的线程的对象来本地传播脉冲。

75. 发明授权

US08248412B2 Physical rendering with textured bounding volume primitive mapping 失效
标题翻译：具有纹理边界体积原始映射的物理渲染
公开(公告)号：US08248412B2
公开(公告)日：2012-08-21
申请号：US12407398
申请日：2009-03-19
申请人： David K. Fowler , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
发明人： David K. Fowler , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
IPC分类号： G06T15/40 , G06T1/00 , G06T15/00 , G06T15/50 , G06T15/60 , G06T15/10 , G06T15/20 , G06T15/06
CPC分类号： G06T15/06 , G06T15/40
摘要： A circuit arrangement, program product and circuit arrangement utilize a textured bounding volume to reduce the overhead associated with generating and using an Accelerated Data Structure (ADS) in connection with physical rendering. In particular, a subset of the primitives in a scene may be mapped to surfaces of a bounding volume to generate textures on such surfaces that can be used during physical rendering. By doing so, the primitives that are mapped to the bounding volume surfaces may be omitted from the ADS to reduce the processing overhead associated with both generating the ADS and using the ADS during physical rendering, and furthermore, in many instances the size of the ADS may be reduced, thus reducing the memory footprint of the ADS, and often improving cache hit rates and reducing memory bandwidth.
摘要翻译：电路布置，程序产品和电路布置利用纹理边界体积来减少与生成和使用结合物理渲染的加速数据结构（ADS）相关联的开销。特别地，场景中的图元的子集可被映射到边界体积的表面，以在物理渲染期间使用的这些表面上生成纹理。通过这样做，可以从ADS中省略映射到边界体积表面的原语，以减少在物理渲染期间生成ADS和使用ADS相关联的处理开销，此外，在许多情况下，ADS的大小可以减少，从而减少ADS的内存占用，并且经常提高缓存命中率并减少内存带宽。

76. 发明申请

US20110321057A1 MULTITHREADED PHYSICS ENGINE WITH PREDICTIVE LOAD BALANCING 失效
标题翻译：多重物理发动机具有预测负载平衡
公开(公告)号：US20110321057A1
公开(公告)日：2011-12-29
申请号：US12822615
申请日：2010-06-24
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F9/46
CPC分类号： G06F9/5083 , G06F9/505 , G06F2209/5019
摘要： A circuit arrangement and method utilize predictive load balancing to allocate the workload among hardware threads in a multithreaded physics engine. The predictive load balancing is based at least in part upon the detection of predicted future collisions between objects in a scene, such that the reallocation of respective loads of a plurality of hardware threads may be initiated prior to detection of the actual collisions, thereby increasing the likelihood that hardware threads will be optimally allocated when the actual collisions occur.
摘要翻译：电路布置和方法利用预测负载平衡来在多线程物理引擎中的硬件线程之间分配工作量。预测性负载平衡至少部分地基于对场景中对象之间预测的未来碰撞的检测，使得可以在检测到实际冲突之前启动多个硬件线程的相应负载的重新分配，从而增加在发生实际冲突时硬件线程将被最佳分配的可能性。

77. 发明申请

US20110285710A1 Parallelized Ray Tracing 失效
标题翻译：并行光线跟踪
公开(公告)号：US20110285710A1
公开(公告)日：2011-11-24
申请号：US12784525
申请日：2010-05-21
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06T15/50
CPC分类号： G06T15/06 , G06T2210/52
摘要： A method includes assigning a priority to a ray data structure of a plurality of ray data structures based on one or more priorities. The ray data structure includes properties of a ray to be traced from an illumination source in a three-dimensional image. The method includes identifying a portion of the three-dimensional image through which the ray passes. The method also includes identifying a slave processing element associated with the portion of the three-dimensional image. The method further includes sending the ray data structure to the slave processing element.
摘要翻译：一种方法包括基于一个或多个优先级为多个射线数据结构的射线数据结构分配优先级。射线数据结构包括在三维图像中从照明源追踪的射线的特性。该方法包括识别光线通过的三维图像的一部分。该方法还包括识别与三维图像的该部分相关联的从属处理元件。该方法还包括将光线数据结构发送到从属处理元件。

78. 发明申请

US20110285709A1 Allocating Resources Based On A Performance Statistic 失效
标题翻译：基于性能统计分配资源
公开(公告)号：US20110285709A1
公开(公告)日：2011-11-24
申请号：US12784522
申请日：2010-05-21
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06T15/50
CPC分类号： G06T15/005
摘要： A method includes rendering an object of a three dimensional image via a pixel shader based on a render context data structure associated with the object. The method includes measuring a performance statistic associated with rendering the object. The method also includes storing the performance statistic in the render context data structure associated with the object. The performance statistic is accessible to a host interface processor to determine whether to allocate a second pixel shader to render the object in a subsequent three-dimensional image.
摘要翻译：一种方法包括基于与对象相关联的呈现上下文数据结构，通过像素着色器渲染三维图像的对象。该方法包括测量与渲染对象相关联的性能统计量。该方法还包括将性能统计信息存储在与对象相关联的呈现上下文数据结构中。主机接口处理器可访问性能统计信息，以确定是否分配第二像素着色器以在随后的三维图像中呈现对象。

79. 发明授权

US08018466B2 Graphics rendering on a network on chip 失效
标题翻译：片上网络上的图形渲染
公开(公告)号：US08018466B2
公开(公告)日：2011-09-13
申请号：US12029647
申请日：2008-02-12
申请人： Russell D. Hoover , Jamie R. Kuesel , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
发明人： Russell D. Hoover , Jamie R. Kuesel , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
IPC分类号： G09G5/00 , G06F15/16 , G06F13/14
CPC分类号： G06T1/20
摘要： Graphics rendering on a network on chip (‘NOC’) including receiving, in the geometry processor, a representation of an object to be rendered; converting, by the geometry processor, the representation of the object to two dimensional primitives; sending, by the geometry processor, the primitives to the plurality of scan converters; converting, by the scan converters, the primitives to fragments, each fragment comprising one or more portions of a pixel; for each fragment: selecting, by the scan converter for the fragment in dependence upon sorting rules, a pixel processor to process the fragment; sending, by the scan converter to the pixel processor, the fragment; and processing, by the pixel processor, the fragment to produce pixels for an image.
摘要翻译：包括在芯片上的图形渲染（“NOC”），包括在几何处理器中接收要呈现的对象的表示; 通过几何处理器将对象的表示转换成二维原语; 由所述几何处理器将所述原语发送到所述多个扫描转换器; 由扫描转换器将原语转换成片段，每个片段包括像素的一个或多个部分; 对于每个片段：由扫描转换器根据排序规则选择片段以处理片段的像素处理器; 由扫描转换器向像素处理器发送片段; 以及由所述像素处理器处理所述片段以产生用于图像的像素。

80. 发明申请

US20110047355A1 Offset Based Register Address Indexing 审中-公开
标题翻译：基于偏移的寄存器地址索引
公开(公告)号：US20110047355A1
公开(公告)日：2011-02-24
申请号：US12546071
申请日：2009-08-24
申请人： Eric O. Mejdrich , Adam J. Muff , Robert A. Shearer , Matthew R. Tubbs
发明人： Eric O. Mejdrich , Adam J. Muff , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F9/30
CPC分类号： G06F9/342 , G06F9/30098 , G06F9/30185 , G06F9/3851
摘要： A circuit arrangement and method support offset based register address indexing, wherein register addresses to be used by an instruction are calculated using offsets to the full target register address, and the offsets are contained in the instruction and occupy less instruction space than the full address widths. An instruction may include at least one offset value that identifies a register address. During decoding of the instruction, an offset and a full target address are retrieved from the instruction, and then a register address is calculated by addition of the offset to the full target address.
摘要翻译：电路布置和方法支持基于偏移的寄存器地址索引，其中由指令使用的寄存器地址使用对全目标寄存器地址的偏移来计算，并且偏移量包含在指令中并占据比全地址宽度少的指令空间。指令可以包括标识寄存器地址的至少一个偏移值。在指令解码期间，从指令中检索偏移量和完整目标地址，然后通过将补偿相加到完整目标地址来计算寄存器地址。

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