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热词
    • 76. 发明授权
    • Pattern synchronizing circuit
    • 图案同步电路
    • US5210754A
    • 1993-05-11
    • US710522
    • 1991-06-04
    • Toshiro TakahashiTakayuki NakajimaTetsuo SotomeNoboru Akiyama
    • Toshiro TakahashiTakayuki NakajimaTetsuo SotomeNoboru Akiyama
    • H04L1/00H04J3/06H04L7/00
    • H04J3/0608
    • An Nth one of N parallel sequences of low-speed data demultiplexed by a demultiplexer from high-speed input data in synchronization with a high-speed clock is compared by N comparators with N parallel sequences of reference patterns. The N parallel sequences of reference patterns are each generated in synchronization with a frequency divided clock obtained by frequency dividing the high-speed clock into 1/N. When any of the comparators provides a disagreement output at least once, one clock pulse is eliminated by a post-clock eliminating circuit from the divided clock so that the N sequences of reference patterns are each delayed by one bit. When a counter detects that any one of the comparators does not provide the disagreement signal for n consecutive bits, the sequence of reference patterns corresponding to this comparator and the Nth sequence of low-speed data are in synchronization with each other. Clock pulses of the number corresponding to the line position of the synchronized sequence of reference patterns are eliminated by a pre-clock eliminating circuit from the high-speed clock which is applied to the demultiplexer. By this, line positions of the N parallel sequences of low-speed data are sequentially shifted so that the Nth sequence of low-speed data assumes the same line position as that of the synchronized reference pattern, and as a result, the N parallel sequences of low-speed data are synchronized with the N parallel sequences of reference patterns, respectively.